JPH084340B2 - Interface device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a signal input, a data transfer rate of the signal,
The present invention relates to an interface device that converts and outputs a signal format such as a data transfer order and a transfer data format.

[Outline of Invention]

The present invention provides a read / write memory (Random Access Memory; hereinafter referred to as RAM) that temporarily stores an input signal, a write address counter, and a write address counter in an interface device that converts and outputs an input signal. And a read address counter that operates with an asynchronous clock, and the read / write control circuit that selects and switches the RAM read cycle and write cycle in a time-division manner temporarily writes and writes input data to the RAM. By reading out this data at different time intervals from the output data and using it as an output signal, the format conversion of the signal is performed, and the optimum data transfer rate, data transfer order and transfer data form which cannot be obtained by the conventional method are obtained. Also realized an interface device that can obtain output signals. It is.

[Conventional technology]

Conventionally, as an interface device that converts the format of a signal, a direct interface device that uses RAM is used.
Memory access (Direct Memory Access; called DMA)
A circuit for performing block transfer and a circuit for performing cycle stealing have been known.

[Problems to be solved by the invention]

However, the conventional interface device has the following problems. That is, in the block transfer by DMA, reading cannot be performed in the write cycle of RAM, while writing cannot be performed in the read cycle. Therefore, for example, when the data format of the display data signal is converted by block transfer by DMA, the output display data is transferred to the display device because the reading is not performed when the input data is written in the RAM. However, there is a problem that the display cannot be performed during this period.

In cycle stealing, the RAM read and data output are performed in synchronization with the write cycle, so the transfer rate of the output signal is restricted by the transfer rate of the input signal, and an arbitrary transfer rate cannot be selected. However, there is a problem that an optimum output signal cannot be obtained.

Therefore, the present invention solves such a conventional problem, and performs the format conversion of the signal without being restricted by the data transfer rate, etc., and outputs the optimum data transfer rate, the data transfer order and the transfer data form of the output signal. It is an object of the present invention to provide an interface device that can obtain the above.

[Means for solving problems]

In order to solve the above problems, the interface device of the present invention is characterized by having the following configuration.

a) Data input circuit for inputting signals b) Reading / temporarily storing input data
Write memory c) Data output circuit that outputs signals d) Write address counter that counts the address to write input data e) Clock generation circuit that generates a clock that is asynchronous with the clock of the write address counter f) Address that reads the output data , Read address counter that counts with the clock generated by the clock generation circuit g) Read / write control circuit that selects and switches the memory read cycle and write cycle in a time-division manner [Operation] The interface configured as described above The operating principle of the device is as follows. That is, the input signal is input to the data input circuit and written in the RAM at the address designated by the write address counter according to the instruction of the read / write control circuit. The written data is read from the RAM at the address designated by the read address counter according to an instruction from the read / write control circuit and becomes an output signal by the data output circuit.

Since the signal data is temporarily stored in the RAM in this way, the data form of the input signal and the data form of the output signal can correspond to any signal form by the data input circuit and the data output circuit, respectively.

Further, the transfer order of the output signals can be easily changed by changing the counting method of the read address counter.

Further, since the read / write control circuit controls the RAM read cycle and write cycle in a time-division manner, the output signal is not interrupted even when the signal is input. Furthermore, the read / write control circuit captures a change in the read address in order to synchronize the addresses counted asynchronously with each other, and if this change overlaps with the change from the write address to the read address, a new It operates so as to send the output of the read address to the next cycle. This allows the read address counter that determines the data transfer rate of the output signal to operate at a clock that is asynchronous to the write address counter that determines the data transfer rate of the input signal. It can be set to an arbitrary value without being restricted by the transfer rate.

〔Example〕

Embodiments of the present invention will be described below in detail with reference to the drawings. As an example of a signal to be converted, a display data signal for a display device is taken, and a data signal for a CRT display device (hereinafter referred to as a video data signal) is converted to a data signal for a liquid crystal display device (hereinafter referred to as an LCD data signal). A case will be described as an example.

FIG. 1 is a block diagram of the interface device of the present invention. Reference numeral 1 is a personal computer, 2 is a video data signal output from the personal computer 1, 3 is a liquid crystal display device, and 4 is an LCD data signal for the liquid crystal display device 3. Before explaining the operation of FIG. 1, the video data signal 2
And the format of the LCD data signal 4 will be described.

Figure 2 is a format diagram of the video data signal 2. The display screen size is 640 dots in the horizontal direction and 400 lines in the vertical direction.
It is a figure in the case of in interlace mode. Reference numeral 101 denotes a display data area, and 102 denotes a data transfer order. Further, (a) is a transfer clock, (b) is a video data signal for one horizontal scanning period, and (c) is a timing chart for a video data signal for one frame period. In each case, the shaded area is a display data area. The video data signal is serial data for dot-sequential scanning of the CRT display device. In FIG. 2, areas called a back porch and a front porch shown around the display area are blanking areas for retrace of the scanning beam. The features of the video data signal are listed below.

h) Data transfer speed ・ ・ ・ 21Mbps i) Transfer clock frequency ・ ・ ・ 21M Hz j) Data transfer sequence ・ ・ ・ Intermittent data transfer including back porch and front porch period which are invalid data period k) Transfer data form ・ ・ ・Serial transfer On the other hand, FIG. 3 is a format diagram of the LCD data signal 4 in the case where the display screen size is 640 dots in the horizontal direction and 400 lines in the vertical direction as in the case of the video data signal.
Reference numeral 103 indicates a display data area, and 104 indicates a data transfer order.
Further, (a) is a transfer clock and (b) is a timing chart of an LCD data signal. Since the LCD display device is a line-sequential scanning type display device, the transferred LCD data signals are collectively output to the display pixels at the timing when the data for one line is transferred. Therefore, the LCD data signal need not be serial data as long as it can send the data of the next line within one line time, and a plurality of bits may be collectively transferred in parallel.

The example shown in FIG. 3 is an example in which four bits are collectively transferred. The following is a list of LCD data signal features.

l) Data transfer speed ・ ・ ・ 14Mbps m) Transfer clock frequency ・ ・ ・ 3.5M Hz n) Data transfer order ・ ・ ・ Upper and lower two-screen divided alternate transfer o) Transfer data form ・ ・ ・ 4 bit parallel transfer Above and second As shown in FIG. 3 and FIG. 3, the video data signal which is an input signal and the LCD data signal which is an output signal have different data transfer rates, data transfer sequences and transfer data forms.

Here, there is no great difference in the cycle (frame cycle) for transferring data for one screen between the input signal and the output signal.
Although it is around 60Hz, there is a big difference in the transfer clock frequency of both signals. There are two reasons for this. First, as shown in Fig. 2, the video data signal needs to have a blanking area called a back porch or front porch around the CRT screen, so it takes about 2 / one frame time. Data for one frame must be sent within the time of 3 or less, and the transfer clock frequency becomes high.

On the other hand, in the LCD data signal, the transfer clock frequency may be low because one frame time and the data transmission time for one frame coincide with each other. The second reason is that since the video data signal is a signal for a CRT display device using a point-sequential scanning type electron beam, it must be serial and data, whereas the LCD data signal is generally used in flat display. This is because it is a line-sequential scanning type signal that is commonly used and a plurality of bits can be collectively transferred to the segment and the driver. For example, in the 4-bit parallel transfer shown in FIG.
That is, one frame of data can be transferred in this time.

Therefore, in the case of the present embodiment, as for the output data with respect to the input data, a very small amount of display data corresponding to the difference in frame period is mixed in the data of a certain frame and the data of the next frame. However, in the case of a general personal computer, since the data of the next frame is updated to the data of one frame in only a small part of the screen, the mixed data may not be the original data. It is extremely small and does not cause any visual discomfort. Further, when the data for one screen changes at a time, the mixed data is less than the changed data, so that it is recognized that the screens are switched in an instant.

The present invention was made by paying attention to the above points, and CR
Since the video data signal for the T display device is converted into the optimum signal for the LCD display device and output, the software developed for the CRT can be used as it is to display on a display device such as an LCD. It will be possible.

In the interface device of the present invention shown in FIG. 1, a video data signal 2 output from a personal computer 1 is input to a serial / parallel conversion circuit (hereinafter referred to as S / P conversion circuit) 8 in a data input circuit 5. , Serial data is being converted into parallel data. Signal 9 is a clock signal for S / P conversion. Rock. Loop circuit (Phas
e Lock Loop; hereinafter referred to as a PLL circuit) 12. Since the PLL circuit 12 is controlled by the horizontal synchronizing signal 10, it is possible to generate the clock signal 9 having the frequency and phase suitable for inputting the video data signal 2.

In the case of this embodiment, the frequency of the clock signal 9 is 21 MHz. The horizontal back porch determination circuit / horizontal dot number counter 6 and the vertical back porch determination circuit / vertical line number counter 7 input a horizontal synchronization signal 10 and a vertical synchronization signal 11, respectively, and input a back porch period and a display data period 101 which are invalid data periods. It judges and controls so that only the display data which is effective data in the video data signal is S / P converted.

The case where one word of the RAM 16 is composed of 8 bits is explained as an example. When the data of 1 word 8 bits is input, the write address counter is counted and the read / write control circuit 17 outputs the control signals 18 and 19. Then, the data input to the S / P conversion circuit 8 is output to the data bus 14, and the write address counted by the write address counter 13 is output to the address bus 15. Then, the data is written to the RAM 16 by the control signal 20.

On the other hand, the clock generation circuit 25 generates a read clock signal 26 which is asynchronous with the clock signal 9 on the data writing side. The LCD data conversion circuit 24 in the data output circuit 22 is R
Output data read from AM16 is a 4-bit parallel LC
LCD converted to D data signal and transferred at the transfer rate according to clock 26
The data signal 4 is output. In the case of this embodiment, the transfer clock frequency is 3.5 MHz. Also, LCD control signal generation circuit
23 generates and outputs other control signals necessary for the liquid crystal display device. When the data of 1 word 8 bits is output, the read address counter 27 is counted, the read / write control circuit 17 switches the control signal 18, and the counted read address is output to the address bus 15. As a result, the RAM 16 outputs the output data to the data bus 14. The LCD data conversion circuit 24 takes in this data by the control signal 21 and converts it into an LCD data signal which is an output signal.
The read address counter matches the transfer order of the LCD data signals, and every time the address corresponding to the display data for one line is counted, the addresses are switched discontinuously alternately on the upper screen and the lower screen to count.

The above is the outline of the operation of the interface device of the present invention. Next, the operation of the read / write control circuit 17 will be described in more detail using a specific example.

FIG. 4 is a specific example of the read / write control circuit 17, and FIG. 5 is a timing chart showing the operation of the read / write control circuit. The read / write control circuit 17 is a circuit for enabling asynchronous operations on the data write side and the data read side, and is the most important component of the present invention. The outline of the operation is as follows, itemized.

p) Synchronization of the write address counter and the read address counter, which operate asynchronously with each other q) Generate a read address / write address switching signal.

In FIG. 4, 42 is a signal indicating that the read address has changed, and 35 is generated by the circuit. Circuit 35
Is a read determination circuit that determines whether to execute a memory read operation. The operation is as follows. That is, the rising edge of the clock 31 of the read address counter is differentiated to generate the signal 40. The signal 40 is input to the data of the latch 38, and the output of the latch 38 becomes the signal 42. Latch 38
The clock input 41 of is a signal generated by differentiating the falling edge of the clock 30 of the write address counter,
The signal has a pulse width narrower than the pulse width of the signal 40. Therefore, as shown in the timing chart of Fig. 5, the clock
When the rising edge of 31 and the falling edge of the clock 30 overlap, the output 42 of the latch 38 does not change because the clock 41 is at a low level. The output 42 changes after the clock 41 goes high. That is, when the switching edge of the clock 30 of the write address counter and the clock 31 of the read address counter overlap, the read determination circuit 35 operates so that the output signal 42 is output with a time delay, and a new read address is output. The output of is sent to the next cycle. Clock 30 and clock 31 are signals that are asynchronous to each other and therefore have all timing relationships.

Therefore, as in the above case, the falling edge of the clock 30 which is the switching output timing of the read address counter and the rising edge of the clock 31 which is the counting timing of the read address counter may randomly occur with a certain probability. The read determination circuit 35 outputs the new address and data at such timing.
The output of the control signal 21 for reading from the RAM 16 is sent to the next cycle so that the reading is surely performed.

In this way, the read / write control circuit 17 controls the write address counter 13 and the read address counter 27.
Even if they are operated asynchronously with each other, the read address has changed but the read control signal 21 is not output, or vice versa, it is possible to prevent malfunction of the circuit and obtain correct converted data output. .

Next, when the read address changes and the signal 42 is output, the set / reset type flip-flop 39 is set and the signal 43 changes from the low level to the high level. As a result, the reset of the flip flops 45, 46 is released and the clock input is enabled. Here, if the clock 30 of the write address counter is input, the flip-flop 45 operates and the signal 21 is output. The signal 21 is a signal obtained by synchronizing the signal indicating that the read address has changed with the clock 30 of the write address counter, and is output to the latch 28 and the LCD data conversion circuit 24 as shown in FIG. 1 and output from the RAM 16. Read data. In response to the signal 21, the latch 28 latches the address content of the read address counter 27 and outputs the address at the timing synchronized with the clock of the write address counter. Further, the LCD data conversion circuit 24 receives the signal 21 and receives the RAM 16
Capture the data output by. Returning to the explanation of FIG. 4, the flip-flop 46 and the signal 44 are for returning the set / reset type flip-flop 39 to the reset state, whereby the circuit is in the state of waiting for the change of the read address. Further, the memory cycle division circuit 47 outputs the signal 18 for switching between the read address and the write address. Signal 18 is the inverted clock of the write address counter. As can be seen from FIG. 1, when the signal 18 is low level, the write address is output to the address bus, and when the signal 18 is high level, the read address is output. The above description is shown in the timing chart of FIG. The address bus 15 is time-divided by the clock 30 of the write address counter, and the write address and the read address are alternately output. The write address becomes a new address every cycle,
As for the read address, a new read address is output in the next read cycle only when the read address counter is counted. Since the signal 21 is output only at that time, the LCD data conversion circuit takes in new output data from the RAM 16. As described above, the read / write control circuit 17 synchronizes the addresses counted asynchronously with each other, and controls the read cycle and the write cycle to be performed in a time-sharing manner. Even if the side is operated by an asynchronous clock, all write data and read data can be accurately read from and written to the memory without data loss.

Therefore, it can be applied to the field such as an LCD device for displaying a character, such as an information display terminal in which display characters cannot be recognized when data is lost or thinned out.

The read / write control circuit of FIG. 4 and the timing chart of FIG. 5 are diagrams showing the operation when a video data signal is input. Since the video data signal is not input during the back porch or front porch period,
The read / write control circuit need only perform a read cycle.

In this case, the signal 18 is fixed to the high level so that the read address is always output. Then, every time the read address counter 27 is counted, the signal 21 is output,
It may be controlled so that new data is read from the RAM 16.

The read / write circuit described here is only one example, and it is of course possible to control the read cycle and the write cycle by other methods.

As described above through the embodiments, according to the interface device of the present invention, the video data signal for the CRT display device is referred to as the LCD data signal for the liquid crystal display device,
It is possible to convert the signal into a signal having completely different data transfer rate, data transfer order, and transfer data form. This is because the interface device of the present invention inputs an input signal through a data input circuit that fits the format, temporarily writes the data in RAM and stores the data, and reads the data to generate an output signal by the data output circuit. It depends on that. Furthermore, since the read / write control circuit synchronizes asynchronous addresses, the write side of input data and the read side of output data can operate with clocks that are asynchronous with each other, and the data transfer rate of the output signal can be set to an arbitrary value suitable for the liquid crystal display device. It can be set to the value of.

Here, application of the interface device of the present invention will be described. According to the present invention as described in the embodiment, since the video data signal can be converted into the LCD data signal, the CRT display device, which is conventionally large and requires a large power,
It is possible to replace the liquid crystal display device with a thin type and capable of low power operation without changing special hardware and software. As a result, the size and weight of the display device can be easily reduced, so that it is possible to meet the needs for downsizing such as a personal computer.

In the above description, the case where the signal for the CRT display device is converted into the signal for the liquid crystal display device is shown as an example, but other display devices such as a plasma display device and an EL (Electro Lumine
The conversion of signals to a display device or the like can be performed in exactly the same manner. Further, it is also possible to convert the signal for the CRT display device into a signal for a video printer other than the display device. In this case, change the configuration of the data output circuit 22 and change the CPU (Central Processing Unit) of the video printer.
It is also possible to perform a handshake operation with the or DMA controller and take out the output data at the required timing. Such an application is possible because the interface device of the present invention outputs data asynchronously with the input.

As described above, the application range of the interface device of the present invention is extremely wide, and the input signal is not limited to the video data signal and can be applied to general data conversion.

[Advantages of the Invention] As described above, the present invention temporarily changes the input signal to RA.
It is possible to perform format conversion of data by writing and storing in M, and reading out this as an output signal, and by operating the RAM read address counter with a clock asynchronous with the write address counter, Without being restricted by the data transfer rate,
There is an effect that an optimum output signal can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram of the interface device of the present invention,
2 is a format diagram of a video data signal taken as an example of an input signal, FIG. 3 is a format diagram of an LCD data signal taken as an example of an output signal, and FIG. 4 shows a concrete example of a read / write control circuit. 5 and 5 are timing charts showing the operation of the read / write control circuit of FIG. 1 …… Personal computer 3 …… Liquid crystal display device 5 …… Data input circuit 16 …… RAM 17 …… Read / write control circuit 22 …… Data output circuit

Claims (2)

[Claims] 1. An interface device which converts the format and frequency of an input signal and outputs the converted signal, which has the following configuration. a) Data input circuit for inputting signals b) Read / write memory for temporarily storing data input from the data input circuit c) Data output circuit for reading data from the read / write memory and outputting signals d) Input data Write address counter that counts the address of the read / write memory for writing e) Clock generation circuit that generates a clock that is asynchronous with the clock of the write address counter f) The address of the read / write memory that reads the output data Read address counter that counts with the generated clock g) Divide the memory cycle in synchronization with the clock with the shorter cycle of the write address counter and the read address counter that operate with clocks that are asynchronous with each other, and write. The write cycle and the read cycle are alternately generated, and the shorter one of the read operation and the write operation is performed in each cycle, and the other operation is performed in the next cycle after the address counter is counted. Read / write control circuit 2. The interface device according to claim 1, wherein the read / write control circuit is configured as follows. a) A memory cycle dividing circuit which generates a signal for dividing the memory cycle by the clock of the write address counter and alternately allocates the write cycle and the read cycle. b) The write operation is performed for each write cycle, and the read operations are asynchronous with each other. The memory cycle is determined such that the operation is judged based on the clock of the write address counter and the clock edge of the read address counter, and the operation is performed in the next read cycle after the read address counter is counted. Readout determination circuit for controlling the division circuit