JPS5463621A - Crt display system - Google Patents

Crt display system

Info

Publication number
JPS5463621A
JPS5463621A JP12989377A JP12989377A JPS5463621A JP S5463621 A JPS5463621 A JP S5463621A JP 12989377 A JP12989377 A JP 12989377A JP 12989377 A JP12989377 A JP 12989377A JP S5463621 A JPS5463621 A JP S5463621A
Authority
JP
Japan
Prior art keywords
numbered
signals
character
pattern information
odd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12989377A
Other languages
Japanese (ja)
Inventor
Hideyuki Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12989377A priority Critical patent/JPS5463621A/en
Publication of JPS5463621A publication Critical patent/JPS5463621A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To make it possible to update character and pattern information without influences on a display screen by providing refresh memories for character and pattern information respectively.
CONSTITUTION: Refresh memory 12 to store character informaion, refresh memory 13 to store pattern information, timing circuit 22 to generate horizontal synchronizing signals, vertical synchronizing signals and signals indicating that odd-numbered and even-numbered vertical synchronizing signals are being generated, gate 18 to cause one memory output to pass synchronously with odd-numbered and even- numbered signals from circuit 22, and data resister 19 to store display contents of the memory which are outputted from gate 18 are provided. Then, stored information in register 19 is displayed on 25, and character and pattern information are rewritten individually, and the rewrite is performed synchronously with odd- numbered and even-numbered signals from circuit 22 when each information is not displayed.
COPYRIGHT: (C)1979,JPO&Japio
JP12989377A 1977-10-29 1977-10-29 Crt display system Pending JPS5463621A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12989377A JPS5463621A (en) 1977-10-29 1977-10-29 Crt display system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12989377A JPS5463621A (en) 1977-10-29 1977-10-29 Crt display system

Publications (1)

Publication Number Publication Date
JPS5463621A true JPS5463621A (en) 1979-05-22

Family

ID=15020956

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12989377A Pending JPS5463621A (en) 1977-10-29 1977-10-29 Crt display system

Country Status (1)

Country Link
JP (1) JPS5463621A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57180963U (en) * 1981-05-12 1982-11-16
JPS6063590A (en) * 1983-09-17 1985-04-11 安藤電気株式会社 Graphic pattern generator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57180963U (en) * 1981-05-12 1982-11-16
JPS6063590A (en) * 1983-09-17 1985-04-11 安藤電気株式会社 Graphic pattern generator

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