JPS5463622A - Crt display system - Google Patents

Crt display system

Info

Publication number
JPS5463622A
JPS5463622A JP12989477A JP12989477A JPS5463622A JP S5463622 A JPS5463622 A JP S5463622A JP 12989477 A JP12989477 A JP 12989477A JP 12989477 A JP12989477 A JP 12989477A JP S5463622 A JPS5463622 A JP S5463622A
Authority
JP
Japan
Prior art keywords
information
numbered
signals
characters
odd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12989477A
Other languages
Japanese (ja)
Inventor
Hideyuki Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12989477A priority Critical patent/JPS5463622A/en
Publication of JPS5463622A publication Critical patent/JPS5463622A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Computer Display Output (AREA)
  • Document Processing Apparatus (AREA)

Abstract

PURPOSE: To make it possible to update character information and information other than characters without influences on a display screen by providing refresh memories for character information and information other than characters respectively.
CONSTITUTION: Refresh memory 12 for character information storage, refresh memory 13 for information other than characters, timing circuit 22 to generate horizontal synchronizing signals, vertical synchronizing signals and signals indicating that odd-numbered and envn-numbered vertical synchronizing signals are being generated, gate 18 to cause one memory output to pass synchronousy with odd- numbered and even-numbered signals from circuit 22, and data register 19 to store display contents of the memory which are outputted from gate 18 are provided. Then, storage information in register 19 is displayed, and character information and information other than characters are rewritten individually. Then, the rewrite is performed synchronously with odd-numbered and even-numbered signals from circuit 22 when each information is not displayed.
COPYRIGHT: (C)1979,JPO&Japio
JP12989477A 1977-10-29 1977-10-29 Crt display system Pending JPS5463622A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12989477A JPS5463622A (en) 1977-10-29 1977-10-29 Crt display system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12989477A JPS5463622A (en) 1977-10-29 1977-10-29 Crt display system

Publications (1)

Publication Number Publication Date
JPS5463622A true JPS5463622A (en) 1979-05-22

Family

ID=15020982

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12989477A Pending JPS5463622A (en) 1977-10-29 1977-10-29 Crt display system

Country Status (1)

Country Link
JP (1) JPS5463622A (en)

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