JP2889258B2 - Scroll display - Google Patents

Abstract

PURPOSE:To make the display which renders a viewer a strong impression by constituting the device in such a manner that the time region assigned by the region assignment signal of a video signal is displayed. CONSTITUTION:The video signal led out of a signal generating means 12 is controlled by a control means 14 so that the time region assigned by the region assignment signal from a region assigning means 13 is delivered as the display signal to a display means 15. The processing to successively move the display image, i.e., to impart movement of, so-called, scrolling, etc., to the video is, therefore, executed by changing the region assignment signal. The display having the high degree of impression of the viewer is executed in this way.

Description

Description: TECHNICAL FIELD The present invention relates to a light emitting diode (hereinafter referred to as “LED”).
The present invention relates to a scroll display device suitably implemented as an image display device such as an electric bulletin board using the same.

2. Prior Art FIG. 10 is a block diagram showing an electrical configuration of a typical prior art display device 1. As shown in FIG. For example, from the signal generator 2 constituted by a personal computer or the like,
For example, a video signal of a still image such as a computer graphic is derived as a digital RGB video signal,
Input to the control device 3. The control device 3 is provided with a display area designation device 4 in association therewith.

The display area designating device 4 comprises, for example, two sets of date switches 4a and 4b.
4b, an area designating signal for designating an area that can be actually displayed by the display 5 is derived from the video signal from the signal generator 2, and the controller 3 is designated in this way. A display signal corresponding to the displayed display area is generated and transmitted to the display unit 5.

That is, the controller 3 counts the number of pulses of the clock signal having a frequency sufficiently higher than the horizontal synchronizing signal from the time when the horizontal synchronizing signal is derived from the video signal, and the counted value becomes equal to or larger than the set value by the dip switch 4a. At this point, the video signal is derived to the display 5 as a display signal. The display signal is derived in this manner, and when the number of pulses becomes equal to or greater than the value set by the dip switch 4b, the transmission of the display signal is stopped. Thus, only a predetermined area of the video signal can be displayed.

Problems to be Solved by the Invention In the display device 1 of the related art as described above, only the display area set by the dip switches 4a and 4b is displayed, so that the display area does not change. That is, there is no movement of the display image, and the viewer who sees the display has a small impression.

On the other hand, conventionally, a method of giving a motion to the display image by processing by software in the signal generating device 2 has been used, but this requires a huge data processing capability.

An object of the present invention is to provide a scroll display device capable of performing display with a high degree of impression to a viewer with a simple configuration.

Means for Solving the Problems The present invention provides a display panel 23 in which a plurality of display units U11 to Umn for displaying data signals DG and DR of a video signal are arranged in a matrix, and a vertical synchronization for each field of the video signal. The signal VSYNC,
A signal source for generating a horizontal synchronization signal HSYNC of a video signal and a clock signal CLK having a higher frequency than the horizontal synchronization signal HSYNC and sequentially addressing the display units U11 to Umn in each cycle of each horizontal synchronization signal A vertical direction setting circuit 32 for setting the number of horizontal synchronization signals HSYNC to be paused between the vertical synchronization signals VSYNC, and a horizontal synchronization signal HSYNC is provided. A vertical direction adjustment circuit 31 for suspending the derivation of the set number of horizontal synchronization signals HSYNC and deriving the remaining horizontal synchronization signal HSYNCa; First counters 33 and 64 for counting the synchronization signal HSYNCa, and horizontal adjustment signals AEP and A for each horizontal synchronization signal HSYNC.
First and second to determine start and end of EPa, respectively
Processing means 40 to 4 for outputting set value data X, Y which can change
3, a second counter 35 that counts the clock signal CLK between the horizontal synchronization signals HSYNC in response to the horizontal synchronization signal HSYNC and the clock signal CLK from the signal source. When the value becomes equal to or more than the first setting data X from the first setting data X to the first setting data X from the processing means 40 to 43, the count value of the second comparator 35 is equal to or more than the first setting data X from the processing means 40 to 43. , The first comparison output is given in response to the second comparator 37 for deriving the second comparison output, and the first and second comparison outputs from the first and second comparators 36 and 37. Second later
Horizontal direction adjustment signal generating circuits 38, 39, 63 for deriving horizontal direction adjustment signals AEP, AEPa that last only for a period (51-52) until a comparison output is obtained; provided for each row of the display panel 23 A row address setting means 67 for setting an address signal for designating each row; and a first counter 33, 6 provided for each row of the display panel 23.
In response to the outputs of the address counter 4 and the row address setting means 67, when the address designation signal which is the count value of the first counter 33, 64 is equal to the address number of the row address setting means 67, the address from which the address discrimination signal l41 is derived. A discrimination circuit 61, and a vertical adjustment circuit provided for each row of the display panel 23.
In response to each output of 31 and the address discriminating circuit 61, the remaining horizontal synchronization signal HS7YNCa from the vertical direction adjusting circuit 31,
When the address discrimination signal l41 is given, the circuit 62 for deriving the write pulse WRP and the duration (51-52) of the horizontal direction adjustment signals AEP and AEPa in the row to which the write pulse WRP is given Means for selecting a display unit corresponding to the duration by the clock signal CLK and displaying the data signals DG and DR of the video signal.

According to the present invention, in one field of the display panel 23, the derivation of the horizontal synchronizing signal HSYNC by the vertical direction adjusting circuit 31 is suspended by the number of horizontal synchronizing signals HSYNC set by the vertical direction setting circuit 32. Can be
In particular, in the present invention, the first and second set value data X and Y that determine the start 51 and the end 52 of the horizontal direction adjustment signals AEP and AEPa, respectively, are set to be changeable by the processing units 40 to 43. Therefore, various display states can be achieved by the moving horizontal display unit.

It is possible to perform a scroll process for sequentially moving the display image to give a motion to the video, thereby performing a display with a high impression level for the viewer.

Embodiment FIGS. 1 and 2 are block diagrams showing the basic structure of a scroll display device 11 according to an embodiment of the present invention. Referring to FIG. 1, the display device 11 includes a signal generator 12 for deriving a video output of a personal computer as a video signal, and an area designation signal for designating an area to be actually displayed in the video signal. Display area designating device
13, a control device 14 for deriving a predetermined region of the video signal as a display signal in response to a region designation signal, and the control device
And a display 15 for displaying an image based on the display signal from the display 14.

Referring to FIG. 2, a digital RGB signal from a personal computer 21 constituting the signal generating device 12 is input to a main control device 22, and a plurality of sub-control devices C1 to Cm are transmitted through the main control device 22. (Hereinafter, collectively referred to by reference numeral C). The main control device 22 and the plurality of sub-control devices C constitute the display area specifying device 13 and the control device 14.

The display panel 23 of the display 15 includes a plurality of LED units U11, U12,..., U1n; U21,.
2n; Um1,..., Umn (hereinafter collectively referred to as U), and each LED unit U is composed of, for example, 16 × 16 LEDs of two colors of green and red, respectively. Be composed. The numerical values m and n are selected according to the resolution of the video signal.

In the display panel 23 thus configured, the LED units U11 to U1n are controlled by the sub-control device C1, and
D units U21 to U2n are controlled by sub-control device C2,
As described above, the sub-control devices C in the corresponding rows are controlled by setting the LED units U in each row as one set. An address number is set in advance for each sub-control device C. The main control device 22 sends display data together with data representing the address number, and the LED units U are sequentially transmitted via the sub-control device C. Is selected and controlled.

FIG. 3 is a block diagram showing a specific configuration of the main control device 22. From the personal computer 21 via lines l1 to l5, a green data signal DG, a red data signal DR, a vertical synchronization signal VSYNC, and a horizontal synchronization signal HSYNC are output.
And a video signal composed of the clock signal CLK.

The vertical synchronization signal VSYNC shown in FIG.
The horizontal synchronization signal HSYNC shown in FIG. 2B is provided to the vertical direction adjustment circuit 31. A dip switch 32 is provided in connection with the vertical direction adjusting circuit 31, and the vertical direction adjusting circuit 31 receives the vertical synchronizing signal VSYNC as shown in FIG.
The horizontal synchronizing signal HSYNCa from which the derivation of the pulse of the horizontal synchronizing signal HSYNC is suspended for the number set by 2, for example, for 25 lines is derived.

The horizontal synchronizing signal HSYNCa from the vertical direction adjusting circuit 31 is input to the clock input terminal CLK1 of the counter 33. The vertical synchronizing signal VSYNC is input to a reset terminal CLR1 of the counter 33. The counter 33 counts up the count value by 1 every time the horizontal synchronization signal HSYNC6a is input by 16 pulses, and uses the count value as the address designation signal AD1 for selecting the sub-controller C as described above. As shown in FIG. 4D, the output is derived from the output port P1 to the line l11, for example, at 5 bits. The count value of the counter 33 is reset when the vertical synchronization signal VSYNC is input. That is, it is reset for each field.

The horizontal synchronization signal HSYNC also includes the clock signal CLK.
At the same time, it is input to the horizontal direction adjustment circuit 34. FIG. 5 is a block diagram showing a specific configuration of the horizontal direction adjustment circuit 34. The horizontal direction adjustment circuit 34 includes a counter 35,
It comprises two comparators 36 and 37, an inverting buffer 38, and an OR gate 39.

The clock signal CLK is input to a clock input terminal CLK2 of the counter 35, and the horizontal synchronization signal HSYNC
Is input to the reset input terminal RESET2 of the counter 35. The clock signal CLK has a frequency sufficiently higher than the horizontal synchronizing signal HSYNC, as shown in FIG.
The counter 35 outputs the horizontal synchronizing signal SY shown in FIG.
The number of pulses of the clock signal CLK is counted from the time when the derivation of the NC is stopped, and the counted value is input from the output port P2 to one of the input ports P11 and P21 of the comparators 36 and 37 via the buses L12 and l13. I do. The other input ports P12, P22 of the comparators 36, 37 are connected to the set value data X, Y from an input / output circuit 40 (see FIG. 3) via buses l21, l22, respectively.
Is entered.

The comparators 36 and 37 derive high-level outputs from the output ports P13 and P23 when the set value input to the input ports P11 and P21 is equal to or greater than the set value input to the input ports P12 and P22. . The output from output port P13 is applied to one input of OR gate 39 via inverting buffer 38, and the output from output port P23 is applied to the other input of OR gate 39. Thus, the count value of the counter 35 is equal to or greater than the set value input from the input port P12, and the input port P
When it is less than the set value input from 22, the OR gate
As shown in FIG. 6 (3), a low-level horizontal adjustment signal AEP is derived from 39.

Accordingly, the smaller the set value input to the input port P12, the lower the timing of the horizontal adjustment signal AEP, which is the area designation signal, as shown by the reference numeral 51 in FIG. 6 (3). The higher the set value inputted from the input port P22, the later the rising timing is delayed as indicated by reference numeral 52 in FIG. 6 (3). The display area can be moved by changing the set values input to the input ports P12 and P22 in this manner.

Referring again to FIG. 3, the input / output circuit 40 includes two output ports P31 and P32 connected to the buses l21 and l22.
And an input port P33 to which the vertical synchronization signal VSYNC is input.
These ports P31 to P33 are addressed by an address signal from the processing circuit 41 via an address bus l31, and data is input / output via a data bus l32.

In connection with the processing circuit 41, an input circuit 42 and a read-only memory (hereinafter, referred to as “ROM”) 43 are provided. The input circuit 42 starts a scroll operation of a display screen as described later. Stopping can be instructed. When the start of the scroll operation is input from the input circuit 42, the processing circuit 41 reads the rising edge of the horizontal adjustment signal AEP and the initial value of the rising timing stored in the ROM 43, and reads the initial value of the rising timing via the input / output circuit 40. Are set in the comparators 36 and 37.

FIG. 7 is a block diagram showing an electrical configuration of the sub-control device C. The sub control device C includes an address determination circuit 61
, An AND gate 62, an OR gate 63, a counter 64, an inverting buffer 65, a flip-flop 66, and a dip switch 67. The address designation signal AD1 from the counter 33 via the bus l11 is input to one input port P41 of the address discrimination circuit 61. To the other input port P42 of the address discriminating circuit 61, the address number of the sub-control device C set by the dip switch 67 is inputted.

When the address designation signal D1 via the bus l11 is equal to the address number set by the dip switch 67, the address discrimination circuit 61 outputs
A low-level output is derived from P43 to a line l41, and this output is inverted and input to one input of an AND gate 62. A
The other input of the ND gate 62 is connected to the horizontal synchronization signal HSYNCa.
Is inverted and input. Accordingly, a write pulse WRP shown in FIG. 6 (4) is derived from the AND gate 62 and applied to each of the LED units U.

The horizontal adjustment signal AEP is inverted and supplied to one input of an OR gate 63, and the other input of the OR gate 63 receives the inverted vertical synchronization signal VSYNC. Therefore, a horizontal direction adjustment signal AEPa that does not overlap with the vertical synchronization signal VSYNC is derived from the OR gate 63, and is supplied to each LED unit U.

The horizontal synchronizing signal HSYNCa is also input to a clock input terminal CLK3 of a counter 64, and the vertical synchronizing signal VSYNC is input to a reset terminal CLR3 of the counter 64. As shown in FIG. 6 (5), the count value of the horizontal synchronizing signal HSYNCa is derived from the output terminal P3 of the counter 64 to the bus 130 as the address designation signal AD2 at, for example, 4 bits. Is input to

Thus, for example, the first of the LED units U11 to U1n
The addresses are sequentially addressed from the dot to the 16th dot. The vertical synchronizing signal VSYNC is input to the input terminal CK of the flip-flop 66 via the inverting buffer 65, and the output terminal of the flip-flop 66 is connected to the input terminal D, and therefore, the output terminal Q of the flip-flop 66. , An output which is inverted every time the vertical synchronizing signal VSYNC is output is derived and supplied to each LED unit U.

Each LED unit U has two store areas, and the address designation signal AD2 shown in FIG.
, A horizontal line of the LED unit U is selected, and each dot in that line is selected by the clock signal CLK shown in FIG. 6 (1). As shown in FIG. 6 (6), the data signals DG, DR are sequentially stored in the store area which is switched for each field by the output from the flip-flop 66.

In the display device 11 configured as described above, as described above, the output ports P31 and P32 of the input / output circuit 40 of the main control device 22 are used.
By changing the set value data X and Y derived from the above, the time domain displayed on the display panel 23 of the video signal derived from the personal computer 21 can be changed. Accordingly, as shown in FIG. 8 (2) and FIG. 8 (3), each of the set value data X and Y is transferred each time the vertical synchronization signal VSYNC shown in FIG. 8 (1) is input. The image displayed on the display panel 23 is scrolled to the left by one dot every 1/60 sec. As shown.

FIG. 9 is a flowchart for explaining the operation of the processing circuit 41. At step r1, it is determined whether or not the input port P33 of the input / output circuit 40 is at the low level, that is, whether or not the vertical synchronization signal VSYNC shown in FIG. 4A is detected. Is repeated, and when the vertical synchronization signal VSYNC is detected, the process proceeds to step r2.

In step r2, the output ports P31 and P32 of the input / output circuit 40
Is updated by adding 1 to the set value data X, Y derived from the above, and these set value data X, Y are output from the output ports P31, P32 in step r3.

At step r4, it is determined whether or not the count value Y of the counter 35 input from the input port P21 of the comparator 37 is equal to or greater than the set value Ya preset by the processing circuit 41 via the input / output circuit 40. If not, the process returns to step r1. If so, at step r5, the set value data X and Y are reset to the initial values X0 and Y0, respectively, and the process returns to step r3.

In this manner, in the display device 11 according to the present invention, it is possible to give a movement to a display image without performing complicated arithmetic processing, and to give a strong impression to a viewer.
In addition, it can be implemented with a relatively simple configuration, and can be realized at low cost.

In the above-described embodiment, the rise and the rise timing of the horizontal direction adjustment signal AEP are preset in the ROM 43. However, as another embodiment of the present invention, processing is performed using a rewritable random access memory or the like. circuit
It may be configured to be resettable from the 41 side.

Further, in the above-described embodiment, the display image is configured to scroll leftward by one dot,
As still another embodiment of the present invention, a configuration may be employed in which scrolling is performed in a plurality of dots or rightward.

Furthermore, the display panel 23 is not limited to the LED, and other display means such as a liquid crystal or an electroluminescent element may be used.

According to the present invention, the number of the horizontal synchronization signals HSYNC to be paused can be set by the vertical direction setting circuit 32 by the movement of the vertical direction adjusting circuit 31. 43, horizontal adjustment signal AEP
Since the first and second set value data X and Y for respectively determining the start and end of the data can be set to be variable,
The range of the image moving in the horizontal direction can be set to a desired value, and thus various displays can be performed.

It is possible to perform a scrolling process for sequentially moving the display image to give a motion to the video, thereby performing a display that gives a strong impression to the viewer. In addition, it can be implemented with a relatively simple configuration, and can be realized at low cost.

[Brief description of the drawings]

1 and 2 are block diagrams showing a basic configuration of a display device 11 according to an embodiment of the present invention, FIG. 3 is a block diagram showing a specific configuration of a main controller 22, and FIG. FIG. 5 is a waveform diagram for explaining the operation of the device 22, FIG. 5 is a block diagram showing a specific configuration of the horizontal adjustment circuit 34, and FIG. 6 is a diagram for explaining the operation of the main control device 22 and the sub-control device C. FIG. 7 is a block diagram showing a specific configuration of the sub-controller C, FIG. 8 is a waveform diagram for explaining a scroll operation of the processing circuit 41, and FIG. 9 is an operation shown in FIG. FIG. 10 shows a display device 1 according to the prior art.
FIG. 3 is a block diagram showing an electrical configuration of the embodiment. 11 ... display device, 12 ... signal generation device, 13 ... display area designation device, 14 ... control device, 15 ... display device, 21 ... personal computer, 22 ... main control device, 23 ... display Panel, 31 Vertical adjustment circuit, 32, 67 Date switch, 33, 35, 64 Counter, 34 Horizontal adjustment circuit, 36, 37 Comparator, 39, 63 OR gate, 40 ... I / O circuit, 41 ... Processing circuit, 42 input circuit, 43 ... ROM, 61
… Address discriminating circuit, 62… AND gate, 66… Flip flop, C… Sub-controller, U… LED unit

Claims (1)

(57) [Claims] 1. A display panel 23 on which a plurality of display units U11 to Umn for displaying data signals DG and DR of a video signal are arranged in a matrix, a vertical synchronization signal VSYNC for each field of the video signal, and a video signal. A signal source for generating a horizontal synchronization signal HCYNC and a clock signal CLK having a higher frequency than the horizontal synchronization signal HSYNC and sequentially addressing the display units U11 to Umn in each cycle of each horizontal synchronization signal, A vertical direction setting circuit 32 for setting the number of horizontal synchronization signals HSYNC to be paused between the vertical synchronization signals VSYNC, and a horizontal synchronization signal HSYNC are provided, and are set by the vertical direction setting circuit 31 between the vertical synchronization signals VSYNC. A vertical adjustment circuit 31 for deriving the remaining horizontal synchronization signals HSYNCa, and deriving the remaining horizontal synchronization signals HSYNCa. First counters 33 and 64 for counting the horizontal synchronization signal HSYNCa, and horizontal adjustment signals AEP and AEP for each horizontal synchronization signal HSYNC.
Processing means 40 to 43 for outputting first and second changeable set value data X and Y for determining the start and end of a, respectively.
A second counter 35 responsive to the horizontal synchronizing signal HSYNC and the clock signal CLK from the signal source to count the clock signal CLK between the horizontal synchronizing signals HSYNC; When the value becomes equal to or more than the first setting data X from 43, the first comparator 36 for deriving the first comparison output, and the count value of the second counter 35 becomes equal to or more than the second setting data Y from the processing means 40 to 43. The second comparator 37, which derives the second comparison output, and responds to the first and second comparison outputs from the first and second comparators 36 and 37, and receives the first comparison output. Horizontal adjustment signal generation circuits 38, 39, 63 for deriving horizontal adjustment signals AEP, AEPa that last only for a period (51-52) until the second comparison output is obtained from each of the rows of the display panel 23 And a row address setting means 67 for setting an address signal for designating each row. It provided for each row of the display panel 23, a first counter 33,64
In response to each output of the row address setting means 67 and the address designation signal, which is the count value of the first counter 33, 64, is equal to the address number of the row address setting means 67, the address discrimination signal l41 is derived. And a vertical adjustment circuit 31 provided for each row of the display panel 23.
And a circuit 62 for deriving the write pulse WRP in response to the outputs of the address discriminating circuit 61 and the remaining horizontal synchronizing signal HS7YNCa from the vertical direction adjusting circuit 31 and the address discriminating signal l41. A display unit corresponding to the duration (51 to 52) of the horizontal adjustment signals AEP and AEPa in the row to which the write pulse WRP is given is selected by the clock signal CLK, and the video signal data A scroll display device comprising: means 21 and 66 for displaying signals DG and DR.