JPH02278285A - Image display control circuit - Google Patents

Abstract

PURPOSE:To display an image by a scanning line unit or to eliminate an image which is being displayed by providing a control signal generating circuit for controlling an output of data of the image in relation to a vertical synchronizing signal and an output of a comparator. CONSTITUTION:A first up-counter 12 outputs a count value of a horizontal synchronizing signal. A second up-counter 15 up-counts a numerical value of the horizontal synchronizing signal of a boundary position of a display and an erasion of an image by a vertical synchronizing signal, and a down-counter down-counts, respectively and outputs the respective count values. Subsequently, when the count value of a first up-counter 12 and the count value of a second up-counter 15 of the down-counter 16 coincide with each other, a comparator 13 generates a prescribed output, and a load control circuit 21 applies a load signal synchronizing with the vertical synchronizing signal to a second up- counter 15 and the down-counter 16. A control signal generating circuit 19 controls an output of data of the image in relation to the vertical synchronizing signal and the output of the comparator 13. In such a way, the image can be displayed by a scanning line unit, or the image which is being displayed can be erased.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is an open circuit for an image display control circuit that displays images such as characters or symbols on the screen of a television, computer display, etc. using a raster scan method. .

[Conventional technology]

FIG. 7 is a block diagram of a conventional image display control circuit of this type. The CPUI outputs coded data such as the display position of characters to be displayed on the screen and the class II characters, etc., and the data is sent via the data bus 2 to the vertical position control circuit 3.
The signal is input to each of the horizontal position control circuit 4 and the display RAM 6.

A vertical synchronizing signal VIYe and a horizontal synchronizing signal f (svc) are input to the vertical position control circuit 3, and the vertical position control circuit 3 is reset for each vertical synchronizing signal v svc.
The vertical position of the screen is detected by counting the horizontal synchronization signal HSVC after reset, and when the value matches the value corresponding to the vertical position given from the CPU 1, the vertical position signal ■ is generated by the horizontal position control circuit 4 and timing. The signals are respectively input to the circuit 5.

The horizontal position control circuit 4 receives a vertical synchronization signal Vsvc and a horizontal synchronization signal HSVC, and also receives a clock signal CL from an oscillation circuit 9 which outputs a clock signal for determining the dot size of characters to be displayed. . The horizontal position control circuit 4 is reset when the vertical position signal 2 from the vertical position control circuit 3 and the horizontal synchronization signal HS'IC are applied simultaneously, and the oscillation circuit 9 after being reset
The horizontal position of the screen is detected by counting the clock signal Ct given from . Then, the detected horizontal position and CPU
1 and the numerical value corresponding to the given horizontal position match, the horizontal position signal Ha is input to the timing generation circuit 5. The timing generation circuit 5 generates a timing signal T, 4 for display, which outputs display data of characters to be displayed on the screen, based on the input vertical position signal vA and horizontal position signal H1. AM 6, character pattern ROM 7 and output control circuit 8, respectively. The display RAM 6 stores character and color code data to be displayed, given from the CPU, and the character pattern ROM 7 uses the output of the display RAM 6 as an address to store dot data for forming character patterns. It is designed to be output. Further, the output control circuit 8 converts the dot data inputted from the character pattern ROM 7 from parallel to serial.
The converted dot data is converted into analog data, which is input to a drive circuit for displaying an image on a cathode ray tube, and a desired image is displayed at a predetermined position on the screen of the cathode ray tube.

In this way, an image consisting of, for example, six columns of characters in the horizontal direction and five lines in the vertical direction is displayed on the screen, as shown in FIG. 8(a). Note that one character is displayed as, for example, 12 dots in the horizontal direction and 16 dots in the vertical direction.

[Problem to be solved by the invention]

Incidentally, recently there has been a demand for displaying images such as characters or patterns on a screen in various ways, or for erasing the displayed image.

However, since the conventional image display control circuit described above displays a large number of characters in synchronization with the vertical synchronization signal, when erasing the character, it is necessary to erase the entire screen or one character.
There is a problem in that it cannot be erased unless it is character by character.

SUMMARY OF THE INVENTION In view of this problem, it is an object of the present invention to provide an image display control circuit that can display an image on a screen in units of scanning lines or erase the displayed image.

[Means for Solving the Problems] The image display control circuit according to the present invention includes a first up-counter that counts horizontal synchronization signals for each screen, and an initial value that defines an image display or erasing area. The count value of the first up counter and the count value of the second up counter or down counter are compared with the second up counter that counts up and the down counter that counts down in units of one screen. a control signal generation circuit that controls the output of image data in relation to the vertical synchronization signal and the output of the comparison circuit; It includes a counter and a load control circuit that outputs a load signal to be set to the down counter.

[Effect]

The first up counter outputs the count value of the horizontal synchronization signal.

The second up counter counts up the value of the horizontal synchronization signal at the boundary position between image display and erasure using the vertical synchronization signal, and the down counter counts down the value and outputs the respective count values.

The count value of the first up counter and the count of the second up counter or down counter? When j match, the comparator circuit issues a predetermined output. The load control circuit provides a load signal synchronized with the vertical synchronization signal to the second up counter and down counter. The control signal generation circuit controls the output of image data in conjunction with the vertical synchronization signal and the output of the comparison circuit.

Since the display cutoff position changes for each screen, the image appears to spread from the upper side to the lower side, or disappears from the lower side to the upper side.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments thereof.

FIG. 1 is a block diagram of an image display control circuit according to the present invention.

The CPIJ l outputs data that encodes the display position and type of characters to be displayed on the screen, and the data is sent to the vertical position control circuit 3, horizontal position control circuit 42, display RAM 6, and characters via the data bus 2. Area control circuit 10
are input to each of them. The vertical position control circuit 3 receives the vertical synchronization signal Vsvc and the horizontal synchronization signal Hsvc, and the vertical position control circuit 3 receives the vertical synchronization signal V. The vertical position of the screen is detected by counting the horizontal synchronizing signal H3VC after reset, and when it matches the value corresponding to the vertical position given from CPU 1, the vertical position signal ■4 is set horizontally. The position control circuit 4 and timing generation circuit 5 are each manually powered. The horizontal position control circuit 4 receives a vertical synchronization signal Vsvc and a horizontal synchronization signal H9VC, and also receives a clock signal CL from an oscillation circuit 9 which outputs a clock signal that determines the dot size of characters to be displayed.
is entered. The horizontal position control circuit 4 is reset when the vertical position signal V^ from the vertical position control circuit 3 and the horizontal synchronization signal flsvc are applied simultaneously.
Clock signal C given from oscillation circuit 9 after reset
The horizontal position of the screen is detected by counting L. When the detected horizontal position matches the numerical value corresponding to the horizontal position given from the CPU 1, the horizontal position signal HA is input to the timing generating circuit 5. The timing generation circuit 5 receives the input vertical position signal VA and horizontal position signal H^
The timing signal T for outputting the display data of characters to be displayed on the screen is transmitted to the display RAM 6. The data is input to the character pattern ROM 7 and the output control circuit 8, respectively.

The display RAM 6 stores the code data of the characters and colors to be displayed, given from the CPU 1, and stores the character pattern RO? The I7 outputs dot data for forming a character pattern using the output of the display RAM 6 as an address. Further, the output control circuit 8 performs parallel/serial conversion on the dot data inputted from the character pattern ROM 7, and outputs the converted dot data. This dot data is converted into analog data and input to a drive circuit for displaying an image on a cathode ray tube (not shown), and characters are displayed at a required screen position on the cathode ray tube (not shown).

FIG. 2 is a block diagram of the character area control circuit 10. 9
The horizontal synchronizing signal H87, which is the object of counting, is input to the counting input terminal of the first bit up-counter 12, and the vertical synchronizing signal Vsvc is input to the reset terminal R thereof.

This up counter 12 is reset by the vertical synchronizing signal v svc, and from the reset point, the horizontal synchronizing signal 11s
VC is counted to detect the vertical position of the screen, and the count value V^ is input to the comparison circuit 13.

The CPU i provides display image data to the display RAM 6 via the data bus 2. Further, the initial value of the lower end position of the image display area when expanding the display image is similarly given to the 9-bit register 17. Conversely, when the display image is narrowed, the initial value of the lower end position of the image display area is similarly given to the 9-bit register 18. Furthermore, the image display expands as mentioned above.

Similarly, a numerical value representing the end position of the narrowing image display is given to the position detection circuit 20. The contents of register 17 are input to the data input terminal of 9-bit second up-counter 15. The contents of register 18 are also input to the data input terminal of 9-bit down counter 16. The vertical synchronizing signal v svc to be counted is input to each count input terminal of the up counter 15 and the down counter 16, and the load signal SL from the load control circuit 21 is input to each load signal input terminal. . Furthermore, a stop signal St output from the position detection circuit 20 is input to the stop signal input terminal of each of the up counter 15 and the down counter 16. The count values of the up counters 15 and 16 are input to the switching circuit 14 and the position detection circuit 20. The 0 position detection circuit 20 receives the horizontal synchronization signal HSVC of the upper end of the image display area, which is given from cpoi and stored.
The stop signal S is output when the count value given from the up and down counters 15 and 16 matches.

In addition, the load signal S to the up and down counters 15 and 16
When t is given, the contents of registers 17 and 18 are up,
Each item is loaded separately into the down counter 15 and 16. The switching circuit 14 selects one of the count values output by the up counter 15 or the down counter 16 according to the switching control signal S given from the CPU 1 and inputs the selected value to the comparison circuit 13 . The comparison circuit 13 compares the count value from the up counter 12 and the count value input from the switching circuit 14, and outputs a pulse signal vcP if the two count values match. Pulse signal ■ of comparison circuit 13. is input to the input terminal of the control signal generation circuit 19. A vertical synchronization signal v svc is input to a synchronization signal input terminal of the control signal generation circuit 19 .

The control signal generating circuit 19 outputs the pulse signal (2) when the vertical synchronizing signal V SVC is input, and cuts off the output of the pulse signal (2) when the pulse signal Ver of the comparator circuit 13 is input. This pulse signal ■2 is the output control circuit 8
(see Figure 1). When the pulse signal v2 is manually input from the character area control circuit 10, the output control circuit 8 converts the dot data from the character pattern ROM 7 from parallel to serial using the timing signal T from the timing generation circuit 5. Output dot data. This dot data is converted into analog and applied to a cathode ray tube (not shown).

FIG. 3 is a circuit diagram of the control signal generation circuit 19 shown in FIG. 2. The vertical synchronization signal vsvc is
The signal is input to one input terminal of a first NOR circuit 30, which includes OR circuits 30 and 31 forming a flip-flop.

The comparator circuit 1 is connected to one input terminal of the second NOR circuit 31.
3 outputs v and P are input. The output of the N0Ru path 31 is input to the other input terminal of the N0Ru path 30, and the output of the NOR circuit 30 is input to the other input terminal of the NOR circuit 31. Further, the output of the NOR circuit 30 becomes the output V2 of the control signal generation circuit 19 via the inverter 32.

Next, the operation of the image display control circuit configured as described above will be explained in the fourth section.
This will be explained with reference to the timing chart shown in the figure.

First, the case where characters appear from the top of the screen as shown in FIG. 8 will be explained. CPU via data bus 2
1 to input the initial value data 0040E) into the register 17. After inputting the initial value data 00406), C
The PU 1 receives the vertical synchronizing signal V shown in FIG. 4(a) via the load control circuit 21. The load signal S shown in FIG. 4(d) is outputted in synchronization with the rise of C, and the initial value data 004 GG) shown in FIG. 4(e) is sent to the up counter 15.
Enter. At this time, the switching control signal S from CPU 1
3, the switching circuit 14 performs a switching operation to select the count value of the up counter 15.

In such a state, when display control of the first screen is started, the up counter 12 is first reset by the rising edge of the vertical synchronizing signal vsvc. The up counter 12 counts and increments the horizontal synchronizing signal f (syc) after the vertical synchronizing signal v svc falls. At this time, the output v2 of the inverter 32 of the control signal generating circuit 19 is As shown in Figure (C), it becomes "H++" in synchronization with the rising edge of the vertical synchronizing signal vsvc. Then, when the fourth pulse of the horizontal synchronizing signal HSVC is input to the up counter 12, the count value of the up counter 12 becomes 004. (16), and when the comparison circuit 13 detects that the count value of the up counter 12 and the count value of the up counter 15 given via the switching circuit 14 match, the result is shown in FIG. 4(b). As shown in , the output vcp of the comparison circuit 13 is “[I
The output voltage Vt of the inverter 32 of the control signal generating circuit 19 shown in FIG. 4C falls to 0. Then, the count value of the up counter 12 becomes 00506 due to the input of the 5th pulse horizontal solution signal H8vc)
Then, the output VeP of the comparator circuit 13 falls to "L".

On the next second screen, the up counter 15 is incremented in synchronization with the rise of the vertical synchronization signal shown in FIG. 4(a), and the count value becomes 00506).

Then, the up counter 12 operates in the same manner as on the first screen, and when the 5th pulse horizontal synchronization signal H'1'IC rises, the count value of the up counter 12 becomes 00506)
become. When the comparator circuit 13 detects that the count value of the up counter 12 and the count value of the up counter 15 given via the switching circuit 14 match, its output rises to H11. Then, the output V of the inverter 32 of the control signal generation circuit 19
2 falls to L”.

When the sixth pulse horizontal synchronizing signal Hsvc is input, the count value of the up counter 12 becomes 006θe, and the output of the comparison circuit 13 falls to ■, °°.

The output of the control signal generation circuit 19 is input to the output control circuit 8 shown in FIG. 1, and controls the output control circuit 8 to turn on or off.

That is, the output of dot data from the display RAM 6 is controlled so that an image is displayed on the screen during the period when the output 2 of the control signal generating circuit 19 is "H", and no image is displayed during the period when the output is "L". do. If there is dot data in the display RAM 6, a part of the image is first displayed from the top of the screen to the 4th grain scanning line, and then the displayed image is displayed for each scanning line at the 8th grain.
It spreads downward as shown in Figure (b).

When the lower end of the image display area is reached, the position detection circuit 20 outputs a stop signal Sv and the up counter 15
Then, the counting operation of the down counter 16 is stopped, and the image display continues until then. In this way, the image is displayed smoothly from the top of the screen to the bottom one by one scanning line by scanning line.

Next, when erasing the image displayed on the screen sequentially from the bottom of the screen scanning line by scanning line, the horizontal synchronization signal HmV shown in FIG.
Initial value data I Fl' of c (Iω is input from CP[I 1 to register 18. Initial value data IF'FQ6)
After the CPU 1 manually outputs the load signal SL shown in FIG. 4(d) via the load control circuit 21 in synchronization with the rise of the vertical synchronizing signal V3YC shown in FIG. 4(a), the CPU 1 outputs the load signal SL shown in FIG. Initial value data IFFQ6 in counter ■6
). At this time, a switching control signal S is sent from the CPU 1.

Accordingly, the switching circuit 14 performs a switching operation to select the count value of the down counter 16.

On the other hand, when erasing control of the first screen is started in the image display state, the up counter 12 is first reset by the rising edge of the vertical synchronizing signal vsvc. The up counter 12 counts and increments the horizontal synchronizing signal HSVC after the vertical synchronizing signal Vsvc falls. At this time, the output v2 of the inverter 32 of the control signal generating circuit 19 becomes °°H'' in synchronization with the rise of the vertical synchronizing signal vsvc as shown in FIG.
When the pulse-th horizontal synchronizing signal H''AVC is input, the count value of the up counter 12 becomes IFFG6).

When the comparison circuit 13 detects that the count value of the up counter 12 and the count value of the down counter 16 provided via the switching circuit 14 match, the comparison circuit 13
The output VCP of the inverter 32 of the control signal generating circuit 19 rises to "H11" and the output 2 of the inverter 32 of the control signal generating circuit 19 falls to "L".Then, the count value of the up counter 12 changes to the fourth Figure Q
The IPF becomes IPF (16) as shown in l), and Fig. 4(f)
As shown in , the output of the comparison circuit 13 falls to 'L'.

In the next second screen, the down counter 16 is activated in synchronization with the rise of the vertical synchronizing signal vsvc shown in FIG. 4(a).
is incremented, and the count value becomes 255Go. Then, the up counter 12 operates in the same manner as on the first screen, and the horizontal synchronization signal HS"IC of the 255th pulse is
rises, the count value of up counter 12 becomes OF
F Q6). When the comparison circuit 13 detects that the count value of the up counter 12 and the count value of the down counter 16 provided via the switching circuit 14 match, its output rises to "H". In synchronization with this, the output v2 of the inverter 32 of the control signal generating circuit 19 falls to "L"° as shown in FIG. 4 (6). When the 255th pulse of horizontal synchronization signal HNYC is input, the count value of up counter 12 turns OFF.Q
6), and the output VCP of the comparison circuit 13 falls to "L" as shown in FIG. 4(f).

The output of the control signal generation circuit 19 is inputted to the output control circuit 8 as described above, and the output of the control signal generation circuit 19 is "L".
”, the output control circuit 8 is controlled on and off so that no image is displayed on the screen, so after the output ■2 of the control signal generation circuit 19 shown in FIG. , the image will not be displayed.If the image is displayed to the bottom of the image display area on the screen, part of the image will start to be erased from the 256th 0 scan line at the bottom of the screen, and the down counter 16 will start to disappear. As the count value decreases, the image from the bottom of the screen changes line by line as shown in Figure 8(b).
As shown in the figure, the area will be erased and narrowed. Then, when the desired position in the image display area is reached, position detection time A'3 is detected.
20 outputs a stop signal S7, and up counter 1
5 and the down counter 16 are stopped,
The image will be erased up to that point.

Note that if the inverter 32 of the control signal generation circuit 19 is removed, the image can be erased from the top of the screen, or the image can be displayed from the bottom of the screen, as shown in FIG. 8(C). Furthermore, by setting initial value data for each of the up counter 15 and the down counter 16, and switching the switching circuit 14 to alternately select each data of the up counter 15 and down counter 16 for each screen, the eighth Figure (d
) on the screen as shown.

Images can be sequentially displayed, acquired, or erased from the bottom toward the center.

In this way, according to the present invention, images can be smoothly displayed one by one scanning line by scanning line from the top or bottom of the screen, and the displayed image can be erased.

It is possible to increase the manner in which information is conveyed through images, and
can meet the demands for multifunctionality in transmitting information.

Note that it is also possible to configure the image to be displayed during a period in which the output V2 of the control signal generation circuit 19 is at the "L11 level."

FIG. 5 is a circuit diagram of the load control circuit 21. This load control circuit 21 includes a NOR circuit 54, 3 manual NOR circuits 5
5. D flip-flop56. It includes a NANO circuit 57 and an inverter 58, and a flip-flop 51 is configured by a NOR circuit 54 and a three-way NOR circuit 55. Further, the NAND circuit 57 and the inverter 58 constitute an AND circuit 53. A load command signal A from the CPU 1 is input to one input terminal 54a of the NOR circuit 54, and a reset signal SR1 for resetting the system is input to a second input terminal 55b of the three-man power NOR circuit 55.
is input. The output of the NOR circuit 54 is input to the first input terminal 55a of the three-man power NOR circuit 55. 3 person power NO
The output S of the R circuit 55 is input to the other input terminal 54b of the NOR circuit 54 and the input terminal of the D flip-flop 56. The vertical synchronizing signal V3Ye is input to the trigger terminal T of the D flip-flop 56, and the reset signal S□ for system reset is input to the reset terminal R. D
The output terminal Q of the flip-flop 56 is connected to the NAND circuit 57.
is connected to one input terminal 57a, and the other input terminal 57b
A vertical synchronizing signal v svc is input to.

The output of NAND circuit 57 is output via inverter 58. The output side of the inverter 58 is connected to the three-person car NO.
It is connected to the third input terminal 55c of the R circuit 55.

The operation of this load control circuit 21 is as shown in the timing chart shown in FIG. When the reset signal Sat shown in FIG. 6(C) is applied, the flip-flop 51 and the D flip-flop 53 are put into a reset state.

At timing TI, CPUs 1 to 6 ('b
), when load command signal A is given, N
The output S of the flip-flop 51 by the OR circuit 54 and the three-way NOR circuit 55 becomes "I" as shown in FIG. 6(d).
(rises to ”. Then, the next vertical synchronization signal v svc
At the falling timing T2 of the vertical synchronizing signal vs"tc shown in FIG. 6(a), the output of the D flip-flop 56 goes to "H" as shown in FIG. 6(e). Furthermore, at the timing T when the next vertical synchronization signal V, V rises, as shown in FIG. 6(f).
The load signal S shown in FIG.

By using this load control circuit 21, even if the CPU 1 outputs the load command signal Ac asynchronously to the vertical synchronization signals V, , c, it is possible to output the load signal SL in synchronization with the vertical synchronization signal vsvc.

〔Effect of the invention〕

As described in detail above, according to the present invention, since an image is displayed in relation to the horizontal synchronization signal, it is possible to display an image for each scanning line, and it is also possible to erase the displayed image.

This increases the number of display modes for images, producing an excellent effect that can meet the demand for multifunctionality in which information can be transmitted in different modes.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an image display control circuit according to the present invention;
FIG. 2 is a block diagram of the character area control circuit, FIG. 3 is a circuit diagram of the control signal generation circuit, FIG. 4 is a timing chart of signals of each part of the character area control circuit, and FIG. 5 is a circuit diagram of the load control circuit. FIG. 6 is a timing chart of signals of various parts of the load control circuit, FIG. 7 is a block diagram of a conventional image display control circuit, and FIG. 8 is an explanatory diagram of an image display state. ■...CPU 2...Data bus 10...Character area control circuit 12...9-bit up counter
13...Comparison circuit 15...9 bit up counter 16...9 bit down counter 17...9
Bit register 18...9 Bit register 19...
...Control signal generation circuit 21...Load control circuit In the drawings, the same reference numerals indicate the same or equivalent parts. (a) (C) (b) (d) One drawing procedure amendment (voluntary)

Claims (1)

[Claims] (1) In an image display control circuit that displays an image in a raster scan method in relation to a vertical synchronization signal and a horizontal synchronization signal, a first up counter that is reset by the vertical synchronization signal and counts the horizontal synchronization signal; an initial value defining a display or erasing area of the image is set, a second up counter that counts up the vertical synchronization signal, a down counter that counts down the vertical synchronization signal, and a count value of the first up counter and a second up counter or a comparison circuit that compares the count value of a down counter and outputs a predetermined output if the compared count values match, and a control that controls the output of the image data in relation to the vertical synchronization signal and the output of the comparison circuit. An image display comprising: a signal generation circuit; and a load control circuit that outputs a load signal to set the initial value to the second up-counter and down-counter in synchronization with a vertical synchronization signal. control circuit.