JPS6021784U

JPS6021784U - CRT display device

Info

Publication number: JPS6021784U
Application number: JP1983113028U
Authority: JP
Inventors: 坂口　正三郎; 五十嵐　豊明
Original assignee: パイオニア株式会社
Priority date: 1983-07-22
Filing date: 1983-07-22
Publication date: 1985-02-14
Also published as: JPH0334794Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来例を示すブロック図、第２図はキャラクタ
表示例を示す図、第３図乃至第５図は第１図中の各部の
波形を示す図、第６図は本考案の一実施例を示すブロッ
ク図、第７図は第６図中の各部の波形を示す図、第８図
は本考案装置による表示例を示す図、第９図は第６図中
の一部分の変形を示す図、及び第１０図は第９図の例に
よって得られる表示例を示す図である。Ｄ−ＦＦ　１・・・、・・・第１の遅延手段、Ｄ−ＦＦ
２・；・・・・第２の遅延手段、Ｇ１・・・・・・第１
のゲー）　（ＮＡＮＤゲー）　）　、Ｇ　２−−−−−
−回路（ＮＯＲゲート）、Ｇ３・・・・・・第２のゲー
ト（ＮＡＮＤゲート）。Figure 1 is a block diagram showing a conventional example, Figure 2 is a diagram showing an example of character display, Figures 3 to 5 are diagrams showing waveforms of each part in Figure 1, and Figure 6 is a diagram showing an example of character display. FIG. 7 is a block diagram showing the embodiment, FIG. 7 is a diagram showing waveforms of each part in FIG. 6, FIG. 8 is a diagram showing an example of display by the device of the present invention, and FIG. 9 and FIG. 10 are diagrams showing display examples obtained by the example of FIG. 9. D-FF 1..., first delay means, D-FF
2.;...Second delay means, G1...First
(game) (NAND game) ), G 2------
- circuit (NOR gate), G3... second gate (NAND gate).

Claims

[Scope of utility model registration request]

In a CRT display device capable of displaying images and characters in a superimposed manner on a CRT screen, the first delay means delays a character/signal for synthesis by one clock of a character shift clock, and the first delay means a first gate which receives the output of the circuit and the character signal as input; a circuit which receives the output of the first delay means and the character signal and outputs a composite signal of both; and a circuit which delays the output of the circuit by one shift clock. and a second delay means to set the video signal to a black level by the output of the second gate which receives the output of the first gate and the output of the second delay means as inputs. CRT display device.