JPH0334794Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a CRT display device that can display images and characters in a superimposed manner on a CRT screen.

Conventionally, when displaying a character signal (including any graphical pattern) superimposed on an image projected on a CRT, the configuration shown in Figure 1 was used.

In the figure, the block indicated by the chain line 1 corresponds to a general monitor TV (in this case, it is a monochrome CRT). The video signal input from VIDEOINPUT is sent to the video amplification circuit 3 via the buffer 2, and lights up the CRT 4. On the other hand, the output of the buffer is sent to the synchronization separation circuit 5 and output as a horizontal synchronization signal (H.SYNC) and a vertical synchronization signal (V.SYNC). Each synchronizing signal is applied to each of the horizontal oscillation circuits 6 and vertical oscillation circuits 7, and drives the respective deflection coils 10 and 11 via the same output circuits 8 and 9.

The timing generation circuit 12, the character signal generation circuit 13, and the display controller 14 are circuits for generating a character signal by superimposing it on a video signal. The timing generation circuit 12 determines the display start position on the screen based on the H.SYNC from the synchronization separation circuit 5, and sends a clock corresponding to one dot on the display to the character signal generation circuit 13. The display controller 14 receives a signal from the timing generation circuit 12 and outputs data of a character to be displayed at that location to the character signal generation circuit 13 in accordance with the scanning position of the screen. The generation circuit 13 sequentially outputs the display data sent from the controller 14 using the clock received from the timing generation circuit 12.

For example, when displaying the characters "AI" as shown in Figure 2 on a CRT, No.
When scanning the scanning line, the G Yarakuta signal generation circuit 1
The waveform shown in FIG. 3 is output as the signal output No. 3. Thereafter, character signals corresponding to character 2 are output in the order of No. 3 → No. 4, etc. This character signal and the video signal shown in FIG. 4 inputted to the VIDEO INPUT are combined in a combining section 15 consisting of a diode OR to obtain the signal shown in FIG. 5. At this time, the "H" level of the character signal is set so that it becomes a white level when used as a composite video signal (FIG. 5). Therefore, CRT
On the screen displayed on the screen, characters are superimposed on the video signal.

Since the conventional character composite display was performed as described above, it had the disadvantage that if the background was bright at the time of composition, the white level of the character could not be distinguished, and the character was buried in the background image. In addition, some characters had a border behind them, but some characters are difficult to distinguish just by having a border behind them. The present invention was made in order to eliminate the above-mentioned drawbacks, and its purpose is to provide a CRT display device that forcibly inserts a black level on the left and right sides of the display character and adds borders to the display to make the characters easier to read. There is.

Embodiments of the present invention will be described below with reference to FIG. 6 and subsequent figures.

In the figure, a monitor TV section 1, a timing generation circuit 12, a character signal generation circuit 13, and a display controller 14 are basically the same as those in the conventional example. Logic has been added.

Next, the operation will be explained with reference to waveforms at various locations shown in FIG.

The character signal generating circuit 13 outputs a character signal at the rising timing of the clock (CK) sent from the timing generating circuit 12 [FIG. 6A]. D-FF1 uses the same signal as 1CK
This is a D-type flip-flop that serves as the first delay means for delaying the delay (Fig. 6B).
The NAND gate JG1 is a gate for announcing the front edge of the character dot, and the above A signal and the Q output of the flip-flop D-FF1 are input to the same gate G1, and when the A signal changes from "L" to "H" , the output of gate G1 becomes "L" for a time span of 1 CK at the rising timing of CK [Figure 6, C].
Further, the NOR gate G2 is a gate for adding a dot after the character dot, and receives the above-mentioned A signal and the Q output of the flip-flop D-FF1.
When the A signal changes from "H" to "L", the gate G2 becomes "H" at the rising timing, and as in the previous section, it becomes "H" for a time span of 1CK.
level [Figure 6, D]. D-FF2 is this C
This is a D-type flip-flop that functions as a second delay means to delay the signal by 1 CK.
E]. Additionally, NAND gate G3 and inverter G4
is a gate for synthesizing the above-mentioned front edge signal C and rear edge signal D, and the waveform shown in FIG. 6F is obtained as the final edge signal. The waveform becomes "L" level at the part where the border is attached. These signals are combined by a signal combining section 15.

Level shifter LF1 and level shifter LF2 are level shift circuits that match the character signal (white level) and border signal (black level) to the white and black levels of the video signal input from VIDEO INPUT during this synthesis. The synthesized video signal becomes as shown in FIG. 6G, and characters with black borders attached to the left and right sides of the character dots are displayed on the screen with the video signal as the background. Figure 8 shows an example of a border. In the above example, black borders were added before and after the white character dots (including arbitrary patterns), but it is also possible to reverse the white and black and add white borders before and after the black character dots. It is possible. In that case, the input logic of the level shifter circuit is inverted, and the diode of the combining section 15 is
The polarity of D ₂ and D ₃ may be reversed.

In addition, in this embodiment, a character signal is synthesized with the video signal, but in a color CRT capable of RGB driving, the character signal and border signal of the present invention are used, and the character signal and border are added in the RGB drive circuit. It is also possible. In that case, the color of the character dots and border can be set to any color by combining RGB.

Further, in this embodiment, a black level equivalent to one character dot is used as the border signal, but the width of the black level is not limited to this, and the width of the black level is 0.5 dot (FIG. 10) as shown in FIG. An example of a circuit that adds . G5 and G6 in the figure are additional gates for this purpose.

As described above, according to the present invention, because borders are added before and after the composite character by the black level,
It becomes possible to clearly display characters even when the background is bright during screen composition.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, FIG. 2 is a diagram showing an example of character display, FIGS. 3 to 5 are diagrams showing waveforms of each part in FIG. 1, and FIG. 7 is a diagram showing waveforms of various parts in FIG. 6, FIG. 8 is a diagram showing an example of display by the device of the present invention, and FIG. 9 is a partial modification of FIG. 6. 9 and FIG. 10 are diagrams showing display examples obtained by the example of FIG. 9. D-FF1...first delay means, D-FF2...
second delay means, G1...first gate (NAND gate), G2... circuit (NOR gate),
G3...Second gate (NAND gate).

Claims (1)

[Scope of utility model registration request] In a CRT display device capable of displaying a superimposed image and a character on a CRT screen, a first delay means for delaying a character signal for synthesis by one clock time of a character shift clock; a first gate receiving the output of the means and the character signal as input, a circuit receiving the character signal as input and outputting a composite signal of both, and a second delay means delaying the output of the circuit by one shift clock. . A CRT display device, characterized in that a video signal is set to a black level by the output of a second gate which receives the output of the first gate and the output of the second delay means.