JPS6051828B2 - television receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a television receiver in which a sub-screen supplied from another channel or the same channel can be inserted simultaneously on the main screen of one television receiver, and the image quality of the sub-screen can be The aim is to improve this compared to the conventional method.

The content of the present invention will be explained in detail below while comparing with the conventional example. The effect shown in FIG. 1 can be considered as an effect of blowing out images of two channels I) (2) on the same screen.

Full screen 1 of channel I and screen 2 of channel ■ are the first
In the situation shown in Figure aNb, the vertical direction (hereinafter referred to as the vertical scanning direction) and the horizontal direction (hereinafter referred to as the horizontal scanning direction) of screen 2 of channel ■ are each ln screen area, and the main screen of channel I is At 119, if you blow up at the bottom right, you will get composite screen 3. The principle of displaying such a channel screen is as follows, for example. First, the pixel signals present in one horizontal scanning period in the memory circuit are written at the sampling frequency fcw, the pixel signals of two horizontal scanning periods following this horizontal scanning period are ignored, and the above process is repeated. Perform similar writing. That is, picture element signals are sequentially written into the memory circuit in a repeating period of three horizontal scanning periods (3H). Next, when the horizontal scan of the channel ■ scans the part ■ of the composite screen 3, the signal written in the memory circuit is applied to all the horizontal scans at a frequency fcR■3fcw, which is three times the writing sampling frequency fcw. The synthesized screen 3 is obtained by reading out the signal over a period (that is, with period H) and replacing the read signal with the image signal of channel I. 5. The previously proposed television receivers described above have the following drawbacks.

For example, on screen 2 of channel ■, in the horizontal scanning direction,
If there is a striped pattern whose black level duration is close to the sampling period of 3H, the above conventional method samples only once every three times in the horizontal scanning direction, so depending on the conditions for starting writing to the memory circuit. , this striped pattern is completely ignored for writing, and as a result, an inserted screen 5 with no striped pattern is displayed. The present invention aims to improve the above-mentioned drawbacks and provide an insertion screen 7 as shown in the composite screen 6.

FIG. 2a shows the principle of signal writing according to a conventional example in relation to a normal projection screen 2. In FIG.

The hatched areas 8 to 10 represent part of the signal information consisting of the striped pattern 4 of channel 1 shown in FIG. 1b. Broken line 11-1
7 indicates the write state of pixel signals over one horizontal scanning direction, and the 3 horizontal scanning periods (3
H) Every other repetition constitutes writing across the vertical scanning line direction. Therefore, in Figure 2a, the dashed lines 11~
The writing state indicated by 17 is the shaded area 6 to 10 of striped pattern 4.
The black level does not overlap with the black level of the picture element consisting of , and therefore the black level cannot be written at all. In other words, only the inserted screen 5 without the above-mentioned striped pattern is obtained.
FIG. 2b shows the writing principle according to the present invention in a manner similar to that shown in FIG.

Similarly, the hatched areas 18 to 20 represent part of the signal information consisting of the striped pattern 4 of channel (2) shown in FIG. Dashed lines 21 to 27, dashed dotted lines 28 to 3, and dashed and double dotted lines 35 to 41 each represent a pixel signal writing shape extending in one horizontal direction. Indicates the timing of the state. First, the vertical synchronization period V with channel ■
1, three horizontal scanning periods (
It is assumed that repetition every 3FI) constitutes writing in the vertical scanning line direction. As a result of this writing, the screen information 42 consisting of the hatched areas 18 to 20 is stored in the storage means and then read out, and an inserted screen 43 as shown in FIG. In other words, the diagonal lines 18 to 2 of the striped pattern are displayed.
0 is written in states 21 to 27 in the same way as in Figure 2a.
Since the insertion screen 43 is further off, the insertion screen 43 becomes a completely white screen. In the next vertical synchronization period 112 of channel (2), repetition of diagonal lines 28 to 34 every 3H constitutes writing in the vertical scanning line direction. By this writing, the screen information 42 consisting of the diagonal lines 18 to 20 of the striped pattern is stored in the storage means and then read out, and over the vertical synchronization period V2'' of channel I, the screen information 42 shown in FIG. An insertion screen 44 as shown in FIG. 1 is displayed. That is, since the diagonal lined portions 18 to 20 of the striped pattern overlap the writings 28 to 34, the insertion screen 44 includes the black level.
In the next vertical synchronization period V3 in channel (2), repeating every 3H consisting of two-dot chain lines 35 to 41 constitutes writing in the vertical scanning line direction. By this writing, the screen information 42 consisting of the diagonal lines 18 to 20 of the striped pattern is stored in the storage means and then read out.
During the vertical synchronization period V3'' of channel I, an insertion screen 45 as shown in FIG. 3c is displayed on the composite screen. That is, as in the case of FIG.
8 to 20 overlap with the writings 35 to 41, so the insertion screen 45 includes the black level. As can be easily seen from the above explanation, dashed lines 21 to 27, dashed lines 28 to 3
4. The timing of the three different write states represented by the two-dot chain lines 35 to 41 is sequentially divided into vertical synchronization periods ■1, ■2, ■3, ■1, ■2, V3, etc. in channel ■. If returned, the read vertical synchronization period in the corresponding channel I ■1'', V2'', V3'', V1'',
The insertion screens are 43, 44, corresponding to V2'', V3''...
45, 43, 44, 45... are displayed repeatedly in sequence.

Therefore, it is possible to obtain an oblique effect as if a striped pattern were present in all vertical synchronization periods. in this way,
In the conventional example, write state timings 11 to 17 were fixed and repeated at a 3H cycle, but if the position to be written is determined and modulated for each vertical synchronization as explained in FIG. 2b, It is clear that an image quality improvement effect can be achieved. In the above explanation, the selection period for whether or not to write in the horizontal scanning direction is 3H, and therefore three writing states are sequentially modulated in the vertical scanning direction, but this number is limited to three. It goes without saying that the effects of the present invention can generally be obtained as n (an integer). FIG. 4 is a block diagram showing an embodiment of the television receiver of the present invention.

Through an antenna 46, a reception system 47 for channel I (hereinafter abbreviated as ChI), which is composed of an independent tuner, a video intermediate frequency amplification circuit, a video detection circuit, and a video amplification circuit, and a reception system for channel ■ (Ch■) 4
8, the received signals are respectively added to obtain an independent ChI video signal 49 and a Ch■ video signal 50. Block 51 is a circuit that generates vertical synchronization signal 53 and horizontal synchronization signal H 54 for Ch. Block 52 is a circuit for generating Ch.
I's vertical synchronization signal VI55 and horizontal synchronization signal HI56
This is a circuit that generates The timing block 57 receives the synchronization signals VII, H■, VI, HI as input,
This circuit generates the timing pulse system 58 that drives the memory circuit element 60. The storage circuit system 60 receives the video signal 50 as an input, and performs writing, storage, and readout according to the information from the timing pulse system 58, and performs operations such as writing, storage, and reading, which will be described in detail with reference to FIGS. 2 and 3, which are the principles of the present invention. This realizes a write judgment modulation function. The signal synthesis block 63 combines read video signal outputs 61 and 62 from the storage circuit system 60 and ChI
are synthesized by the control signal 59 from the timing block 57, and this synthesized image signal 64 is
Added to T67 to get a composite screen. Note that FIG. 4 shows a case where the memory circuit system 60 is composed of two series of memory circuits 65 and 66, and when one memory circuit 65 is in a write state, the other memory circuit 66 is in a read state, The mutual states are reversed every vertical synchronization. In order to further clarify the features of the present invention, the memory circuits 65 and 66 and the timing pulse system 58 that constitute the memory circuit system 60 will be described with reference to detailed embodiments.

FIG. 5 shows the configuration of memory circuit 65 or 66.

Block 68 is an NH (integer) bit horizontal scanning direction shift register. Block 69 contains NH bits in the horizontal scanning direction and Nv bits in the vertical scanning direction. This matrix storage section has a function of transferring pixel information in the storage section of NH bits arranged in one horizontal scanning direction in parallel in the vertical scanning direction. Block 70 is similar to block 68;
This is an NH-bit horizontal scanning direction shift register. In the write operation 71 of the input signal, the shift register 68 is operated at the signal sampling clock, that is, the write frequency Fc, and NH bits, which are the number of pixels in one horizontal scanning direction, are set as one set within one horizontal scanning period H. In order to complete, the repetition period is 1 (in the case shown in Figures 1 to 3, n =
3) is repeated. The shift operation 72 repeats the pixel information of the NH bits as a set written in the shift register 68 during the H period described above with a repetition period of ml.
and the write operation is not performed (n-1)H
The data is transferred in parallel to the first row of the matrix storage unit 69 during the period. By repeating operations 71 and 72 a total of Nv times within one vertical scanning period, NHX is applied to all of the matrix.
Writing of pixel information consisting of Nv bits can be completed.
The shift operation 73 is a reverse operation of the shift operation 72, and from the NH bit written in the Nvth row of the matrix storage section 69, pixel information corresponding to one horizontal scanning direction is transferred at a repetition period H and horizontally. The data is transferred in parallel to the shift register 70 during the synchronous blanking period. The read operation 74 reads the shift register 70 at a frequency F. By operating with R=NfCW, each NH of the shift register 70 is transferred by the transfer operation 73 as described above.
The pixel information transferred to bits is sent out as an output signal within each horizontal scanning period H. Operation 73
and 74 are repeated a total of Nv times within one vertical scanning period, NH
Reading of all pixel information consisting of XNv bits can be completed. The memory circuit 65 having blocks 68 to 70 and operations 70 to 74 shown in FIG. 5 can be realized using a charge transfer element, for example.

That is, the shift registers 68 and 70 are charge transfer delay lines consisting of NH bits, and the matrix storage section 69 is a charge transfer delay line consisting of NH bits.
It can be easily constructed by arranging ×Nv charge transfer elements. Next, regarding an embodiment in which the memory circuit 65 shown in FIG. 5 is configured using a charge transfer element, it is driven to perform the above-mentioned judgment modulation that can improve the image quality as shown in FIGS. 1 to 3. The configuration of the timing pulse system 58 that enables this function will be described below.

FIG. 6 is a timing chart that takes the case where n=3 again as an example and correlates it with the writing principle shown in FIG. 2b. Pulse systems 75, 76, 77, etc. govern the timing of write operation 71 and shift operation 72 defined in FIG. The internal structure of each pulse system 75, 76, 77 consists of pulse trains 78, 79, 80 having different properties. Each of these pulse trains 78 to 80 has a repetition period of 3H with respect to the time axis t (the horizontal synchronization period H in this case is that of Ch), and is composed of Nv pulses. ing. That is, pulse systems 75, 76, 77
correspond to writing over the vertical synchronization periods Vl, ■2, and V3 of channel (2) defined when explaining the writing principle in FIG. 2b, respectively. In the example of FIG. 6, the memory circuit system 60 consists of two memory circuits 65 and 66 as shown in FIG. 4, and supports a system in which these are mutually switched between a write state and a read state for each vertical synchronization. To do so, Vl
, V2, and V3 are set to 6V, or 3 frames. Therefore, the pulse systems 75 to 77 are pulse systems to be applied to either one of the memory circuits 65 or 66, and a pulse system obtained by shifting the phase of the pulse systems 75 to 77 by one vertical synchronization period is applied to the other memory circuit. ing. The above pulse system 75~
As can be seen from the correspondence between 77 and the vertical synchronization periods T1, V2, and V3 of channel ■, the timings 81, 82, 83, etc. in the pulse train 78 correspond to the broken lines 21, 22 in FIG. , 23, . . . corresponding to the start timing of one horizontal writing state, and similarly, each timing 84, 85, 86, . . . in the pulse train 79.
correspond to the write states represented by the dashed-dot lines 28, 29, 30 in FIG. 2, and each timing 87, 88, 89, . . . , 36, and 37 correspond to the writing states.

Further timing 81-83, 84-86, 87-89
It should also be noted that .

FIG. 7 shows that the drive pulses to be applied to the shift register 68 are constructed from timings 81 to 89 . . . generated in the pulse systems 75 to 77 .

That is, each pulse train 90, 91, 92, 93 is composed of timings 81, 82, 84, 87. Each of the pulse trains 90 to 93 has a repetition frequency Fcv,
The condition is that it is composed of pulses that are repeated NH times. Video signal 50 and pulse trains 90 to 93...
. . . are written into the shift register 68 in a portion where the data overlaps in time. On the other hand, in FIG. 6, pulse systems 94 to 95 etc. control the timing of the read operation 74 and shift operation 73 defined in FIG.

The internal structure of the pulse systems 94 and 95 consists of a pulse train 96. This pulse train 96 has a repetition period of H (the horizontal synchronization period H in this case means that of ChI since it is at the time of reading) and is composed of Nv pulses. Timings 97 to 101 present in pulse train 96
. . . is the timing for starting the shift operation 73 defined in FIG. 5 and the vertical scanning direction transfer operation of the matrix storage section 69 that occurs simultaneously. Pulse system 94~
FIG. 8 shows that the drive pulses to be applied to the shift register 70 can be constructed from the timings 97 to 101 of the pulse train 96 generated according to the conditions described above.

That is, the timings 97, 98, 99 of the pulse train 96
. . , each pulse train 102, 103, 104, . . .
is configured. The condition is that each of the pulse trains 102 to 104 is composed of pulses having a repetition frequency FcR=NfOi and a repetition number NH. The signals 105 to 10 controlled by each pulse train 102 to 104 and read out from the memory circuit 65 or 66 in this way
7 is the ChI video signal 49 and the aforementioned composite block 6
3, resulting in a composite video signal 64 as shown in FIG. 8a. The states of the read signals 105 to 107 are as follows during the read vertical synchronization period ■1'', ■2''...
It is clear from the principle of the present invention shown in FIG. 2b and FIG. FIG. 9 shows one embodiment of a modulator for generating the described pulse trains 78-80 shown in FIG. 6, with the number of different write states being n=3.

Further, FIG. 10 shows the pulses that are manually applied to the modulator at that time and the pulses generated in each part of the modulator.
Terminals 127 and 128 are input terminals, and terminals 129 and 128 are output terminals. When a timing pulse 153 of vertical synchronization V is applied to the input terminal 1/27, that is, the clock terminal of the J-K flip-flop 108, pulses 154 and 155 are generated at the Q terminal 113 and O terminal 114 of the J-K flip-flop 108, respectively. J-K flip-flop 1
Pulse 156 is applied to the Q terminal 115 of the J-K flip-flop 110, and pulse 157 is applied to the Q terminal 116 of the J-K flip-flop 110.
A pulse 158 is generated at the output terminal 117 of the D circuit 145. That is, the J-K flip-flop 108 has a divide-by-2 logic, and the J-K flip-flops 109, 110 and N
The AND circuit 145 operates as a frequency divider logic. When pulse 154 and pulse 156 are passed through AND circuit 131, pulse 159 is output to terminal 118, and pulse 154 and pulse 1 are output to terminal 118.
When 57 is passed through the AND circuit 132, a pulse 1 is output to the terminal 119.
60 connects pulses 154 and 158 to N1 circuit 133
When passed through the AND circuit 134, a pulse 161 is output to the terminal 120. When the pulse 155 and pulse 156 are passed through the AND circuit 134, a pulse 162 is output to the terminal 121.
When passed through the circuit 135, a pulse 163 is generated at the terminal 122, and when the pulse 155 and pulse 158 are passed through the AND circuit 136, a pulse 164 is generated at the terminal 123. These six types of pulses 159 to 164 are at high level for one vertical synchronization period V.
The repetition period is 6 cm, and the pulses are phase-rotated with respect to each other. Therefore, the set of pulses 159 to 161 can be used as a logical decision to select each vertical synchronization period consisting of ■1, ■2, and V3 shown in FIG.
It is clear that the set of 64 can be used as a logical decision to select each vertical synchronization period that is phase-shifted by (■) from each of the vertical synchronization periods (1), (2), and V3. Input terminal 128 i.e. J-K
When horizontal synchronization H timing pulse 165 is applied to the clock terminals of flip-flops 111 and 112,
Pulse 166 to Q terminal 124 of J-K flip-flop 111, Q terminal 125 of J-K flip-flop 112
pulse 167, output terminal 126 of NAND circuit 146
A pulse 168 is generated. That is, the JK flip-flops 111 and 112 and the NAND circuit 146 operate as a horizontal synchronization H divided-by-3 pulse generator. From the timing relationship of each pulse shown in FIG. 10, if the pulses 162 and 166 are passed through the AND circuit 137, the generated pulses will be delivered to the terminal 147, and if the pulses 163 and 167 are passed to the AND circuit 138, the generated pulses will be delivered to the terminal 147. The pulse generated at 148 connects the pulse train 79 to pulse 164 and pulse 1.
68 is passed through the AND circuit 139, it is clear that the pulses generated at the terminal 149 generate the timing for forming the pulse train 80, respectively. Therefore, terminal 147,1
By combining the pulses generated at 48 and 149 in the 0R circuit 143, a trigger-pulse system for successively generating a series of pulse systems 75, 76, and 77 can be obtained at the terminal 129. In the same way, terminals 150 and 151
, 152 are synthesized by the 0R circuit 144, a trigger pulse with one vertical synchronization phase of the above trigger pulse
A pulse system is obtained at terminal 130. Here two terminals 129 and 1
It should be noted again that the need for two output systems from the memory circuit 30 is due to the fact that the memory circuit system 60 is composed of two memory circuits 65 and 66 in FIG. According to the above embodiment, Nv per vertical scanning period is obtained as a horizontal sampling signal consisting of NH pieces at a rate of one for every three horizontal scanning lines of the television signal of channel ■.
By providing a modulator that can determine and vary which one of the three channels to select and write in each vertical scanning period when writing to the memory circuit, the channel
Since the black level signal that repeats vertically like a striped pattern is not lost and stored, when displaying an image in which the image of this channel ■ is inserted as part of the image,
It has become possible to improve image quality compared to before.

Note that in the above example, n = 3 and a set of every 3 horizontal scanning lines is used, but this n (integer) can be arbitrarily changed depending on the size of the inserted screen. Needless to say, it is necessary to change the frequency division logic of the modulator used in Although the configuration is such that one line is sequentially written from a set of three horizontal scanning lines, it is also easy to configure a modulator that uses so-called random pulses that arbitrarily select and write from a set of three horizontal scanning lines, and in this case, the above embodiment also applies. As described above, the present invention can improve image quality of a channel once stored in a television receiver that combines images of two channels and displays them on a single CRT. In each vertical scanning period, when selecting one horizontal scanning line from a set of several horizontal scanning lines, a modulator that appropriately changes the selection method prevents information loss in the vertical direction of the inserted image. , which is very useful in improving image quality.

[Brief explanation of the drawing]

Fig. 1 is a front view showing the image receiving surface of a television receiver that projects two screens on one image receiving surface, and Fig. 2 is sub-screen information for comparing and explaining a conventional example and an embodiment of the present invention. 3 is a schematic diagram of the screen according to the sub-screen information of this embodiment,
FIG. 4 is a block diagram showing an embodiment of the present invention, FIG. 5 is a schematic diagram of the functions of the memory circuit of this embodiment, FIGS. 6 and 7,
FIG. 8 is a timing chart of input/output to the storage circuit, FIG. 9 is a circuit diagram of a modulator for forming a timing pulse system, and FIG. 10 is a waveform diagram of main parts of the modulator. 47...Channel I reception system, 48.
...Channel ■ reception system, 51, 52...
・Synchronization pulse generation circuit, 57...Timing block, 63...Signal synthesis block, 65, 66
...Memory circuit.

Claims (1)

[Claims] 1 means for simultaneously receiving first and second different television signals to obtain first and second video signals; means for obtaining vertical and horizontal synchronization signals from the two video signals, respectively; a storage means for writing a video signal, a driving means for receiving the various synchronizing signals as input and generating pulses for driving the storage means, and a second video read out from the storage means by the pulses of the driving means. a combining means for inserting a signal into a part of the first video signal under the control of the pulses to form a composite image; and a projection means for projecting the output of the combining means; , when writing n horizontal scanning lines of the second television signal into the storage means N_V times per vertical scanning period at a rate of one from the n horizontal scanning lines, n horizontal scanning lines are written into the storage means N_V times per vertical scanning period. Modulation means is provided for determining which line to select from a set and further changing the selected position for each vertical scanning period, and one horizontal scanning line selected by the output of the modulation means is converted into N_H samples. 1. A television receiver characterized in that the television receiver stores data as a pixel signal.