KR920001106B1 - Color display apparatus of color led - Google Patents

Abstract

The display using color LED dot matrix type displayes image signal of TV broadcasting, graphics or overlapped image of then through a mammoth display. The displayer includes a color image unit (A) for rearranging the displaying range of color image data and synchronous signal transmitted from color image system to fit the LED display and for recording by one frames, a color graphic unit (B) for rearranging the color graphic data and synchronous signal transmitted from a color graphic system (F), an image selector (C) for selecting and transmitting the data from the color image unit (A) or the color graphic unit (B) to a LED display (93) independantely or alternatively, an interface unit (7) for generating select pulse, clock pulse and brightness pulse from the rearranged synchronous signal, and an line interface unit (8) for transmitting the pulses to a LED display drive unit (91).

Description

Color image display device of color LED

1 is a schematic schematic diagram of the present invention.

FIG. 2 is a circuit block diagram of the schematic diagram of FIG. 1 in more detail.

3 is a reference diagram of a drive control circuit and a driver of one color LED unit on the color image display unit side in FIG.

4 is a reference diagram of a color LED element on the side of the color image display part of FIG.

FIG. 5 is an exemplary embodiment showing a related configuration between a color video signal demodulated by a color decoder in color image measurement such as a VTR and a color video AD converter in FIG.

6 is a reference diagram and a sync diverter for separating a sync signal from a demodulated color image signal of the color decoder.

7 is an embodiment of a color video memory and a color graphics memory circuit in FIG.

8 is an embodiment of the first timing control logic circuit in FIG.

9 is an embodiment of the external operation control in FIG.

10 is an exemplary embodiment of an interface in FIG.

Fig. 11A is a reference diagram showing the dot arrangement in the color image display board of the color LED dot matrix.

(b) is a timing chart of driving said color image display board in (a).

* Explanation of symbols for the main parts of the drawings

A: color image part 1: color video AD converter

1a: color decoder 2: color video memory

2a: synchronous separator 3: first timing control logic

31,51: vertical synchronization setting unit 32,52: horizontal synchronization setting unit

33,53: control signal counter 34,35: decoder

35,55: address counter section B: color graphics section

4: Color Graphics Memory 4a: EGA Card

5: second timing control logic 5a: control board

C: Image selector 6a: Image graphic select circuit

61: Image selector 62: Image selector

63: graphic selector 6b: or gate

7 interface 71 luminance interface

72: line select interface 73: clock interface

8: Line Interface 9: Color LED Video Output

OC: external control unit

The present invention relates to a color image display apparatus using a video signal, which is a color LED dot matrix method rather than a color image display mediating means by a cathode ray tube of a TV receiver, and is directly visualized by a video signal of the TV broadcast. The present invention relates to a color image display apparatus of a color LED capable of reproducing a color image and graphics or a color image superimposed on a large display board of three color LEDs.

In the crowded state, the information transmission medium needs to be given a relatively large size in order to visually widen the situation of the economy such as the Olympics. In addition, in order to achieve a relatively large image display device in accordance with the above requirements, there are considerable limitations.

For example, a typical apparatus capable of reproducing a moving color image or a graphic from a color image signal is known as a TV receiver using a cathode ray tube or a monitor such as a PC. In addition, such a TV receiver or a monitor processes color and contrast corresponding to each pixel from a color image signal, and sequentially scans an electron beam horizontally and vertically on a CRT screen of an image medium to display an image, character, graphic, etc. Color images can be reproduced.

However, such image display apparatus is given by a cathode ray tube whose image reproducing medium is a CRT, and such cathode ray tube is relatively large in its own manufacture, and has physical and design constraints. It was difficult to use as a wide area and large image display device.

On the other hand, it is known that a character or graphic is designed to be displayed in a relatively large size by the dot matrix method of a personal computer (PC), a microprocessor, and the like together with the LEDs. Here, a large display panel in which LEDs are arranged in a dot-matrix method is used to change characters and graphics edited by a PC or the like, one by one, in a static state, intermittently or in whole, or locally, or mixed with several primary color graphics and characters. The display function was provided.

However, such a large display panel using LED is not desirable because it is limited to its function as a static display panel (information bulletin board, advertisement board, work order board of factories, etc.) rather than an image display board itself.

As such, a large display using a conventional LED is simply provided with only a function as a display device, and thus, a color image information transmission medium with a more vibrant and wider viewing range is possible because the image cannot be reproduced by directly receiving a color image signal like a TV receiver. It is difficult to expect a video system such as a TV, a generalized TV system, a VCR, a VTR, etc. to be compatible with a recording / playback device and to display the video.

The main object of the present invention is to provide a color image display device of a color LED, which is capable of reproducing a color image, a color image, a character, a graphic, and a dynamically moving color image such as an active photograph.

It is still another object of the present invention to receive a color image, text, or graphic data output from a monitor such as a general-purpose color TV broadcast receiver, a VTR or VCR, which is a recording / playback apparatus for video data, or a PC. It is to provide a color image display device of color LED that can be reproduced images and graphics on the LED image display board, which can ensure the richness of the software utilizing the video media.

It is still another object of the present invention to provide a color image display apparatus for a color LED, which enables the selective display of the output from the image data medium and the output from a character and graphic data output medium selectively or superimposed on a single color LED image display board. It is provided.

It is another object of the present invention to flexibly design a range in which the image data output, text and graphic data output are reproduced and displayed on the color LED image display board of the three-color LED corresponding to the pixel pixel of the TV receiver system system. The present invention provides a color image display apparatus for a color that can flexibly give a screen size for color image display.

In particular, the present invention achieves the above object, and the analog composite video signal outputted from a receiver or a VTR of an NTSC TV broadcasting system is demodulated into an R (RED) or G (GREEN) signal by a color decoder and converted into a digital signal. From a video AD converter, a color video memory for temporarily writing and reading the digital output of the video AD converter side by color and luminance, and a video AD converter for digital conversion, writing and reading of the color video memory. Color image part including signal register timing and n-level brightness control to synchronize with the synchronous signal of the first signal, first timing control logic to flexibly control vertical and horizontal synchronization, and output from a PC-side graphics card Color graphics memory which writes read-out color graphics, character data temporarily in one screen range and data to this color graphics memory side The color graphics unit is composed of a second timing control logic for synchronizing the writing with a control signal from the control board on the PC side and setting and controlling the vertical and horizontal synchronization sections in a flexible manner when the reading is performed. An image selection output unit for selectively providing a data output, and an interface for respectively interfacing vertical and horizontal synchronous clocks, line selection, and luminance outputs of a color LDE image display board drive from the first and second timing control logics; Characterized in that the color image display device of the color LED that is associated with the line interface, the color LED image output unit and the like to interface the line.

This will be described in more detail below. That is, FIG. 1 schematically shows a color image display device of a color LED according to the present invention.

In this case, the composite color video signal outputted from a conventional color TV broadcasting receiver or a color imager E such as a VTR is provided to the color video unit A, and on the other hand, a PC side, which is edited by a keyboard and a graphic mouse. The color graphic data and the synchronization signal sent out from the EGA (Enhancement Graphic Adapter Card) card 4a in the color graphics system F are supplied to the color graphics unit B.

Each of the color image unit A and the color graphic unit B is provided with its data output to the image selection unit C, and its output is directed to the drive control circuit 91 side of the color LED image output unit 9. It is provided.

In addition, the color image unit (A) is a video AD (Analog / Digital) converter (1) for converting the demodulated analog color image signal from the color decoder (1a) to digital, and the synchronization signal is separated into horizontal and vertical frequencies And a color video memory 2 capable of reading and writing the digital data of the video AD converter 1 as color image data of one screen of RED (R) and GREEN (G); When the R and G digital data is written and read out on the color video memory 2 side, a synchronous clock is provided and the vertical and horizontal synchronous sections are flexibly set and controlled by the image display range of the color LED image display board 93. The first timing control logic 3 and the like are possible.

In addition, the color graphic unit B is a color graphics memory 4 capable of writing and reading digital color data output from the EGA card 4a on the PC side for one screen, and between the vertical and horizontal driving mechanisms from the synchronization signal. The second timing control logic 5 and the like that can be stretched and controlled in the same manner.

In addition, an interface 7 is provided from the first timing control logic 3 or the second timing control logic 5 to provide a line select signal, a luminance control signal, a clock signal, and the like to the line driver 8. The output of the line driver 8 is connected to a color LED image output unit 9 including a color LED driving control circuit 91, a driver 2, and a color LED image display board 93. On the other hand, Figure 2 shows the schematic system of Figure 1 in more detail.

Here, the color image system such as VTR is connected to the analog R, G color demodulation signal demodulated by the color decoder 1a, and the horizontal and vertical registration outputs are respectively connected to the video AD converter 1 and the synchronous separator 2a. The R and G digital data outputs through the video AD converter 1 lead to a color video memory 2, and the synchronous separator 2a receives signals separated into vertical and horizontal synchronous signals for one screen. The first and second timing control logic 3 synchronizes the color data by subdividing and adjusting the vertical width and the horizontal width for one screen according to the screen pixel.

In addition, the first timing control logic 3 and the vertical synchronization setting unit 31 of the water frequency divider counter 31A and flip-flops 31a and 31b configured to reset and output the vertical synchronization signal VS to a predetermined section. Address and control of the horizontal frequency divider counter 32A for resetting and outputting the horizontal synchronization signal HS to a predetermined number, the horizontal sync setting unit 32 having the flip-flops 32a and 32b, and the color video memory 2 The control signal counter 33 of the counters 33A and 33B for providing the output, the decoder 34 for providing the R / W and the chip selector signal CS, and the timing clock of the oscillator D are connected. The address counter 35 includes an address designation counter 35A, 35B, and 35C.

In addition, in the color graphics system F such as a PC, the color graphics data output from the EGA card 4a is led to the color graphics memory 4 on the side of the color graphics section B, while the image is displayed from the control board 5a. The image graphic selection circuit 6a on the selection unit C side is followed.

In addition, the synchronization signal from the EGA card 4a leads to the second timing control logic 5 for subdividing and adjusting the vertical width and the horizontal width for one screen and generating various R / W, CS, and addresses. The second timing control logic 5 is a numerical division counter 51A and flip-flops 51a and 51h which also reset the vertical synchronization signal, such as the first timing control logic 3 on the color image unit A side, by resetting the predetermined interval. ), A vertical synchronous setting unit 51 of the configuration, a horizontal divider counter 52A for resetting and outputting a horizontal synchronous signal to a predetermined number, a horizontal synchronous setting unit 52 of the flip-flop 52a, 52b, and the color The address of the graphics memory 4 and the control signal counter 53 by the counters 53A and 53B of the control output generation, the decoder 54 and the address for providing the R / W signal, the chip select signal CS, and the like. The address counter part 55 etc. by the designated counter 55A, 55B, 55C are comprised, respectively.

In the first and second timing control logics 3 and 5, the overlapping control of the display screen and the color graphics memory between the flip-flops 31a, 31b, 51a, and 51b on the vertical synchronization setting units 31 and 51, respectively. 4) Pause the graphic output data from 4), control to select only one color video and color image, and memory load control when one screen is written to the color video memory (2) and the color graphics memory (4), respectively. The external operation control part OC including these is provided.

The image selector C between the output of the color graphic memory 4 and the color image memory 2 includes an image graphic selector 61, an image selector 62, and a graphic selector 63. The selectors 62 and 63 are capable of performing selective color image or alternating output of color graphic, color image and color graphic data by the image graphic selection circuit 6a with selection control from the control board 5a on the PC side. The outputs of the selectors 62 and 63 provide the R and G color data to the driving circuit 91 of the color LED image display unit 9 via the or gate 6b.

In addition, the shift registers 71a and 71b shifted to a horizontal synchronization signal and a counter 71A receiving two inputs from the flip-flop 31b and the timing clock providing oscillator D on the first timing control logic 3 side. And a luminance interface 71 as 71c), and a counter 72A connected to two inputs from the flip-flop 32b on the side of the first timing control logic 3 and the oscillator D, and an output thereof. The line select interface 72 is composed of a counter 72B and a decoder 72a connected to the counter 72A, and also connected to the counter 73A connected to the two inputs from the flip-flop 32b and the oscillator D and an output thereof. The clock interface 73 is composed of the counters 73B and 73C and the decoders 73a, 73b and 73c.

The output of the interface 7 including the luminance interface 71, the line select interface 72, the clock interface 73, and the like are respectively supplied to the line driver control circuit 91 on the color LED image display unit 7 side driving control circuit 91. Provided via (8).

In addition, the color LED image display unit 9 is constituted by a plurality of color LED units 9a, and the color LED unit 9a is arranged in a row with a color LED unit 93a that forms 16 x 16 dots as shown in FIG. The row drivers RV ₁ and RV ₂ of the column and row ROW, the driver 91a by the column driver CD ₁ , the R data controller RDC, the G data controller GDC, and the clock CK are A drive control circuit 91a including provided counters COa, COb, decoder DE, and the like is configured to drive a 16 × 16 dot color LED unit 93a. External inputs such as R, G data, line select signal SE, luminance signal BR, clock CK, reset terminal RT, and the like are connected.

On the other hand, Figure 4 shows a known color LED element 90 used in the present invention. Here, G color chip 90a generating green G color light, green when emitting light on the common chip 90b side, and red when emitting light on the R color chip 90c and common chip 90b side, and they are lit at the same time. When the amber (A) (A) is output. Therefore, the combined colors of various colors can be expressed by combining and subtracting the luminance of these R, G, and A colors.

On the other hand, Fig. 5 shows the embodiment circuit for outputting digital data from the video AD converter 1 to the demodulated color video signal from the color video system E output such as VTR via the color decoder 1a in the present invention. It was.

In this case, the color image signal demodulated from the color decoder 1a is applied to the color image input terminal CIS, which is connected to the video AD converter (O ₁ ) and the signal comparison operation amplifier O ₂ . 1) and its output is provided as a 4-digit data output (D ₀ -D ₃ ), wherein the video AD converter 1 is provided with an oscillating circuit (CT) and a counter (CK ₁ ) provided to the counter (CO ₁ ). It is a configuration that is output in synchronization with.

6, the synchronous signal output from the color decoder 1a is divided into horizontal and vertical synchronous signals VS and HS by the synchronous separator 2a to provide the output to the first timing control logic 3. The circuit is shown.

Here, mono multi (M _1, M ₂₎ of the synchronization separator (2a) a signal separator (SS) of the synchronization signal end (SP) from the transistor (Q _1, Q ₂₎ circuit, to remove the horizontal pulses in the vertical frequency range The vertical synchronous output circuit VS ₀ is included.

7 illustrates the circuit of the color image memory 2 and the color graphics memory 4 in more detail in FIG. Here, the data output D ₀ aD ₃ a of the video AD converter 1 is input to the R or G memory IC 21-24, and the address A ₀ aA ₁₂ a of this memory IC 21-24. Is selected and provided by the video graphic selector 6a in the video graphic selector 61 of the image selector C, and is provided with a chip select signal stage CS or the like.

The data output D ₀ aD ₃ a is applied to the direct image selector 62 and provided to the data input of the memory ICs 21-24. In addition, the image selector 62 is provided with a selection control stage IS for selecting an output at the time of reading the memory ICs 21-24 and an output provided directly to the image selector 62, and an output of the image selector 62. A stop control stage (CH) for stopping the entire surface is provided, and the image selector 62 outputs the synchronous clock data D´ provided from the first or second timing control logic (3, 5) side of the comparator (CP). ₀ -D ' ₃ ) to the side of the orate 6b.

The video memory ICs 21-24, the image selector 62, the comparator CP, and the like each have the same circuit configuration for the R and G colors. The color graphics memory 4 is also provided with graphic memory ICs 41-44 and graphic selector 63 and outputs of the graphic selector 63 for the R and G colors to the orifice 6b. The graphic memory ICs 41-44 are each provided with the graphic color data inputs D ₀ bD ₃ b and R from the EGA card 4a and the address A ₀ bA ₁₂ b selected and provided by the video graphic selector 61, respectively. / W, CS control stage, etc. are provided.

8 shows only the circuit of the first timing control logic 3 side in more detail in the present invention. Here, the vertical synchronization setting section 31 includes a binary counter 31a for setting the vertical synchronization section, and a period setting selection section 31d and a flip-flop 32a reset gate 31c on its output side. Similar to the vertical synchronization setting unit 31, the horizontal synchronization setting unit 32 also has a period setting selection unit 32d with the counter 32A and the flip-flops 32a and 32b, and the reset gate of the flip-flop 32a ( 32c) and an output gate 32e are provided.

In addition, from the oscillator D including the preliminary frequency dividing counter CO ₂ and the pulse delay gate, the address counter 35 by the counters 35A, 35B, 35C is provided with a predetermined clock, whereby the address output is performed. (A ₀ aA ₃ a), and on the other hand, in the vertical synchronization setting section 31, the vertical synchronization is reset to the synchronization section signal in which the vertical synchronization is abbreviated, and the horizontal synchronization signal (HS) is input to the address output (A ₉ aA). ₁₂ a) and the output synchronization data _(D'0 -D' ₃₎ has a counter (33A, 33B) to the control signal, the counter unit 33 consisted offering.

On the output side of the counter 33, the decoder 34 is controlled via the gate 34a to the output of the flip-flop 31b on the side of the vertical synchronization setting unit 31, and the output is R / with a NAND gate. It is provided with W ₁ -R / W ₁₆ signals and chip select signals (CS ₁ -CS ₁₆ ).

9 shows an external operation control unit OC which can be adjusted by automatic control by a program on the PC side or by an external manual operation switch. Here, the PT stage for temporarily fixing the graphic data on the color graphics memory 4 side when providing the overlapped screen of the color image and the color graphic, the V / G stage for displaying only one color image or color graphic, and one screen A JK flip-flop (JK) and a D flip-flop (DF) are provided for the LD stages of data memory control for performing the above functions with these control input stages (PT, V / G, LD) and the vertical synchronization signal VS. ₁ , DF ₂ , DF ₃ ) and various gates, and W connected from the output of the flip-flop 31b on the vertical synchronization setting part 31 side of the first timing control logic 3; G and reference clock ckb from the output of the flip-flop 32b on the horizontal synchronization setting section 32, four inputs of the horizontal synchronization signal HS, and GIVS and GCA from the second timing control logic 5 side of the color graphics section B. Graphic control signal line to selectively output 4 inputs, 4 GCLK and 4 GHS A trough VGS is provided. 10 shows the circuit of the interface 7 in FIG. 2 in more detail.

Here, the horizontal synchronous clock CA provided from the flip-flop 32b of the horizontal timing setting unit 32 on the first timing control logic 3 side and the clock pulse CKb and vertical synchronous setting provided from the oscillation D side. Clock pulses CK as the clock interface 73 of the counters 73A, 73B and 73C and the decoders 73a, 73b and 73c, respectively, from the vertical section synchronization pulses IVS provided to the negative side 31 flip-flop 31b. ₁ -CK ₂₀ is provided, and the line select pulses SE ₁ -SE ₁₀ are provided to the counters 72A and 72B and the select interface 72 of the decoder 72a, and the counters 71A and the shift register. Luminance pulses BR _1- BR ₂₀ are provided from the luminance interface 7 of 71a, 71b, 71c, respectively.

In the luminance interface 71, the horizontal synchronization signal HS is converted into a predetermined luminance width through the mono multi-M ₃ , which is output through the output and the or gate on the shift registers 71a, 71b, and 71c. The configuration provided as an output.

The present invention of such a configuration is as follows. That is, in the normal color image system E, the NTSC color edited and recorded video data from the main body such as the TV receiver side antenna or the VTR performs the video reproduction operation on the device side, and the CRT expresses the video output. .

In addition, the color image signal generated by the reproduction operation is demodulated through the color decoder 1a on the side of the color image storage unit A, and the color image signal is R, G through the color AD converter 1. Color data, synchronization signal, and luminance data can be obtained respectively.

Therefore, the synchronizing signal is divided into a horizontal synchronizing signal (e.g., 15.75 KHZ) and a vertical synchronizing signal (e.g., 60HZ) via the synchronizing separator 2a of the second embodiment. After the synchronization signal inputted to the stage SP is separated by the signal separator SS of the transistors Q ₁ and Q ₂ , only the horizontal synchronization signal HS and the horizontal synchronization signal loaded in the vertical synchronization section are mono-multi ( M ₁ and M ₂ are removed by the vertical synchronous output circuit VSO to output the vertical synchronous signal VS.

The horizontal and vertical synchronous signals HS and VS filtered by the synchronous separator 2a are period-setting selectors 31d as shown in FIG. 8 in the horizontal and vertical synchronous setting units 31 and 32 on the first timing control logic 3 side. 32d and the flip-flops 31a and 32a reset gates 31c and 32c set the number of vertical sections and horizontal pulses.

In this case, for example, as shown in FIG. 3, the color LED image display plate 93 has 16 × 16 color LED elements 90 as one color LED unit 93a, and the color LED unit 93a is columned. Assuming that the color LED display board 93 is 14-16 lines in a row and 20 rows in a row, the column pixel is 16 × 20 = 320 and the row pixel is 16 × 14 = 224. In addition, since the color LED unit 93a forms one line as 20 pieces per line, the color LED unit 93a is 14 to 16 lines in the above-described embodiment of the present invention.

Therefore, when scanning one line, the line selection requires 14 sequential countings per screen at the same time as 320 counting. Accordingly, the vertical synchronous signal VS is made of one pixel of the vertical synchronous signal VS required for the color LED image display plate 93 with essentially fewer pixels in proportion to the dot matrix CRT. The period setting selectors 31d and 32d respectively reduce the width of one section of the vertical signal and the number of horizontal signals in consideration of the width and the number of rows and columns of the image display plate 93 of the color LED. By the timing signals set by the vertical and horizontal synchronization setting units 31 and 32 of the first timing control logic 3, color data passing through the color video AD converter 1 is written to the color video memory 2 side. It is used as a control signal to be read out. Here, the address counter 35 of the first timing control logic 1 writes the color data into the color video memory 2 side by one screen. A ₀ aA ₀ a), and at the control signal counter 33 and decoder 34, the clock data D ′ ₀ -D ′ ₃ , the address A ₉ aA ₁₂ a and the horizontal synchronization setting unit ( 32) side output gate (32e), the read / write control signal (R / W ₁ -R / W is controlled to _16), a chip select signal (CS ₁ -CS ₁₆₎ is provided each side of the color video memory (2) .

Therefore, the various control signals of the first timing control logic 3 side are R and G color video memories having color screen data D ₀ aD ₃ a provided from the color video AD converter 1 side as shown in FIG. It is provided when writing to the (2) side and reading color data from the color video memory (2) side.

The second timing control logic 5 side of the graphics system performs the same operation as the first timing control logic 3 side, except that color graphics data and a synchronization signal are directly received from the EGA card 4a as a digital output. It only differs in that point.

Here, as shown in FIG. 7, A ₀ bA ₁₂ b is provided from the second timing control logic 5, and the R / W signal and the chip select signals CS _1- CS ₁₆ are provided, respectively. Therefore, the data D ₀ aD ₉ a inputted from the color video AD converter 1 side is written into the color video memory 2 by R and G colors.

At this time, on the color video memory 2 side, the input data D ₀ aD ₉ a is directly passed through the image selector 62, the comparator CP, and the orifice 6b. While being supplied as data input on the drive control circuit 91 side, the color data for one screen is stored in the color video memory 2 side at the same time.

This is because the output is cut off while storing data from the first timing control logic 3 side to the memory 2 side when color information is sent to the color LED image display board 93 in a single line. This is to eliminate the phenomenon that is not a continuous expression by this.

In addition, in the color video memory 2 and the color graphics memory 4, the video graphic selector 61 is used by the image graphic selection circuit 6a of the image selection unit C to write or read data for one screen. By controlling the graphic address (A ₀ bA ₁₂ b) or the video address (A ₀ aA ₁₂ a), the color video memory (2) or the color graphic memory (4) is selectively controlled. .

When the readout data of the color video memory 2 side or the data output of the color video AD converter 1 side is provided to the comparator CP via the image selector 62, the output of the image selector 62 is stopped. By stopping at the control stage CH, as a result, there is no output of the video memory 2 and the color video AD converter 1, so that only the output data of the color video memory 4 side passes through the orifice 6b. The address A ₀ aA ₁₂ a on the side of the color video memory 2 or the address A ₀ on the side of the color graphics memory 4 in the image graphic selection circuit 6a. By alternately selecting bA ₁₂ b), the color LED image display board 93 can output an image containing graphics or characters.

The comparator CP on the output side of the image selector 62 is provided with a synchronous data clock D ′ ₀ -D ′ ₃ provided from the control signal counter 33 of the first timing control logic 3. It is provided as a synchronous clock when reading data.

On the other hand, in the first and second timing control logic (3, 5), as shown in FIG. 8, the vertical synchronization reduction pulse (IVS) on the output side of the vertical synchronization setting unit 31 and the horizontal projection on the output side of the horizontal projection setting unit 32. The reduction pulse CA and the clock pulse CKb on the oscillator D side are respectively output, which is applied to the interface 7 of FIG.

The interface 7 is connected to the clock interface of the counters 73A, 73B, 73C and decoders 73a, 73b, 73c from the vertical synchronization reduction pulse CA, the clock pulse CKb, and the horizontal synchronization reduction pulse IVS. By providing the hang pixel clock (CK _1- CK ₂₀ ) _per line, the vertical synchronization reduction pulse (IVS) by the counter 72A, 72B and the line select interface 72 of the decoder 72a The line select signal SE ₁ -SE ₁₆ of 14 or 16 line selection on the surface is provided, and the 16 × 16 is provided by the luminance interface 71 of the counter 71A and the shift resists 71a, 71b, 71c. It is possible to provide a luminance clock (BR ₁ -BR ₂₀ ) that provides the luminance by selectively adjusting the predetermined maintenance of a predetermined pixel of the color LED block having 20 colored LED blocks per line.

Meanwhile, in the first and second timing control logics 3 and 5, a vertical LED reduction pulse IVS, a horizontal synchronization reduction pulse CA, a basic clock pulse CK, and the like are transmitted through a line interface 8 to display a color LED image. When provided to the display unit 9 side, the PT function or V / G function and image graphic control signal selector (VGS) of FIG. 9 are selected together with the selection operation of the image graphic selector 61 on the image selector C side. The color image display to the color LED image display plate 93 side is performed in parallel with the control operation.

The selected output of the first and second timing control logics 3 and 5 extracts screen information of one screen from the color video memory 2 or the color graphics memory 4 and outputs the screen information of one screen. The R, G data is provided to the drive control circuit 91 on the side 9), while the line select clocks SE ₁ -SE ₁₆ , luminance signals BR ₁ -BR ₂₀ , and clock provided from the interface 7 are provided. The signals CK _{1 to} CK ₂₀ are provided to the drive control circuit 91 on the side of the color LED image display unit 9 via the line driver 8, respectively.

The color LED image display unit 9 includes a color LED unit 93a having a 16 × 16 dot as shown in FIG. 3, a driver 92a and a drive control circuit 91a, respectively. Since the color LED image display board 93 is provided with 20 rows and 14-16 columns, the control signal is driven by a line select and one row and column luminance signal driving control and driving of the color LED unit 9a. Each is provided by a clock.

Here, the color LED image display unit 9 assumes that, for example, the color LED unit unit 9a is combined as 2 horizontal x 2 vertical, and FIG. 11 (a) shows the relation between the control signal and the data. ) And (b).

Here, as shown in (a), the horizontal axis is a line L ₁ , L ₂ , and the line select signal at this time is SEa, SEb, and the R and G data are provided at each point. ) Is given as a correlation with the line select signals SEa, SEb, clock CKd, luminance signals BRa, BRb, display data, and the like.

Here, the luminance signals BRa and BRb can express the brightness and darkness of the luminance by lengthening or shortening the lighting holding time of the data carried on the color LED unit 9a.

In addition, the R, G data is provided with a lighting signal input to one color LED element 90 as R or G, or R and G are simultaneously provided, and the color of R, G and R + G at this time is provided. It is assumed that data of various color reproduction by the combination is included.

In the present invention, a device for reproducing a color image medium is a color LED image display plate. The color LED image display plate is relatively large, and data information related to images from color image systems such as VTRs and color graphics systems such as PCs. It is possible to obtain them directly by individually or to display them in a superimposed screen can be obtained a beneficial advantage that the display panel using the color LED can be utilized as an image output medium.

The present invention also provides a color LED display panel, which is a novel color LED image display board capable of directly displaying data output from a color image system and a color graphic system, and thus, from a widely used VTR, VCR or TV broadcasting system or a PC. By obtaining the video data in abundance, there is an advantageous feature that various advantages can be obtained in terms of the software.

Claims (7)

In an apparatus for receiving and outputting image data from an NTSC color image system (E) such as a VTR or a color graphics system (F) such as a PC including an EGA card 4a and a timing board 5a, The color image data and the synchronization signal from the color image system E are reset to match the display range of the color LED image display board 93 side by the dot matrix combination of the color LED unit 93a so that they can be stored and read out one by one. Color image unit A and color data from the color graphic system F and the synchronization signal are reset to match the display range of the color LED image display board 93 side, and the color graphics unit can be stored and read out one by one. (B) and the image selection unit (C) which enables the data output of the color image unit (A) and the color graphic unit (B) to be independently or alternately provided to the color LED image display plate 93 side, respectively. , The color image part A and the color graphic part ( Interface 7 providing line select pulses, clock pulses, and luminance pulses in the vertical and horizontal ranges of the synchronization signal reset on the B) side, and the output of the interface 7 side of the color LED image display plate 93; A color image display device for a color LED, characterized in that it is associated with a line interface (8) for line interface to the drive control circuit (91) side. The color image unit (A) according to claim 1, further comprising: a color decoder (1a) for demodulating the color image signal from the color composite video signal, a synchronous separator (2a) for separating the synchronization signal from the color decoder (1a), A video AD converter (1) for converting analog data to digital, timing control logic (3) for generating vertical and horizontal synchronization signals and various control signals reset from the output of the synchronous separator (2a), color image data storage, A color image display device of a color LED, characterized by comprising a readout color video memory (2). 2. The color graphic unit (B) according to claim 1, wherein the color graphic unit (B) includes timing control logic (5) for generating vertical and horizontal synchronization signals and various control signals for resetting synchronization signals from the EGA card (4a), and storing color graphic data and Color image display device of a color LED, characterized in that the configuration including a read color graphics memory (4). 2. The image selecting unit (C) according to claim 1, wherein the image selection unit (C) is configured to perform address selection or the like on the color video memory (2) or the color graphics memory (4) with control signals provided to the control board (5a) on the PC side. An image graphic control circuit 6a for generating a control signal, an image selector 62 for controlling selection of output from the image graphic selector 61 and the memories 2, 4, graphic selector 63 and or gate 6b. Color image display device of the color LED, characterized in that the configuration including. The clock interface (73) according to claim 1, wherein the interface (7) generates n clock signals from vertical and horizontal synchronization reduction signals and clock signals on the first and second timing control logics (3,5). A color image display device of a color LED, characterized in that it comprises an associated configuration with a luminance interface (3) for generating two luminance signals and a line select interface (72) for generating n line select signals. The vertical synchronization setting according to claim 2 or 3, wherein the timing control logic (3, 5) resets and outputs the vertical and horizontal synchronization signals to match the display range of the color LED image display board (93) from the synchronization signal. Sections 31 and 51, horizontal synchronization setting sections 32 and 52, control signal counter sections 33 and 53, decoders 34 and 54 for R / W and chip select signal outputs, and address generation counter sections of memory ( 35, 55, a color image display device of a color LED comprising a timing control logic (3, 5) including an image or graphic and an external operation control unit (OC) for controlling their overlapping operation. The external control unit (OC) according to claim 6, wherein the external operation control unit (OC) stores a PT stage for temporarily fixing graphic data in a memory when displaying an image of a color image and graphic data, a V / G stage for selecting an image or graphic, and data for one screen. LD stages for controlling memory are provided, and flip-flops JK and D flip-flops DF ₁ and DF ₂ on the side of the vertical synchronizing signal VS which perform these control functions, and the image graphics control signal selector VGS, etc. are provided. Color image display device of a color LED, characterized in that the circuit containing.

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