JPS6138993A - Display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention comprises a display surface in which a large number of picture elements are arranged in a matrix, and each picture element is displayed on the display surface in accordance with the luminance gradation of an image to be displayed on the display surface. The present invention relates to a display device that controls the pulse width of the light output of picture elements to display color or monochrome images consisting of still images, moving images, characters, etc., or a combination thereof.

(Background of the Invention) Conventionally, this type of device uses light emitting devices such as incandescent lamps, fluorescent lamps, and light emitting diodes (LEDs) instead of cathode ray tubes (CRTs) widely used in television receivers and the like. It is known to use a display surface having a large number of picture elements arranged in a matrix, each consisting of a display element such as a liquid crystal display element (LCD) that opens and closes transmitted or reflected light. Such a display device is used, for example, as a large-scale display device for scoreboards in baseball stadiums, stadiums, amusement parks, etc., various types of displays, outdoor advertising, or as a video screen for large-sized televisions or ultra-thin televisions.

(Object of the Invention) An object of the present invention is to reduce the memory capacity used in a display device that displays images, etc. by individually controlling the brightness of a large number of picture elements in a Noculus width.

(Structure of the Invention) In order to achieve the above object, the present invention provides a display surface formed by arranging a large number of display elements in a grid pattern, and a display screen in which individual display elements are displayed as picture elements in an image to be displayed on the display surface. In a display device comprising a display control circuit that controls a pulse width according to a luminance gradation to be output from an element, the display control circuit includes an image data memory that temporarily stores luminance gradation data for each of the display elements. , a shift register that serially reads and sequentially shifts the brightness gradation data read from the memory and outputs signals of the same bits of each brightness gradation data in parallel; and a shift register that stores the signals output from the shift register. At the same time, there is a latch circuit that energizes each display element in response to each signal, and a latch circuit that reads the next bit read signal every time a time proportional to the weighting of the bits of the brightness gradation data latched in the latch circuit elapses. It is characterized by comprising a readout control circuit that generates.

(Explanation of Examples) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 shows the overall configuration of a video display device according to an embodiment of the present invention. Further, FIG. 2 shows details of the main parts of the apparatus shown in FIG. 1.

In FIG. 1, a video device 1 includes a broadcast reception tuner,
Consisting of a TV camera, video tape recorder (VTR), video disc recorder (VDR), etc., it generates a standard video signal and based on this video signal, it outputs a brightness signal (if the video screen is monochrome) or red (R), green. (
G) and blue (B) and generate R signals (images (if the heron is in color)).

The image processing circuit 2 transmits the luminance or each color rail signal from the video device 1 to each display element 5 (511) arranged on the display surface 4.
, . . . e 5 yn n ) at timings corresponding to the respective positions, the sampling signal is A/D converted, and 6-bit (0 to 63) image data KD is output. This image data KD is temporarily stored in an address associated with each of the display elements 5 of the image data memory 31 (FIG. 2) in the display control circuit 3.

Referring to FIG. 2, this display control circuit 3 includes display elements 5k (1 to 5 kn per 5) for one horizontal scanning line, that is, one column.
For example, after the image data of the +1st column is supplied to the image data KD supplied from the image processing circuit 2, the write address 9 address WA, the write control signal R/W, and It is driven by the horizontal synchronization signal H8y.

The (k+1)th horizontal synchronizing signal H8y is supplied to the clock input terminal CP of the delay 9 fritz flop (DFF) 32 and the clear terminal CL of the counter 33. DF
The delay input terminal of F32 is pulled up by 1 level, and when the signal H5y is input as a clock, the output Q becomes 1 level. Therefore, the always-on oscillator 34
The excavation output of is supplied to the counter 36 via the ambi circuit 35, and the counter 36 starts counting.

The gradation pulse generation ROM 37 stores a-bit image data (
gradation data), the maximum on-time T (for example, 16.6 m5) of the display element 5 is divided into 2a, and 2a-x (X is 0 to
Data is written in advance so that gradations and contrasts are generated at timings (integer a). For example, when a=6 and the display brightness is controlled to 64 gradations, assuming that the count value output of the counter 36 that accesses this ROM 37 is counted up in T/64 cycles, the ROM 37 has the following:
Data 1 is written to address 65-2 and data 0 is written to the remaining Aviles.

Therefore, when the counter 36 starts counting, a gradation pulse whose cycle changes in the same way as the latch pulse shown in FIG. 3 is read out from the ROM 37 in accordance with the output of the count value.
Clock input terminal CP of counter 33 and DFF38
is supplied to the clock input terminal C of. This allows DF
The output Q of F38 becomes I+ in response to the delay input "1", the AND9 circuit 39 becomes conductive, and the output of the oscillator 40 is supplied to the counter 41. The count value of this counter 41 is read out from the image data memory 31. For example, 256 pieces of image data for one column are read out from the image data memory 31 by being supplied as an address.

The counter 33Iζ counts the gradation pulses from the ROM 37 and supplies the count output to the bit selection input terminals 81 to S3 of the bit selector 42. pit selector 42
selects and outputs only the signal of the Xth bit from the upper side with respect to the count output χ of the counter 33 out of the image data read out from the image data memory 31.

Therefore, when the ROM 37 generates the first gradation pulse after inputting the horizontal synchronizing signal H8y, the counter 33
"1 is output, and the pit selector 42 enters the most significant bit selection state. At the same time, the counter 41 counts the output of the oscillator 40, and sequentially accesses the image data memory 31 using this count value. As a result, the shift register 43 Only the most significant bit of the image data in the column is inputted via the pit selector 42 and sent from the oscillator 40 to the AND circuit 39.
are sequentially shifted by a clock supplied via the

The most significant bit of the pixel data of all the display elements in column k is read into the shift register 43, and the output of the counter 41 becomes 0.
When it becomes FFH, the output of the AND circuit 44 becomes 0°'. As a result, the DFF 38 is cleared and the clock from the oscillator 40 is cut off by the AND circuit 39.
While the data in the shift register 43 is held, the latch circuit 45 latches the 256 output signals of the shift register 43 as the output 9 signal of the AND 9 circuit 44. 6
(6-1,..., 6-n), and the display element 5 is supplied with 1. ..., 5kn is driven.

Next, when the second gradation pulse is generated from the ROM 37,
The counter 33 outputs a count value of 2, the pit selector selects the second bit from the upper side, and the DFF 38
, Ant 9 circuit 39 and counter 41 operate in the same manner as described above, and the signal of the second bit of the image data read from image data memory 31 is read into shift register 43.

When the counter 41 counts 256, that is, when all n=256 second bit signals have been read, these signals are taken from the shift register 43 into the latch circuit and latched.

This ends the display of time T/2 corresponding to the first bit, and starts displaying time T/4 corresponding to the second bit. From then on, T / 2 X + 1 corresponding to (, -X) bits in order
is displayed, and in processing with the B+1st (X=a) gradation data, all stages of the shift register 43 are cleared, all of the display elements 5 after the next latch are deenergized, and the next +1 Wait for the second horizontal sync signal.

(Effects of the Invention) As described above, according to the present invention, the capacity of image memory can be reduced compared to conventional ones (for example, Japanese Patent Application No. 58-81786), and peripheral ICs such as comparators are no longer required. Effects such as being able to reduce costs and requiring less wiring can be obtained.

(Modified Example of Embodiment) In the above embodiment, a specific bit of data from the image data memory is selected by a pit selector, but it is also possible to directly read out only the signal of this specific bit from the memory. You can also do this. Also, for example, a shift register with 256 outputs, one output for every 6 bits, is used in a 256x6 stage, all image data is read out once, and then shifted by 1 bit each time a gradation pulse is generated. Alternatively, the output signal may be output to the latch circuit. Furthermore, in the above description, the data are read out in order from the upper bits, but the data may be read out from the lower bits. In this case, the grayscale pulses are generated at a period of 2x. Furthermore, when using a liquid crystal element as a display element, as shown in FIG.
11z) The polarity of the element drive may be reversed in the middle of the display for one bit (dotted line in Figure 3). In this case, one additional pulse is generated in the ROM 37 in the middle of the generation timing of the gradation pulse for driving each bit. In FIG. 4, 48 is a steering circuit.

[Brief explanation of the drawing]

FIG. 1 is an overall block diagram of a display device according to an embodiment of the present invention, FIG. 2 is a detailed block diagram of the display control circuit in FIG. 1, and FIG. 3 is a latch generated in the display control circuit in FIG. FIG. 4 is a timing chart showing the drive state of the display element in pulses and 32nd and 37th gradations, and FIG. 4 is a partial circuit diagram showing another embodiment of the circuit in FIG. 2. 3...display control circuit, 4...display section,
Display element, 31... Image data memory, 43... Shift register support, 45...
...Latch circuit.

Claims (1)

[Claims] 1. A display surface formed by arranging a large number of display elements in a matrix, and a gradation of luminance to be output from each display element as a picture element in an image to be displayed on the display surface. In the display device, the display control circuit includes an image data memory that temporarily stores luminance gradation data for each of the display elements, and a luminance gradation read from the memory. A shift register that reads tone data serially and shifts them sequentially, and outputs signals of the same bits of each brightness tone data in parallel; The display device includes a latch circuit that energizes a display element, and a readout control circuit that generates a next bit readout signal every time a time period proportional to the weighting of the bits of the luminance gradation data latched in the latch circuit elapses. A display device characterized by: