JPH06324639A - Circuit and method for drive of flat display panel - Google Patents
Circuit and method for drive of flat display panelInfo
- Publication number
- JPH06324639A JPH06324639A JP4280648A JP28064892A JPH06324639A JP H06324639 A JPH06324639 A JP H06324639A JP 4280648 A JP4280648 A JP 4280648A JP 28064892 A JP28064892 A JP 28064892A JP H06324639 A JPH06324639 A JP H06324639A
- Authority
- JP
- Japan
- Prior art keywords
- driving
- data
- scan lines
- display panel
- flat panel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/04—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions
- G09G3/16—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source
- G09G3/18—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of a single character by selection from a plurality of characters, or by composing the character by combination of individual elements, e.g. segments using a combination of such display devices for composing words, rows or the like, in a frame with fixed character positions by control of light from an independent source using liquid crystals
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/18—Use of a frame buffer in a display terminal, inclusive of the display panel
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は平板形表示パネルに係
り、特に平板形表示パネルを駆動するための駆動回路お
よび方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flat panel display panel, and more particularly to a driving circuit and method for driving the flat panel display panel.
【０００２】一般に、平板形表示パネルを駆動するため
の駆動回路は図１に示した通り、平板形表示パネル１５
とパネル１５の偶数番目の陰極を駆動するための偶数番
目の陰極駆動回路１と、パネル１５の奇数番目のの陰極
を駆動するための奇数番目の陰極駆動回路２と、パネル
１５の奇数番目の陽極を駆動するための奇数番目の陽極
駆動回路３と、パネル１５の偶数番目の陽極を駆動する
ための偶数番目の陽極駆動回路４より構成されている。
そして、駆動方法は図２に示したように、偶数番目ある
いは奇数番目の陰極駆動回路１、２によって１つのスキ
ャンライン駆動時に、前記偶数番目あるいは奇数番目の
陽極駆動回路３、４から１ライン分のデータをパネル１
５に出力し、一つのデータフィールド（Field）で一つ
のフレーム（Frame）が構成されるようにした順次方式
を使用する。期間Ｔ１はフレーム周期を示すものであ
り、期間Ｔ２はスキャン周期を示す。Generally, a driving circuit for driving a flat panel display panel is as shown in FIG.
An even-numbered cathode driving circuit 1 for driving an even-numbered cathode of the panel 15, an odd-numbered cathode driving circuit 2 for driving an odd-numbered cathode of the panel 15, and an odd-numbered cathode driving circuit 2 of the panel 15. It is composed of an odd-numbered anode driving circuit 3 for driving the anodes and an even-numbered anode driving circuit 4 for driving the even-numbered anodes of the panel 15.
As shown in FIG. 2, the driving method is one line from the even-numbered or odd-numbered anode driving circuits 3 and 4 when one scan line is driven by the even-numbered or odd-numbered cathode driving circuits 1 and 2. Data of panel 1
5 is used, and a sequential method is used in which one frame is composed of one data field. The period T1 indicates a frame period, and the period T2 indicates a scan period.
【０００３】従って、それぞれのスキャンラインを駆動
させ得るようにスキャンライン数と等しい数の駆動回路
が必要となる。また、表示パネルが大型化されると、限
られたフレーム時間内に駆動すべきパネルのスキャンラ
イン数が増加する。表示パネルの大きさが大きくなり、
スキャンライン数が増加すれば、結局限られたフレーム
時間内にデューティ比（＝スキャンライン数）が減少さ
れ、１ラインの放電時間が減少され、ディスプレイ画面
の輝度が落ちる問題点が生じる。Therefore, as many drive circuits as the number of scan lines are required so that each scan line can be driven. Also, as the display panel becomes larger, the number of scan lines of the panel to be driven increases within a limited frame time. The size of the display panel increases,
If the number of scan lines increases, the duty ratio (= the number of scan lines) eventually decreases within a limited frame time, the discharge time of one line decreases, and the brightness of the display screen decreases.
【０００４】[0004]
【発明が解決しようとする課題】本発明の目的は一つの
フレーム領域内で分割された画面を構成するスキャンラ
インのみを駆動することによって、デューティ比と画面
の輝度が高くなる平板形表示パネルの駆動回路を提供す
ることである。SUMMARY OF THE INVENTION An object of the present invention is to provide a flat panel display panel in which the duty ratio and the brightness of the screen are increased by driving only the scan lines constituting the screen divided in one frame area. A drive circuit is provided.
【０００５】本発明の他の目的は二重（或いは多重）駆
動方式を用いてスキャン駆動用電極数を分割された画面
数まで減らして駆動回路を簡単にする平板形表示パネル
の駆動方法を提供することである。Another object of the present invention is to provide a driving method for a flat panel display panel using a double (or multiple) driving method to reduce the number of scan driving electrodes to the number of divided screens to simplify a driving circuit. It is to be.
【０００６】[0006]
【課題を解決するための手段】前述した目的を達成する
ために、本発明の平板表示パネルはＮ個のスキャンライ
ンとＭ個のデータラインとを有し、かつＫ個の部分に分
かれ、駆動回路は前記Ｋ個の各部分のスキャンラインを
同時に順次的に駆動するための第１駆動回路と、前記Ｋ
個の各部分のスキャンラインに該当するデータをスキャ
ンラインに同時に出力するためのＫ個の第２駆動回路と
を備えることを特徴とする。In order to achieve the above-mentioned object, a flat panel display panel of the present invention has N scan lines and M data lines, and is divided into K parts for driving. The circuit includes a first driving circuit for sequentially driving the scan lines of each of the K parts at the same time;
And K second driving circuits for simultaneously outputting the data corresponding to the scan lines of the respective parts to the scan lines.
【０００７】また、前述した他の目的を達成するため
に、本発明の平板形表示パネルは、Ｎ個のスキャンライ
ンとＭ個のデータラインとを有し、かつＫ個の部分に分
かれ、その駆動方法は前記Ｋ個の部分のスキャンライン
を同時に順次的に駆動するための第１過程と、前記Ｋ個
の部分の前記スキャンラインに該当するデータを前記ス
キャンラインに同時に順次的に伝送する第２過程とから
なることを特徴とする。In order to achieve the above-mentioned other object, the flat panel display panel of the present invention has N scan lines and M data lines and is divided into K parts. The driving method includes a first step for sequentially driving the scan lines of the K parts simultaneously, and a step of simultaneously transmitting data corresponding to the scan lines of the K parts to the scan lines simultaneously. It is characterized in that it consists of two processes.
【０００８】[0008]
【実施例】以下、添付した図面に基づいて本発明による
平板形表示パネルの駆動方法及び回路を説明すれば次の
通りである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The driving method and circuit of a flat panel display panel according to the present invention will be described below with reference to the accompanying drawings.
【０００９】図３は本発明の１実施例の平板形表示パネ
ルを駆動するための駆動回路とマトリックス構造を示
す。FIG. 3 shows a driving circuit and a matrix structure for driving a flat panel display panel according to an embodiment of the present invention.
【００１０】上側と下側より二分割された平板形表示パ
ネル２０と上側の陽極を駆動するための上側陽極駆動回
路５と、下側の陽極を駆動するための下側陽極駆動回路
６と、上側と下側の各対応される偶数番目の陰極を駆動
するための偶数番目の陰極駆動回路７と、上側と下側の
各対応される奇数番目の陰極を駆動するための奇数番目
の陰極駆動回路８より構成されている。A flat panel display panel 20 divided into two parts from the upper side and the lower side, an upper anode drive circuit 5 for driving the upper anode, and a lower anode drive circuit 6 for driving the lower anode. Even-numbered cathode driving circuit 7 for driving each corresponding even-numbered cathode on the upper side and lower side, and odd-numbered cathode driving circuit for driving each corresponding odd-numbered cathode on the upper side and lower side It is composed of a circuit 8.
【００１１】図４は図３に示した回路の各電極に印加さ
れるパルス波形を示す。FIG. 4 shows a pulse waveform applied to each electrode of the circuit shown in FIG.
【００１２】垂直同期信号Ｖｓｙｎｃは表示パネルのフ
レーム周波数を示し、期間Ｔ１のフレーム周期を有す
る。The vertical synchronizing signal Vsync indicates the frame frequency of the display panel and has a frame period of the period T1.
【００１３】水平同期信号Ｈｓｙｎｃは上側と下側の各
対応する陰極に共通に印加される周波数を示し、期間Ｔ
３のスキャン周期を有する。データ（Data）はスキャン
動作に応じて表示されるデータの表示期間を示す。ここ
で、期間Ｔ３はＴ２／２になるのでデータ表示期間が２
倍に伸びることになり、これによって輝度が高くなる。
また、印加される電極波形が１／２に縮められることに
よってハードウェアが縮められることになる。The horizontal synchronizing signal Hsync indicates the frequency commonly applied to the corresponding upper and lower cathodes, and the period T
It has a scan period of 3. Data indicates the display period of the data displayed according to the scan operation. Here, since the period T3 becomes T2 / 2, the data display period is 2
It will be doubled, which will increase the brightness.
Further, the applied electrode waveform is reduced to ½, which reduces the hardware.
【００１４】図５は本発明の実施例の平板形表示パネル
の駆動回路を示す。FIG. 5 shows a drive circuit for a flat panel display panel according to an embodiment of the present invention.
【００１５】図５に於て、平板表示パネルの駆動回路
は、２分割された平板形表示パネル２０、上側及び下側
陽極駆動回路５、６、偶数番目及び奇数番目の陰極駆動
回路７、８、第１画面の上側データを記憶するための第
１メモリ９、第１画面の下側データを記憶するための第
２メモリ１０、第２画面の上側データを記憶するための
第３メモリ１１、第２画面の下側データを記憶するため
の第４メモリ１２より構成され、ライト信号ＷＥ１、Ｗ
Ｅ２、ＷＥ３、ＷＥ４に応答してデータを記憶し、リー
ド信号ＲＤ１、ＲＤ２、ＲＤ３、ＲＤ４に応答して上側
及び下側の陽極駆動回路等５、６にデータを出力する。In FIG. 5, the driving circuit of the flat panel display panel is divided into two flat panel display panel 20, upper and lower anode driving circuits 5 and 6, and even and odd cathode driving circuits 7 and 8. A first memory 9 for storing upper data of the first screen, a second memory 10 for storing lower data of the first screen, a third memory 11 for storing upper data of the second screen, It is composed of a fourth memory 12 for storing lower side data of the second screen, and has write signals WE1 and W.
Data is stored in response to E2, WE3, and WE4, and data is output to the upper and lower anode drive circuits 5 and 6 in response to read signals RD1, RD2, RD3, and RD4.
【００１６】図６は図５に示した回路の動作を説明する
ための動作タイミング図を示したものである。FIG. 6 is an operation timing chart for explaining the operation of the circuit shown in FIG.
【００１７】ライトイネーブル信号ＷＥ１、ＷＥ２、Ｗ
Ｅ３、ＷＥ４とリード信号ＲＤ１、ＲＤ２、ＲＤ３、Ｒ
Ｄ４の周期は垂直同期信号Ｖｓｙｎｃ期間の２倍であ
る。また、リードタイムはライトタイムの２倍である。
前記ライト及びリードタイミングによるメモリ等の動作
を見れば次の通りである。Write enable signals WE1, WE2, W
E3, WE4 and read signals RD1, RD2, RD3, R
The period of D4 is twice the period of the vertical synchronizing signal Vsync. The read time is twice as long as the write time.
The operation of the memory or the like according to the write and read timings is as follows.
【００１８】まず、１０２４×７６８個の要素よりなっ
ていると仮定する。First, it is assumed that it is composed of 1024 × 768 elements.
【００１９】第１期間に第１画面の上側データ（１−Ｋ
１×１０２４〜１−Ｋ３８４×１０２４）がライトイネ
ーブル信号ＷＥ１に応答して第１メモリ９に記憶され
る。Upper data (1-K) of the first screen in the first period
1 × 1024 to 1-K384 × 1024) are stored in the first memory 9 in response to the write enable signal WE1.
【００２０】第２期間に第１画面の下側データ（１−Ｋ
３８５×１０２４〜１−Ｋ７６８×１０２４）がライト
イネーブル信号ＷＥ２に応答して第２メモリ１０に記憶
される。In the second period, the lower data (1-K) of the first screen is displayed.
385 × 1024 to 1-K768 × 1024) are stored in the second memory 10 in response to the write enable signal WE2.
【００２１】第３期間に第２画面の上側データ（２−Ｋ
１×１０２４〜２−Ｋ３８４×１０２４）がライトイネ
ーブル信号ＷＥ３に応答して第３メモリ１１に記憶され
る。During the third period, the upper side data (2-K
1 × 1024 to 2-K384 × 1024) are stored in the third memory 11 in response to the write enable signal WE3.
【００２２】第４期間に第２画面の下側データ（２−Ｋ
３８５×１０２４〜２−Ｋ７６８×１０２４）がライト
イネーブル信号ＷＥ４に応答して第４メモリ１２に記憶
される。また、第３期間と第４期間に前記第１メモリ９
と前記第２メモリ１０に記憶された第１画面のデータ等
（１−Ｋ１×１０２４〜１−Ｋ３８４×１０２４、１−
Ｋ３８５×１０２４〜１−Ｋ７６８×１０２４）がリー
ド信号ＲＤ１、ＲＤ２に応答して同時に上側及び下側陽
極駆動回路５、６に出力される。従って、図４に示され
た期間Ｔ３の間データがディスプレイされる。In the fourth period, the lower data of the second screen (2-K
385 × 1024 to 2-K768 × 1024) are stored in the fourth memory 12 in response to the write enable signal WE4. The first memory 9 is used in the third period and the fourth period.
And data of the first screen stored in the second memory 10 (1-K1 × 1024 to 1-K384 × 1024, 1-K1 × 1024
K385 × 1024 to 1-K768 × 1024) are simultaneously output to the upper and lower anode drive circuits 5 and 6 in response to the read signals RD1 and RD2. Therefore, the data is displayed during the period T3 shown in FIG.
【００２３】第５期間にライトイネーブル信号ＷＥ１に
応答して第３画面の上側データ（３−Ｋ１×１０２４〜
３−Ｋ３８４×１０２４）が第１メモリ９に記憶され
る。In the fifth period, in response to the write enable signal WE1, the upper data (3-K1 × 1024 ...
3-K384 × 1024) is stored in the first memory 9.
【００２４】第６期間にライトイネーブル信号ＷＥ２に
応答して第３画面の下側データ（３−Ｋ３８５×１０２
４〜３−Ｋ７６８×１０２４）が第２メモリ１０に記憶
される。また、第５期間と第６期間に前記第３メモリ１
１と第４メモリ１２に記憶された第２画面のデータ（２
−Ｋ１×１０２４〜２−Ｋ３８４×１０２４、２−Ｋ３
８５×１０２４〜２−Ｋ７６８×１０２４）がリード信
号ＲＤ３、ＲＤ４に応答して同時に上側及び下側陽極駆
動回路５、６に出力される。従って、図４に示された期
間Ｔ３の間データがディスプレイされる。In the sixth period, in response to the write enable signal WE2, the lower data (3-K385 × 102) of the third screen is displayed.
4 to 3-K768 × 1024) is stored in the second memory 10. In addition, the third memory 1 is provided in the fifth period and the sixth period.
1 and the data of the second screen stored in the fourth memory 12 (2
-K1 x 1024 to 2-K384 x 1024, 2-K3
85 × 1024 to 2-K768 × 1024) are simultaneously output to the upper and lower anode drive circuits 5 and 6 in response to the read signals RD3 and RD4. Therefore, the data is displayed during the period T3 shown in FIG.
【００２５】前述した動作を繰り返して行う。The above operation is repeated.
【００２６】[0026]
【発明の効果】以上述べたように、本発明による平板形
表示パネルの駆動回路はスキャン駆動回路が１／２に減
少することによって駆動回路が簡略化され、１水平走査
期間の増加によってデータ表示期間が増加して画面の輝
度が向上する。As described above, in the driving circuit of the flat panel display panel according to the present invention, the driving circuit is simplified by reducing the scan driving circuit to 1/2, and the data display is achieved by increasing the one horizontal scanning period. The period is increased and the screen brightness is improved.
【００２７】本発明は前述した実施例に限らず多分割さ
れた平板形表示パネルにも適用されうる。The present invention is not limited to the above-described embodiment, but can be applied to a multi-divided flat panel display panel.
【図１】従来の平板形表示パネルとパネルを駆動するた
めの駆動回路のブロック図。FIG. 1 is a block diagram of a conventional flat panel display panel and a drive circuit for driving the panel.
【図２】ＡからＣは従来の平板形表示パネルの駆動方法
を示す。2A to 2C show a driving method of a conventional flat panel display panel.
【図３】本発明による平板形表示パネルとパネルを駆動
するための駆動回路ブロック図。FIG. 3 is a block diagram of a flat panel display panel and a driving circuit for driving the panel according to the present invention.
【図４】Ａ乃至Ｄは本発明による平板形表示パネルの駆
動方法を説明するための平板形表示パネルに印加される
信号の波形を示す。4A to 4D show waveforms of signals applied to a flat panel display panel for explaining a driving method of the flat panel display panel according to the present invention.
【図５】本発明の１実施例の平板形表示パネルとそれを
駆動するための駆動回路に入力されるデータを処理する
方法を説明するためのデータ処理回路のブロック図。FIG. 5 is a block diagram of a data processing circuit for explaining a method of processing data input to a flat panel display panel and a driving circuit for driving the flat panel display panel according to an embodiment of the present invention.
【図６】図５に示したブロック図の動作を説明するため
のタイミング図である。FIG. 6 is a timing chart for explaining the operation of the block diagram shown in FIG.
１ 偶数番目の陰極駆動回路 ２ 奇数番目の陰極駆動回路 ３ 奇数番目の陽極駆動回路 ４ 偶数番目の陽極駆動回路 ５ 上側陽極駆動回路 ６ 下側陽極駆動回路 ７ 偶数番目の陰極駆動回路 ８ 奇数番目の陰極駆動回路 ９ 第１メモリ １０ 第２メモリ １１ 第３メモリ １２ 第４メモリ １５ 平板表示パネル ２０ 平板表示パネル 1 Even-numbered cathode drive circuit 2 Odd-numbered cathode drive circuit 3 Odd-numbered anode drive circuit 4 Even-numbered anode drive circuit 5 Upper anode drive circuit 6 Lower anode drive circuit 7 Even-numbered cathode drive circuit 8 Odd-numbered Cathode drive circuit 9 First memory 10 Second memory 11 Third memory 12 Fourth memory 15 Flat display panel 20 Flat display panel
Claims (8)
ラインとを有し、かつ第１部分と第２部分に分かれた平
板形表示パネルを駆動するに於て、 前記第１、第２部分のスキャンラインを同時に順次的に
駆動するための第１駆動回路と、 前記第１、第２部分のスキャンラインに該当するデータ
をスキャンラインに同時に出力するための第２、第３駆
動回路とを備えることを特徴とする平板形表示パネルの
駆動回路。1. In driving a flat panel display panel having N scan lines and M data lines and divided into a first portion and a second portion, the first and second portions are provided. A first driving circuit for sequentially driving the scan lines simultaneously, and second and third driving circuits for simultaneously outputting the data corresponding to the scan lines of the first and second parts to the scan lines. A drive circuit for a flat panel display characterized by comprising.
ータを記憶し、第１リード信号に応答して該上側データ
を出力するための第１メモリと、 第２ライトイネーブル信号に応答して前記第１画面の下
側データを記憶し、前記第１リード信号に応答して該下
側データを出力するための第２メモリとを備えることを
特徴とする請求項１に記載の平板形表示パネルの駆動回
路。2. A first memory for allowing the second drive circuit to store upper data of the first screen in response to a first write enable signal and to output the upper data in response to a first read signal. And a second memory for storing the lower side data of the first screen in response to a second write enable signal and outputting the lower side data in response to the first read signal. The drive circuit for a flat panel display panel according to claim 1.
２ライトイネーブル信号の２倍のデューティ比を有する
ことを特徴とする請求項２に記載の平板形表示パネルの
駆動回路。3. The driving circuit of a flat panel display panel according to claim 2, wherein the first read signal has a duty ratio twice as high as that of the first and second write enable signals.
ータを記憶し、第２リード信号に応答して該上側データ
を出力するための第３メモリと、 第４ライトイネーブル信号に応答して前記第２画面の下
側データを記憶し、前記第２リード信号に応答して該下
側データを出力するための第４メモリとを備えることを
特徴とする請求項３項に記載の平板形表示パネルの駆動
回路。4. A third memory for allowing the third drive circuit to store upper data of the second screen in response to a third write enable signal and to output the upper data in response to a second read signal. And a fourth memory for storing the lower side data of the second screen in response to a fourth write enable signal and outputting the lower side data in response to the second read signal. The drive circuit for a flat panel display panel according to claim 3.
４ライトイネーブル信号の２倍のデューティ比を有する
ことを特徴とする請求項４に記載の平板形表示パネルの
駆動回路。5. The driving circuit of the flat panel display according to claim 4, wherein the second read signal has a duty ratio twice as high as that of the third and fourth write enable signals.
ラインとを有し、かつ第１部分と第２部分とに分かれた
平板形表示パネルを駆動するに於て、 前記第１部分と第２部分のスキャンラインを同時に順次
的に駆動する過程と、 前記第１部分と第２部分のスキャンラインに該当するデ
ータを前記スキャンラインに同時に伝送する過程とから
なることを特徴とする平板形表示パネル駆動方法。6. In driving a flat panel display panel having N scan lines and M data lines and divided into a first portion and a second portion, the first portion and the first portion are driven. A flat panel display, comprising the steps of sequentially driving the scan lines of two parts simultaneously and the step of simultaneously transmitting data corresponding to the scan lines of the first part and the second part to the scan lines. Panel drive method.
ラインとを有し、かつＫ個の部分に分かれた平板形表示
パネルを駆動するに於て、 前記Ｋ個の部分のスキャンラインを同時に順次的に駆動
するための第１駆動回路と、 前記Ｋ個の部分のスキャンラインに該当するデータを前
記スキャンラインに同時に出力するためのＫ個の駆動回
路とを備えることを特徴とする平板形表示パネルの駆動
回路。7. When driving a flat panel display panel having N scan lines and N data lines and divided into K portions, the K scan lines are simultaneously scanned. A flat plate type driving device, comprising: a first driving circuit for sequentially driving the driving circuit; and K driving circuits for simultaneously outputting data corresponding to the K scanning lines to the scanning lines. Display panel drive circuit.
ラインとを有し、かつＫ個の部分に分かれた平板形表示
パネルを駆動するに於て、 前記Ｋ個の部分のスキャンラインを同時に順次的に駆動
する第１過程と、 前記Ｋ個の部分のスキャンラインに該当するデータを前
記スキャンラインに同時に伝送する過程とからなること
を特徴とする平板表示パネルの駆動方法。8. When driving a flat panel display panel having N scan lines and M data lines and divided into K parts, the scan lines of the K parts are simultaneously driven. A method of driving a flat panel display, comprising a first step of sequentially driving and a step of simultaneously transmitting data corresponding to the K scan lines to the scan lines.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR91-23388 | 1991-12-18 | ||
| KR1019910023388A KR940004135B1 (en) | 1991-12-18 | 1991-12-18 | Driving circuit in a display panel of flat type |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06324639A true JPH06324639A (en) | 1994-11-25 |
Family
ID=19325160
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4280648A Pending JPH06324639A (en) | 1991-12-18 | 1992-09-24 | Circuit and method for drive of flat display panel |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPH06324639A (en) |
| KR (1) | KR940004135B1 (en) |
| DE (1) | DE4231847A1 (en) |
| GB (1) | GB2262643B (en) |
| TW (1) | TW207577B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100409441C (en) * | 2001-01-31 | 2008-08-06 | 精工爱普生株式会社 | Display device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20060019755A (en) | 2004-08-30 | 2006-03-06 | 삼성에스디아이 주식회사 | Light emitting display and driving method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4934296A (en) * | 1972-07-28 | 1974-03-29 | ||
| JPH0221692B2 (en) * | 1982-09-01 | 1990-05-15 | Matsushita Electric Ind Co Ltd |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4297695A (en) * | 1978-12-28 | 1981-10-27 | Xerox Corporation | Electrochromic display device |
| US4574280A (en) * | 1983-01-28 | 1986-03-04 | The Board Of Trustees Of The University Of Illinois | Gas discharge logic device for use with AC plasma panels |
| US4533913A (en) * | 1983-04-06 | 1985-08-06 | Burroughs Corporation | Gas-filled dot matrix display panel and operating system |
-
1991
- 1991-12-18 KR KR1019910023388A patent/KR940004135B1/en not_active IP Right Cessation
-
1992
- 1992-09-21 TW TW081107441A patent/TW207577B/zh not_active IP Right Cessation
- 1992-09-23 DE DE4231847A patent/DE4231847A1/en not_active Withdrawn
- 1992-09-24 JP JP4280648A patent/JPH06324639A/en active Pending
- 1992-09-28 GB GB9220402A patent/GB2262643B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4934296A (en) * | 1972-07-28 | 1974-03-29 | ||
| JPH0221692B2 (en) * | 1982-09-01 | 1990-05-15 | Matsushita Electric Ind Co Ltd |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100409441C (en) * | 2001-01-31 | 2008-08-06 | 精工爱普生株式会社 | Display device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW207577B (en) | 1993-06-11 |
| GB2262643B (en) | 1995-11-01 |
| KR940004135B1 (en) | 1994-05-13 |
| GB2262643A (en) | 1993-06-23 |
| GB9220402D0 (en) | 1992-11-11 |
| KR930014236A (en) | 1993-07-22 |
| DE4231847A1 (en) | 1993-06-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6559839B1 (en) | Image display apparatus and method using output enable signals to display interlaced images | |
| US6646629B2 (en) | Liquid crystal display control device, liquid crystal display device using the same, and information processor | |
| CN1519810A (en) | Displaying device driving device | |
| JPH0736406A (en) | Dot matrix display device and method for driving it | |
| JP3070893B2 (en) | Liquid crystal drive | |
| JPH0429293A (en) | Display system for plasma display device | |
| JPH07121143A (en) | Liquid crystal display device and liquid crystal driving method | |
| JPH11175037A (en) | Liquid crystal display device | |
| US6172465B1 (en) | Method for driving plasma display | |
| JP2003140624A (en) | Active matrix type liquid crystal display device | |
| JP2003131630A (en) | Liquid crystal display device | |
| JPH11282437A (en) | Interface device of liquid-crystal display panel | |
| JPH06324639A (en) | Circuit and method for drive of flat display panel | |
| JPH10133621A (en) | Plasma display | |
| JPH0854601A (en) | Active matrix type liquid crystal display device | |
| US5386217A (en) | Method for controlling a liquid crystal display module to show interlaced picture data thereon | |
| JP3015544B2 (en) | Liquid crystal display | |
| JP2776090B2 (en) | Image display device | |
| JPH0854862A (en) | Display and its driving method | |
| JPH07261145A (en) | Liquid crystal driving method | |
| JP3262175B2 (en) | LCD driving method | |
| KR100516065B1 (en) | High resolution liquid crystal display device and method thereof for enlarged display of low resolution image data | |
| JP2003186454A (en) | Planar display device | |
| JP3169377B2 (en) | Driving method of liquid crystal display panel | |
| JPH08185142A (en) | Liquid crystal display device |