JPH0422272B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention comprises a display surface formed by arranging a large number of three-color display elements in a matrix, each displaying the three primary colors of red, green, and blue. By digitally processing, brightness gradation data corresponding to the position and color of each of the display elements in the image to be displayed on the display screen is created, and the corresponding display elements are adjusted according to the brightness gradation. The present invention relates to a color display device that displays color or monochrome images consisting of still images, moving images, characters, etc., or a combination thereof, by controlling the pulse width of the light output of the device.

(Background of the Invention) Conventionally, devices of this type include light-emitting devices such as cathode ray tubes (CRTs), incandescent lamps, fluorescent lamps, and light-emitting diodes (LEDs), and liquid crystal display devices (LCDs) that open and close transmitted or reflected light. A device using a display surface formed by arranging a large number of picture elements made up of display elements in a matrix is known. In this case, if one picture element is composed of one display element that displays a single color, it will become a display device that displays a monochrome image; The display elements R, G, and B that display each of the three primary colors are arranged as shown in FIG.
By using a display surface in which each set is one picture element, a color display device that displays color images can be obtained.

Such display devices are used, for example, as scoreboards in baseball stadiums, stadiums, amusement parks, etc., large-scale display devices for various displays, outdoor advertising, or as video screens for large-sized televisions or ultra-flat televisions. There is.

Incidentally, in such a display device, the white balance of the display surface is adjusted by changing the brightness, for example, the maximum brightness, for each display element that displays each color. The applied voltage is changed by switching the taps of the power transformer, but this increases the size of the equipment and
Since the configuration becomes complicated and the cost increases, switching is performed in only three stages at most, and sufficient white balance adjustment cannot be desired. In addition, as a display device of this kind, a ROM (ROM) that stores pulse width data that generates a light output with a luminance corresponding to the gradation data representing the luminance of each display element obtained by digital processing from a color video signal. There are also known devices equipped with a read-only memory (read-only memory), and it is also possible to obtain white balance by adjusting the correction contents of this ROM according to the brightness characteristics of the display elements of each color. but,
Display elements that display each color generally have different aging characteristics, and for this reason, even if the white balance is adjusted at the beginning of use, if the white balance collapses as the usage time passes, it is necessary to readjust it. The contents of the ROM must be rewritten, and this adjustment is extremely troublesome.

(Object of the Invention) The present invention has been made in view of the above-mentioned problems with the conventional type, and includes a color display surface in which a large number of display elements displaying each of the three primary colors are arranged in a matrix. In a display device that displays images, etc. on the color display surface by controlling pulse widths of display elements, a reference clock generating means for obtaining a pulse width corresponding to gradation data of each display element is provided separately for each color. Based on the concept of independently changing the output frequency of each reference clock generating means, the pulse width, or brightness, for the gradation data of each color display element can be changed independently for each color, and the white balance can be freely adjusted. The purpose is to make it possible.

(Structure of the Invention) In order to achieve the above object, the present invention provides a display surface in which a large number of three-color display elements each displaying the three primary colors of red, green, and blue are arranged in a matrix;
A/D conversion means for digitally processing a color video signal and creating luminance gradation data corresponding to the position and color of each of the display elements in the video to be displayed on the display screen; and a standard for varying the output frequency. In a color display device comprising a clock generating means and a display control means for driving the display element while a number of reference clocks corresponding to the gradation data for each predetermined period of time are counted, Three clocks are provided corresponding to the colors of the display elements, and the display control means is operated by separate reference clocks for each color of the display elements, and the display elements of each color are driven by individually changing the frequency of these reference clocks. The display brightness and white balance of each color are adjusted by individually changing the pulse width of each color.

(Description of Examples) Examples of the present invention will be described below with reference to the drawings. FIG. 2 shows the overall configuration of a video display device according to an embodiment of the present invention. 3 and 4 show details of the main parts of the apparatus shown in FIG. 2. In FIG. 2, a received signal received by an antenna 1 is guided to a receiving section 2, from which a synchronizing signal SY is extracted via a synchronizing signal detection circuit 3 on the one hand, and an image is displayed on the other hand. A video signal is taken out via the signal display device 4. The video signal display device 4 displays each display element 7 ( 7 The video signal is sampled at the timing corresponding to the position ₁₁ ,...,7mn), and this sampling signal is A/D converted to 6 bits (
~63) outputs gradation data. This gradation data is temporarily stored in an address associated with each of the display elements 7 in the one-screen memory 8, and is stored at a predetermined time such as a vertical blanking period for one vertical period (if the video signal is NTSC, 1/2 60 seconds) is transferred to the display control unit 9 in a sufficiently shorter time (for example, several milliseconds).

As shown in FIG. 2, the display control unit 9 includes latches 21 (21 ₁₁ , ..., 21mn) and comparators 22 (22 11 , ₂₁ mn) arranged in a matrix corresponding to each display element 7 on the display surface 6. ..., 22mn), a row address decoder 23 and a column address decoder 2 for distributing gradation data for each display element 7 sequentially output from the one-screen memory 8 to the latch group 21.
4 is provided. When transferring grayscale data, the timing signal generator 5 supplies the read/write clock signal R/W, row address signal RA, and column address signal CA to the one-screen memory 8, and sequentially reads out the grayscale data. , AND the row address signal RA to the row address decoder 23, the column address signal CA and the latch clock signal LC.
The data is supplied to the column address decoder 24 via the gate 25, so that the gradation data sequentially generated by the one-screen memory 8 are sequentially stored in the corresponding latches 21.

The gradation control circuit 10 generates pulse width data B (B _Z ，
B _G , B _B ), and as shown in detail in FIG. 4, flip-flops 31, 31R, 31G,
31B, NAND gate 32, 32R, 32G,
32B, counter 33, 33R, 33G, 33
B. Clock pulse oscillator 34, 34R, 34
G, 34B and gradation ROM35, 35R, 35
It consists of three sets of blocks similarly configured with G, 35B, etc. The flip-flop 31 is set by the synchronization signal SY from the synchronization signal detection circuit 3,
The set output "1" is applied to one input terminal of the NAND gate 32 and also applied to the clear terminal CL of the counter 33 as a clear release signal. As a result, the NAND gate 32 becomes conductive and inverts the clock signal TC from the oscillator 34 and provides it as a counting input to the counter 33. Since the counter 33 has been cleared, it starts counting the clock signal TC. And counter 3
3 overflows when the clock signal TC exceeds a predetermined number, for example, the maximum number of gradations, and generates a signal "1" at the borrow/carrier (B/C) terminal. This signal "1" is supplied to the reset terminal of the flip-flop 31.
is reset and its set output becomes "0". This set output "0" causes the NAND gate 32 to become non-conductive and stop supplying the clock signal TC to the counter 33.
3 is cleared and its output (count value) becomes zero. This state of count stop count output 0 continues until the next synchronization signal SY is generated, and this state of count stop count output 0 continues until the next synchronization signal SY is generated.
The above-mentioned operation is repeated with the occurrence of . Through the operations of the flip-flop 31, NAND gate 42, etc., the gradation control circuit 10 generates pulse width data synchronized with the synchronizing signal SY. Here, a known oscillator such as a crystal oscillator or a multivibrator can be used as the oscillator 34, and the oscillation frequency can be varied by a known method such as replacing the crystal or changing the resistance value. .

The ROM 35 stores pulse width data corresponding to the brightness to be displayed based on the gradation data,
The stored contents are sequentially read out using the count output of the counter 33 as address data. As this pulse width data, for example, if S is the video signal level of this display device, that is, the brightness ratio of each display device to the number N of gradations, then NoS (No is the maximum number of gradations) is stored at the address corresponding to the number N of gradations. Here, the integer data closest to 63) is written.

Pulse width data B read from ROM35
( _BR , _BG , _BB ) are supplied to the display control section 9.

Referring to FIG. 3, each comparator 22 is supplied with the stored contents of the latch 21 to which it is attached as its first input A, ie the gray scale data KD, while its second input B , the pulse width data B (B _R , B R ,
B _G , B _B ) are supplied for each color of the display element 7 controlled by the output of this comparator 22, and B<A
It generates an output signal between B and A, and turns off the output signal when B>A. Therefore, the oscillation frequency of the oscillator 34 is varied by the gradation control circuit 10.
By changing the reading speed of pulse width data from the ROM 35, the pulse width of the optical output, that is, the brightness level of the display element can be changed. Therefore,
Oscillators 34R, 34 provided for each color
The white balance can be easily adjusted by changing the oscillation frequencies of G and 34B separately and adjusting the brightness for each color.

Output driver 11 (11 ₁₁ ,..., 11mn)
In Fig. 3, display elements 7 ₁₁ to _{7 1} m for the first column are shown.
Output driver 11 for one column corresponding to ₁₁ to 11
Although only ₁ m is shown, it is provided corresponding to each comparator 22 and display element 7, and the comparator 22
Each display element 7 is driven by an output signal from.
As a result, each display element 7 is dimmed and controlled at a display brightness corresponding to the gradation data and the oscillation frequency of the oscillator 34.

Note that in the above description, the ROM 35 can be omitted if the display luminance versus video signal level characteristic is linear. In this case, the output of the counter 33 may be directly supplied to the B input of the comparator 22.

(Effects of the Invention) As described above, according to the present invention, even when the white balance is excellent due to the different aging characteristics of the display elements that display each of the three primary colors, the frequency of the reference clock The white balance can be readjusted by an extremely simple operation that only requires changing the values individually. Therefore, it is possible to maintain display of an image with good white balance for a long period of time.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of the arrangement of display elements for three primary colors on the display surface of a color display device, FIG. 2 is an overall block diagram of a display device according to an embodiment of the present invention, and FIG. Detailed circuit diagrams of the display control unit, output driver, and display screen, and Figure 4 is the second
FIG. 4 is a detailed circuit diagram of the gradation control in FIGS. 4...Video signal display device, 6...Display surface, 7
₁₁ ,...7mn...display element, 9...display control unit,
10... gradation control circuit, 21 ₁₁ ,...,
21mn...Latch, 33, 33R, 33G, 3
3B...Counter, 34, 34R, 34G, 34
B...oscillator, 35, 35R, 35G, 35B...
…ROM.

Claims (1)

[Scope of Claims] 1. A display screen formed by arranging a large number of three-color display elements in a matrix, each outputting the three primary colors red, green, and blue, and a color video signal that is digitally processed and displayed on the display screen. A/D conversion means for creating luminance gradation data corresponding to the position and color of each of the display elements in the image to be displayed; a reference clock generating means with variable output frequency; and the gradation data at fixed time intervals. and a display control means for driving the display element while a number of reference clocks corresponding to the number of reference clocks are counted. The display control means is operated with separate reference clocks for each color of the display element, and by individually changing the frequency of these reference clocks, the pulse width for driving the display elements of each color is individually changed to display each color. A color display device characterized by adjusting brightness and white balance. 2. The reference clock generating means includes a ROM in which a gray scale pulse pitch is written in accordance with the video signal and the gray scale data/luminance characteristics of the display element, and the pitch of the reference clock to be applied to the display control means is adjusted to this gray scale. 2. A color display device according to claim 1, wherein the luminance characteristics of said display element are corrected by conversion based on pulse pitch.