JPS6073580A - Display - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention comprises a display surface formed by arranging a large number of three-color display elements in a matrix, each displaying the three primary colors of red, green, and blue. By digitally processing, brightness gradation data corresponding to the position and color of each display element in the image to be displayed on the display screen is created, and each of the above displays is adjusted according to this brightness gradation. The present invention relates to a color display device that displays color or monochrome images consisting of still images, moving images, characters, etc., or a combination thereof, by controlling the pulse width of the light output of an element.

(i'f, bright background) Conventionally, this type of device has been equipped with light-emitting elements such as cathode ray tubes (CRTs), incandescent lamps, fluorescent lamps, and light-emitting diodes (LEDs), and liquid crystal display elements (LCDs) that open and close transmitted or reflected light. It is known that a display surface is made up of a large number of picture elements arranged in a matrix, such as an LCD (LCD).In this case, one picture element is composed of one display element that displays a single color. In this case, it is a display device that displays a monochrome image, but the display element R1G and J that displays each of the three primary colors of red (R), green (G), and blue (B) are used.
: and B are arranged as shown in FIG. 1(a) or (b) to use a display surface in which each display element R, G, G, 8 or one set of RoG, B is one picture element. Accordingly, a color display device that displays color images can be obtained.

Such a display device is used, for example, as a large display device for scoreboards at baseball stadiums, stadiums, M parks, etc., various displays, outdoor advertisements, or as a video screen for large TVs or ultra-flat TVs. There is.

By the way, in J3 of such a display device, the white balance adjustment of the display surface is carried out by changing the brightness, for example, the maximum brightness, for each display element that displays each color. The voltage applied to the lamp is changed by changing the taps of the power transformer, but this increases the size of the device, increases the length of 78 m, and increases costs, so switching is only done in three steps at most. , I couldn't hope for sufficient white balance adjustment. In addition, in this type of display device, a ROM that stores pulse width data that generates a light output with a luminance corresponding to the gradation data from @ gradation data representing the luminance of each display element obtained by digital processing from a C color video signal. (Read-only memory) is also known, and it is also possible to obtain white balance by adjusting the correction contents of this ROM according to the brightness characteristics of the display elements of each color. but,
Display elements that display each color generally have different aging characteristics, and for this reason, even if the white balance is adjusted at the beginning of use, if the white balance collapses as the usage time passes, it is necessary to readjust it. In order to do this, the contents stored in the ROM must be rewritten, and this adjustment is extremely troublesome.

(Object of the Invention) The present invention has been made in view of the above-mentioned problems with the conventional type, and includes a color display surface in which a large number of display elements displaying each of the three primary colors are arranged in a matrix. In the display device that displays images, etc. on the color display surface by controlling the pulse width of the display elements, a reference clock generating means for obtaining a pulse width corresponding to the gradation data of each display element is provided separately for each color. By independently changing the output frequency of each reference clock generating means, the pulse width ′ for the gradation data of each color display element can be changed.
? 1', that is, based on the concept of changing the brightness independently for each color, the purpose is to make it possible to freely adjust the white balance.

(1R composition of invention) Achieve the above purpose! According to the present invention, a color video signal is digitally processed and an image to be displayed on the display surface is formed by arranging a large number of three-color display elements in a matrix to display the three primary colors of red, green, and blue. 14 corresponding to the position and color of each of the above-mentioned display elements inside.
A/D conversion means for creating gradation data of degrees; reference clock generation means having a variable output frequency; In a color display device, the reference clock generating means is provided in three pieces corresponding to the color of the display element, and the display control means is provided with three reference clock generating means corresponding to the color of the display element. Operate with reference clocks and change the frequency of these reference clocks individually M
The present invention is characterized in that the display brightness and self-balance of each color are adjusted by individually changing the pulse width by which the display elements of each color are driven (Explanation of Embodiments) Hereinafter, the present invention will be described with reference to the drawings. A detailed explanation of.

FIG. 2 shows the overall configuration of a video display device according to an embodiment of the present invention. Further, Figures 3 and 4 show details of the main parts of the apparatus shown in Figure 2. In FIG. 2, an IC reception signal received by an antenna 1 is guided to a reception section 2, and a synchronization signal SY is extracted from this reception signal via the same JWJ fg detection circuit 3. On the other hand, a video signal is extracted via a video signal generator @4. The video signal generator 64 generates each display element 7 ( 7n, . . . , 7mn), the sampling signal is A/D converted, and C6-bit (0 to 63) gradation data is output. This gradation data is stored in the 1 screen memory 8
is temporarily stored in an address associated with each of the display elements 7, and is stored for one vertical period (1/60 second if the video signal is NTSC) at a predetermined time such as a vertical blanking period.
The data is transferred to the display control unit 9 in a sufficiently shorter time (for example, several ms).

The display control unit 9 is not shown in FIG.
and comparator 22 (22n, -・-・, 22m
n), a row address decoder 23J3 and a column address decoder 24 for distributing gradation data for each display watermark 7 sequentially outputted from the one-screen memory 8 to the latch group 21. When transferring gradation data, a read/write clock signal R/W, a row address signal RA, and a column address signal CA are sent from the timing signal generator 5.
is supplied to the one-screen memory 8 to sequentially read out the gradation data, and at the same time, the row address signal RA is sent to the row address decoder 23, and the column address signal 3CA and latch clock signal LC are sent to the column address decoder 24 via an AND gate 25. and sequentially store the gradation data sequentially generated by the one-screen memory 8 in the corresponding latches 21 J:
It's a sea urchin.

The gradation control] roll circuit 10 generates the first output j of the display brightness corresponding to the gradation data for each of the three primary colors in synchronization with the output J° of the synchronization signal detection circuit 3. Pulse width data lj(B z, B c .

Bs), the details of which are not shown in Figure 4.J:
uni, flip-flops 31 (31R, '31c, 31e) for each of the three primary colors on the display surface 6.
, N AND goo 1-32 (32R, 32c,
32B), counter 33 (33R, 33G, 33
s), clock pulse oscillator 34 (34R, 34c
, 34 [3) and gradation R0M35 (35R.

It consists of three sets of similarly constructed blocks such as 35G and 35B). The flip-flop 31 is set by the synchronizing signal SY from the synchronizing signal detecting circuit 3, and the output "1" of the cellar 1 is applied to one input terminal of the NAND gate 32, and the clear terminal CL of the counter 33 is sent as a clear cancel signal. -Give C. This allows NAN
The D gate 32 becomes conductive and inverts the clock signal TO from the oscillator 34 and provides it as a counting input to the counter 33. Since the counter 33 has been cleared, it starts counting the clock signal TO. Then, the counter 33 converts the clock signal TC to a predetermined number, for example, the maximum floor n1.
When the number of 7J is exceeded and 4 is released, an overflow occurs and a signal "1" is generated at the borrow/gearia (B/C) terminal. This signal 111 I+ is supplied to the reset terminal of the flip flop 31, and the flip flop 31 is reset and its set output becomes "0'°. With this set output II O11, the NAND gate 1 gate 2 becomes non-operational. It becomes conductive and stops supplying the clock signal TC to the counter 33, and the counter 33 is cleared and the output horn (count value) of -C becomes zero.The state of this count stop count output O is determined by the next synchronization signal SY. This continues until the +11J signal SY is generated, and the above operation is repeated.These flip-flops 31 and NA
Through the operation of the ND gate 42 and the like, the gradation control circuit 10 generates pulse width data that is the same as the signal SY. An oscillator can be used, and the oscillation frequency can be varied by known methods such as replacing the crystal or changing the resistor.

The ROM 35 stores pulse width data corresponding to the luminance to be displayed based on the gradation data, and the stored contents are sequentially read out using the count output of the counter 33 as address data. This pulse width data is, for example,
For the video signal level of this display device, that is, the number of gradations N,
If the brightness ratio of each display element of 4 is S, then the address corresponding to the number of gradations N is No S (No is the maximum number of gradations,
Here, the integer data closest to 63) is written.

Pulse width data B (BR,
BG, Be) are supplied to the display control section 9.

Referring to FIG. 3, each comparator 22 receives as its first input A the memory contents of the latch 21 to which this comparator 22 is attached, that is, gradation data KD, and as its second input B. The pulse width data B (BR, Bc, Be) from the roll circuit 10 is sent to the gradation controller 1 by this comparator 2.
The signal is supplied to each color of the display element 7 controlled by the output of 2, and an output signal is generated while B<A, and the output signal is turned off when BAA is reached. Therefore, when the gradation control weight is 0, the oscillation frequency of the oscillator 34 is varied and the I
(By changing the reading speed of the pulse width data from the 0M35, the pulse width of the optical output, that is, the turquoise level of the display element can be changed. Therefore, the oscillation frequency of the oscillators 34R, 34c, and 34B provided for each color can be changed. Adjust the brightness for each color by changing each separately.
- the white balance can be easily adjusted.

Output driver 11 (11++, ・--, llmn
) shows only output drivers 1111 to 11+m for one column corresponding to display elements 711 to 7+m for the first column in FIG. Each display element 7 is driven by the output signal from the comparator 22. To this J: Su, each display code 7
is dimmed and controlled with display brightness corresponding to the gradation data and the oscillation frequency of the oscillator 34.

Note that in the above description, the ROM 35 can be omitted if the display luminance versus video signal level characteristic is linear.

In this case, the output of the counter 33 can be directly supplied to the B input of the comparator 22.

(Effects of the Invention) As described above, according to the present invention, even if the white balance is disrupted due to the different aging characteristics of the display elements that display each of the three primary colors, even if the reference clock is The self-balance can be readjusted by extremely simple operations such as changing the frequency of each individual. Therefore, it is possible to maintain the display of an image with a high white balance for a long period of time.

[Brief explanation of the drawing]

FIG. 1 shows an example of the arrangement of display elements for three primary colors on the display surface of a color display device, FIG. 2 is an overall block diagram of a display device according to an embodiment of the present invention, and FIG. J3 in the figure
FIG. 4 is a detailed circuit diagram of the display control unit, output driver, and display screen, and FIG. 4 is a detailed circuit diagram of the gradation control 1 shown in FIGS. 2 and 3. 4-1 video signal generator, 6: display surface, 7u, -,
7111n: display element, 9: display control section, 10: gradation control 1 control circuit, 21n, .=, 21mn: latch, 33 (
33R; 33c, 33e): Counter, 34
(34R, 34c, 34s): Oscillator, 35
(35R, 35c, 35e): ROMa Patent Applicant: Toshiba Electric Materials Co., Ltd. Agent: Patent Attorney: Tatsuo Ito Attorney: Patent Attorney: Tetsuya Ito

Claims (1)

[Claims] 1. Outputs each of the three primary colors of red, edge and blue. A display surface comprising a large number of display elements of three colors arranged in a matrix, and a luminance corresponding to the position and color of each display element in the video to be displayed on the display surface by digitally processing a color video signal. A to create gradation data of
/D conversion means, reference clock generation means with variable output frequency, and a number of M corresponding to the above-mentioned gradation data for each fixed time.
In the color display device, the reference clock generating means is set to three times corresponding to the color of the display element.
In addition, the display control means is operated with separate reference clocks for each color of the upper white display element, and by individually changing the frequency of these reference clocks, the pulse width for driving the display element of each color is individually changed. The feature is that the display brightness and white balance of each color can be adjusted by
7J RaL display device. 2. The reference clock generation means includes a ROM in which gradation pulse width control is written in accordance with the video signal and the gradation data/luminance characteristics of the display element, and the reference clock generation means provides the reference clock to the display control means. The first aspect of the present invention is characterized in that the luminance characteristics of the display element are corrected by converting the pitch of the gradation pulse based on the gradation pulse pitch.
Color display device as described in section.