TWI545540B - Displaying apparatus with titled screen and display driving method thereof - Google Patents

Description

Splicing screen display device and display driving method thereof

The present invention relates to a splicing screen display device, and more particularly to a driving technique for a splicing screen display device.

For a large display area, such as a digital billboard, or an indoor video wall, since the display area is much larger than the area of a single display device, the image is displayed by the splicing screen display device.

The so-called screen display device has a plurality of tile screens respectively displaying a part of an image, and the secondary screens are spliced into a large-sized display screen. FIG. 1 is a schematic diagram showing the structure of a conventional splicing screen. Referring to FIG. 1, a large-sized splicing screen 100 is formed by splicing a plurality of small-sized secondary screens 102 in an MxN matrix manner. Here, the M value is generally larger than the N value, but may be equal to N to form a splicing screen 100 having a large square shape. Each of the secondary screens 102 displays a portion corresponding to an image, and the individual images of the secondary screens 102 combine to form a complete image to be displayed.

In the current splicing screen product of a Light-Emitting Device (LED) array, an LED driver is used to drive the LED array to achieve a display effect. Taking the pitch of P1.488 as an example, a 12cm square secondary screen, based on a color pixel, is composed of three LEDs of red, green and blue, which requires about 6,400 beads. In general, a 16-channel driver is used, which requires approximately 60 drivers. This requires more LED drivers for fine pitch requirements. This is not only a problem of heat dissipation at fine pitches, but also a limitation in the manufacturing process.

FIG. 2 is a schematic diagram showing the architecture of a conventional secondary screen 102. Referring to FIG. 2, for a secondary screen 102, n scan lines are used to display images, and each scan line has m pixels. Each monochromatic pixel is an LED lamp bead. Thus, after scanning the n scan lines, the image to be displayed on the screen 102 can be presented, which is a part of the overall image. The pixels are generally composed of a light-emitting device, but may be a liquid crystal (LC) pixel. Another color pixel is generally composed of three pixels of red/green/blue, and is combined into the color to be presented by the other gray scale values of the red/green/blue three pixels. Therefore, there will still be some number of n scan lines on the secondary screen 102, and some number of m pixels on the scan line. The activation of these m×n×3 color pixels is driven by a plurality of drivers provided by a plurality of drivers, and corresponding to each color pixel, the required grayscale values are converted into voltages to drive the m×n× The light-emitting elements of the three color pixels enable the corresponding brightness to be emitted. Therefore, for a secondary screen 102, since the number of channels of the driver is low, a large number of drivers are conventionally required, which causes problems such as heat dissipation and the like.

More specifically, FIG. 3 is a schematic diagram showing the driving mechanism of the conventional splicing screen 100. Referring to FIG. 3, the host 50 will input the digital frame data of the image to be displayed. The controller 60 (Controller, TC) is fed. The controller 60 controls a plurality of drivers 62. The channels provided by these drivers 62 correspond to the pixels connected to the splicing screen 100. Therefore, in one image display, the controller 60 transmits the illuminating source elements of each pixel according to the predetermined brightness by the driver 62. Start up to form a display image. These drivers 62 are actually grouped and are disposed behind the secondary screens 102 as described above.

The conventional method of driving the secondary screen 102 is to use a driver 62 having a low cost and having only a small number of channels, which are directly disposed at the back of the secondary screen 102 to be connected to the circuit substrate. However, one secondary screen 102 still has a significant number of m x n x 3 color pixels, so a secondary screen 102 would require multiple drivers 62. As the image resolution of the image increases, the image resolution (m×n) of the secondary screen 102 also increases. As such, the number of drivers 62 required for the secondary screen 102 will also increase, which may result in a secondary screen 102 requiring a greater number of drivers, which may not be adequately accommodated except for the area available behind the secondary screen 102. These drive problems can cause heat dissipation problems.

Therefore, it is necessary to change the design of the conventional splicing screen 100 in response to the situation that the image tends to be high resolution.

The present invention provides a splicing screen display device and a display driving method thereof, at least in addition to reducing the number of drivers used in the secondary screen. In addition, you can increase the color level of the displayed image.

According to an embodiment of the invention, a splicing screen display device includes a display screen that is spliced by a plurality of secondary screens. Multiple data drives, respectively driving the Some screens. The frame rate control circuit increases the original frame rate by a multiple of K according to an original frame rate of the received image, and K is an integer greater than or equal to 2, so as to correspond to a frame period determined by the original frame rate, K frames will be generated for these data drives. The frame rate control circuit also corrects an original grayscale value of each pixel, and determines that a number of frames in the K frame are grayscales after adding a grayscale to the original grayscale value. The value is displayed, and the number is one of 0 to K-1.

Another embodiment of the present invention provides a display driving method for a splicing screen display device, wherein the splicing screen display device includes a display screen, a plurality of data drivers, and a frame rate control circuit. The display screen is composed of multiple times. Screen stitching. The display driving method includes: configuring the data drivers to respectively drive the plurality of screens; and the frame rate control circuit increases the original frame rate by a K factor according to an original frame rate of the received image, K An integer greater than or equal to 2, such that during a frame determined by the original frame rate, K frames are generated for the data drivers; and by the frame rate control circuit, for each pixel An original grayscale value is corrected, and it is determined that a number of frames in the K frame are displayed by adding a grayscale value to the original grayscale value, and the number is 0 to K- One of the ones.

In an embodiment of the invention, the K value is 2 ^L and L is a natural number.

In one embodiment, the L value is two. The grayscale value generated by the whole of the 2 ^L frames is a grayscale degree of 0, 1/4, 2/4 or 3/4 of the original grayscale value, wherein 0 corresponds to the pixel in the 2 ^L The original grayscale value is displayed in the frame; 1/4 of the corresponding pixels in the 2 ^L frames have 3 frames showing the original grayscale value, and 1 frame shows the original grayscale The step value is added to the modified gray scale value of the one gray scale; 2/4 indicates that the pixel has 2 frames in the 2 ^L frames to display the original gray scale value, and 2 frames show the The original gray scale value is added to the modified gray scale value of the one gray scale; 3/4 indicates that the pixel has 1 frame in the 2 ^L frames to display the original gray scale value, and there are 3 frames The original grayscale value is added plus the modified grayscale value of the one grayscale.

In one embodiment, the image is stored in a frame memory, and correspondingly assigned to the plurality of screens according to the combination of the plurality of screens.

In one embodiment, the image is pre-allocated to the screens and then stored in a plurality of frame memories corresponding to the screens.

In an embodiment, the original frame rate is 60 Hz or 50 Hz. The frame rate of the K frames is 240 Hz or 200 Hz.

The above described features and advantages of the invention will be apparent from the following description.

50‧‧‧Host

60‧‧‧Controller (C)

62‧‧‧ drive

100‧‧‧Splicing screen

102‧‧‧ screens

210‧‧‧Sequence Controller (TC)

212‧‧‧ Frame Rate Control Circuit (FRC)

220‧‧‧Data Drive

222‧‧‧ gate driver

S250~S256‧‧‧Steps

FIG. 1 is a schematic diagram showing the structure of a conventional splicing screen.

FIG. 2 is a schematic diagram showing the architecture of a conventional secondary screen 102.

FIG. 3 is a schematic diagram showing the driving mechanism of the conventional splicing screen 100.

4 is a schematic diagram of a splicing screen display device according to an embodiment of the invention.

5(a)-5(b) are schematic diagrams showing driving signals of a splicing screen display device conforming to the VESA standard according to an embodiment of the invention.

FIG. 6 is a schematic diagram of a display driving method according to an embodiment of the invention.

FIG. 7 is a schematic diagram of a display driving method according to an embodiment of the invention.

FIG. 8 is a schematic diagram showing the relationship between gray scale values and gray scale voltages according to an embodiment of the invention.

FIG. 9 is a schematic diagram of a mechanism for generating a grayscale correction by a frame rate control circuit according to an embodiment of the invention.

The invention proposes a driving mechanism for the splicing screen display device, in addition to reducing the number of drivers used in the secondary screen, and also increasing the color gradation of the displayed image. The invention is illustrated by the following examples, but the invention is not limited to the examples.

In considering the problem of how to reduce the number of drivers required for a secondary screen, the present invention proposes to use a driver used in a general flat panel display without using a conventional driver of the splicing screen.

The driving architecture proposed by the present invention uses a source driver such as a flat panel display and a gate driver to drive LED pixels. In addition, since the image resolution is relatively low due to a single screen, the original digital signal can be redistributed. In addition, it is also possible to generate a faster frame rate to increase the grayscale resolution to increase the color gradation and to display richer colors.

4 is a schematic diagram of a splicing screen display device according to an embodiment of the invention. Referring to FIG. 4, the image resolution of the flat panel display panel is far greater than that of the secondary screen 102. A typical flat panel display is, for example, a liquid crystal display panel (LCD panel) or a light emitting element display panel (LED panel), and its image resolution is, for example, 720×480, 1920×1080 or even higher image resolution. Therefore, in the case of a driver for a flat panel display panel, such as a single data driver 220, It has a larger number of drive channels than the number of channels required for one of the secondary screens in the splicing screen 100. Therefore, in the secondary screen of the present invention, for the data driver, for example, only one need is needed, or in response to the development of higher image resolution, a single screen can be driven by only a small number of data drivers. Since the driving mode of the data driver 220 and the gate driver 222 is adopted, the control mechanism of the data controller 220 and the gate driver 222 by the timing controller (TC) 210 is required, and it is also required to be changed.

Thus, in the splicing screen display device of the present invention, the number of data drivers 220 required for one sub-screen can be reduced to one, or a small amount, without affecting the problem of heat dissipation, and thus can be displayed in response to high image resolution.

5(a)-5(b) are schematic diagrams showing driving signals of a splicing screen display device conforming to the VESA standard according to an embodiment of the invention. Referring to FIG. 5(a), under the VESA standard, the vertical sync signal (Vsync) corresponds to a frame, so the digital data of one image, which is also called frame data, is input during a vertical sync signal. In other words, the frequency of the vertical sync signal is the frame rate, which is typically 60 Hz or 50 Hz. When the pulse of the vertical sync signal is generated, the horizontal sync signal (Hsync) is generated by the gate driver to scan the image of each line, that is, during the period of a vertical sync signal, n pulse signals are required to be added. Buffer pulses during buffering before and after. Between the periods of the horizontal sync signal (Hsync), a signal (DE) is issued to define the time input by the data driver, that is, the gray scale voltages of the m pixels on a scan line need to be in the signal (DE). Drive the secondary screen during the cycle. Figure 5(b) shows the timing relationship between the horizontal sync signal (Hsync) and the signal (DE). The signal (DE) needs to drive the display of the grayscale value of the pixel of a horizontal scan line during the high level. So, a vertical sync signal (Vsync) triggers a frame display.

The present invention employs a flat panel display driver to drive the secondary screen. Since the driver of a flat panel display is based on its display performance, its clock speed can be faster, for example, a frame rate of 240 Hz or higher can be achieved. Such a frame rate for a secondary screen display, its driving ability is greater than the demand. In addition, for a standard 60 Hz frame rate, it is equivalent to one pixel at the same gray level, which will maintain a display time of about 1/60 second. Moreover, due to the image displayed by the splicing screen, the gray scale resolution is small, for example, the resolution of 6 bits, that is, the gray scale value is only 2 ⁶ = 64 gray scale values, so the color level is insufficient, and generally The image used in the flat panel display has a grayscale resolution of up to 2 ⁸ = 256 grayscale values. Therefore, in the present invention, when using a high drive channel and a high frame rate data driver, in addition to reducing the number of data drivers used in one secondary screen, for example, one, and the present invention also proposes to adopt frame rate control. A Frame Rate Control (FRC) circuit 212, such as that shown in Figure 4, can achieve greater color resolution, the mechanism of which will be described later. Frame Rate Control (FRC) circuit 212 is typically integrated into timing controller (TC) 210, but this is not the only way.

FIG. 6 is a schematic diagram of a display driving method according to an embodiment of the invention. The basic processing flow will be described first. Referring to FIG. 6, in step S250, the complete frame material to be displayed is input and stored in the frame memory. In step S252, the allocation unit is based on the matrix structure of the secondary screen of the splicing screen 100, when the image is divided so as to be properly allocated to each of the secondary screens. At step S254, the frame rate control circuit changes the original frame rate, e.g., 60 Hz, to a higher frame rate, such as 240 Hz. According to the highest frame rate allowed, it is generally 2 ^L times 60 Hz, and L is a natural number, that is, 1, 2, 3, ..., N. The upper limit here depends on the highest frame rate of the drive. At a frame rate of 240 Hz, which is a frame rate that is increased by 4 times relative to 60 Hz. Therefore, during the original frame of 60 Hz, there are 4 frames that can be changed. There is a vertical sync signal period of 60 Hz, at 240 Hz, changed to 4 vertical sync signals, so in addition to the original image, you can insert another three image display, the grayscale value will be changed later 8 and 9 are described in detail. After the adjustment of the frame rate in step S254, in step S256, the original frame data and the inserted frame data are sequentially driven to display the images through the data driver.

FIG. 7 is a schematic diagram of a display driving method according to an embodiment of the invention. Figure 7 depicts another variation of the embodiment, but the mechanism is still similar to Figure 6, with the differences as follows. In the embodiment of FIG. 7, each of the secondary screens is provided with a corresponding frame memory, and the capacity of the frame memory only needs to be able to store the image of the secondary screen. With respect to Fig. 6, step S250 and step S252 of Fig. 7 are interchanged. In step S252, the input image to be displayed is allocated before the frame memory is stored, and then the allocated sub-frame data is stored in the corresponding sub-frame memory in step S250. Subsequent steps S254 and S256 are the same as in FIG.

The correction mechanism of the grayscale value by the frame rate control (FRC) circuit 212 is described below. As is generally known, a color pixel is composed of three pixels of red/green/blue, which uses its three monochromatic pixels to generate the brightness of the single color according to the gray scale value, and is composed of red, green, The brightness of the blue three monochromatic pixels blends a color pixel. Therefore, changes in the grayscale value will produce a color change that is presented. In addition, based on the characteristics of the human eye's persistence of vision, the color to be changed is generally determined by the integrated color received at 16.67 ms, so the increased frame rate can be used to adjust the final mixture of multiple frames. Grayscale value.

First, the gray level of the digit is compared with the gray scale voltage actually driven. Since the brightness of liquid crystallin or LED is determined by the applied voltage or current, it is generally not a linear change. FIG. 8 is a schematic diagram showing the relationship between gray scale values and gray scale voltages according to an embodiment of the invention. Referring to Figure 8, a monochromatic pixel, taking the 6-bit grayscale value as an example, has a linear 64 grayscale, but the driving voltage required for each grayscale is not linear, so gamma needs to be utilized. The curve is used to correct the driving voltage, so that for a gray scale value g _i , the corresponding driving voltage V _{i is} obtained by using the gamma curve. But based on, for example, a 6-bit circuit, it will only generate 64 voltages. Therefore, the grayscale resolution is 64 steps.

The following describes how to generate other gray levels by the frame rate control (FRC) circuit 212 under 64 gray levels of 6 bits. FIG. 9 is a schematic diagram of a mechanism for generating a grayscale correction by a frame rate control circuit according to an embodiment of the invention. Referring to FIG. 9, a frame rate of 240 Hz is taken as an example. A frame at a frame rate of 60 Hz can generate corresponding frames by frame rate control (FRC) circuit 212 to f1. Expressed by f2, f3, and f4. For a pixel, the grayscale value that it is originally intended to display is, for example, g _i .

If the gray scale values of g _i are displayed in the four frames f1 to f4, the gray scale values g _{i are} maintained after the four frames f1 to f4 are mixed, so the correction of the gray scale values is zero. If any of the four frames f1 to f4 is, for example, the frame f1, the grayscale value g _i of the pixel of the frame f1 is incremented by 1 to become g _i +1. In addition, the other three frames f2 to f4 maintain the gray scale value g _i . In this way, the four frames f1 to f4 can be mixed to obtain a correction of 1/4 gray scale. If any two of the four frames f1 to f4 are, for example, frames f1 and f2, the grayscale value g _i of the pixel of the frames f1 and f2 is incremented by 1 to become g _i +1. In addition, the other two frames f3 and f4 maintain the gray scale value gi. In this way, the four frames f1 to f4 are mixed to obtain a correction of increasing the 2/4 gray scale. If any three of the four frames f1 to f4 are, for example, frames f1, f2, and f3, the grayscale value g _i of the pixels of the frames f1, f2, and f3 is added. 1 becomes g _i +1. In addition, the other frame f4 maintains the gray scale value g _i . In this way, the four frames f1 to f4 are mixed to obtain a correction of increasing the 3/4 gray scale.

Based on the above mechanism, although the circuit is a 6-bit circuit, after increasing the frame rate, the effect corresponding to the 8-bit circuit can be achieved in this embodiment, with a variation of 256 gray levels. Since the frame rate control circuit can be increased to 256 grayscale changes, the frame rate control circuit has an image processing function for the image to be displayed, and the gray scale of the pixel is corrected under the condition of 256 grayscale changes. The value is such that it has a richer color change.

It should be noted that the frame rate is not limited to the increase of 4 times (240 Hz) in the embodiment, and the other 120 Hz or 480 Hz can be applied equally, and the resolution of the gray scale can be increased by the same reason. . Here, the frame rate of this order multiplication is 2 ^L , L=1, 2, . . . , which is therefore consistent with the bits of the gray scale. This is also generated by multiplying the clock.

However, in general, according to the same mechanism, other frame rates such as 180 Hz, 360 Hz, etc. can also be achieved, wherein the increase of the frequency requires different circuits, not only by frequency doubling, such as 120 Hz or 480 Hz. Can be achieved. For example, 180 Hz and 360 Hz, three or six frames are generated relative to 60 Hz, and the gray scale value is adjusted by 1/3 and 1/6 as a gray scale unit for adjustment. In addition, if the gray-scale circuit is the resolution of 8-bit or higher, it can still use the FRC circuit to increase its gray-scale resolution, and is not limited to a 6-bit gray-scale circuit.

In other words, with respect to the general feature, the FRC circuit of the present invention can increase the original frame rate by K multiple according to the maximum possible driving rate of the driver, and K is an integer greater than or equal to 2. In this way, corresponding to the frame rate determined by the original frame rate, K frames are generated for the data driver. The frame rate control circuit also corrects an original grayscale value of each pixel, and determines that a number of frames in the K frame are modified grayscales after adding a grayscale to the original grayscale value. The value is displayed, and the number is one of 0 to K-1.

Moreover, due to different playback formats, such as NTSC and PAL, the video playback rate is 50 Hz, and the present invention is also applicable to a 50 Hz playback rate.

In summary, the present invention provides a secondary screen for the data driver, which can be driven by only one or a small number of data drivers, so as to avoid an excessive number of images when the image resolution is greatly increased. The case where the drive occupies a usable area. In addition, based on the speed of the data driver, the processing of the FRC circuit can increase the grayscale resolution and enrich the color of the image.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

50‧‧‧Host

100‧‧‧Splicing screen

210‧‧‧Sequence Controller (TC)

212‧‧‧ Frame Rate Control Circuit (FRC)

220‧‧‧Data Drive

222‧‧‧ gate driver

Claims (8)

A splicing screen display device includes: a display screen, which is spliced by a plurality of secondary screens; a plurality of data drivers respectively driving the plurality of screens; and a frame rate control circuit, according to an original frame rate of the received image, K multiplier increases the original frame rate, K is an integer greater than or equal to 2, so that during a frame determined by the original frame rate, K frames are generated for the data drives, where the frame rate The control circuit also corrects an original grayscale value of each pixel, and determines that a number of frames in the K frame are displayed by adding a grayscale value to the grayscale value of the original grayscale value. The number is one of 0 to K-1, wherein the K value is 2 ^L , and L is a natural number, wherein the L value is 2, wherein the gray scale value generated by the 2 ^L frames as a whole is The original grayscale value is increased by 0, 1/4, 2/4, or 3/4, where 0 corresponds to the pixel, and the original grayscale value is displayed in the 2 ^L frames; 1/4 pair there should be three pixel frame displayed in the original gray level value of 2 ^L dpi frame, while a frame Shows the original grayscale value plus the original gray scale a gray scale of the correction value; 2/4 indicates that the pixel has two frame displays the original gray level value of the frame 2 ^L dpi, while 2 a frame displaying the original grayscale value plus a gray level of the gray level value of the correction; 3/4 indicates that the pixel has a display frame of the original gray level value of the frame 2 ^L dpi, and There are 3 frames showing the original grayscale value plus the modified grayscale value of the one grayscale. The splicing screen display device of claim 1, further comprising a frame memory, wherein the image is stored in the frame memory, and according to the The combination of screens is assigned to the screens. A splicing screen display device comprises: a display screen, which is spliced by a plurality of secondary screens; a plurality of data drivers respectively driving the plurality of screens; and a frame rate control circuit, according to an original frame rate of the received image, The multiple increases the original frame rate, K is an integer greater than or equal to 2, so that during a frame determined by the original frame rate, K frames are generated for the data drives, wherein the frame rate control The circuit also corrects an original grayscale value of each pixel, and determines that a number of frames in the K frame are displayed by adding a grayscale value to the original grayscale value. The number is one of 0 to K-1; and the plurality of frame memories respectively correspond to the screen configuration, and the images are stored in the frame memory respectively after the screens are pre-allocated. A splicing screen display device includes: a display screen, which is spliced by a plurality of secondary screens; a plurality of data drivers respectively driving the plurality of screens; and a frame rate control circuit, according to an original frame rate of the received image, K multiplier increases the original frame rate, K is an integer greater than or equal to 2, so that during a frame determined by the original frame rate, K frames are generated for the data drives, where the frame rate The control circuit also corrects an original grayscale value of each pixel, and determines that a number of frames in the K frame are displayed by adding a grayscale value to the grayscale value of the original grayscale value. , the number is one of 0 to K-1, The original frame rate is 60 Hz or 50 Hz, and the frame rate of the K frames is 240 Hz or 200 Hz. A display driving method is used for a splicing screen display device, wherein the splicing screen display device comprises a display screen, a plurality of data drivers, and a frame rate control circuit, wherein the display screen is formed by splicing a plurality of sub-screens, the display driving The method includes: configuring the data drivers to respectively drive the screens; and the frame rate control circuit increases the original frame rate by a K factor according to an original frame rate of the received image, where K is greater than or An integer equal to 2, such that during a frame determined by the original frame rate, K frames are generated for the data drivers; and by the frame rate control circuit, a primitive for each pixel The grayscale value is corrected, and it is determined that a number of frames in the K frame are displayed by adding a grayscale value to the original grayscale value, and the number is 0 to K-1. One, wherein the K value is 2 ^L , and L is a natural number, wherein the L value is 2, wherein the gray scale value generated by the 2 ^L frames as a whole is 0, 1/4 of the original gray scale value, 2/4 or 3/4 ash steps , Where 0 pixel to be the 2 ^L dpi boxes show the original raw grayscale value; should be 1/4 to 2 ^L of the two pixels in FIG. 3 has a box frame displays the original gray value , while FIG. 1 shows the original frame plus the gray level value of the original gray scale a gray scale of the correction value; 2/4 indicates that the pixel has two frame displayed in the original dpi of the box 2 ^L grayscale value, while FIG. 2 show the frame of the original grayscale value plus the correction of a gray value gray level; 3/4 indicates that the pixel has a display frame in the frame 2 ^L dpi The original grayscale value, and three frames display the original grayscale value plus the modified grayscale value of the one grayscale. The display driving method according to claim 5, wherein the image is stored in a frame memory, and correspondingly allocated to the plurality of screens according to the combination of the plurality of screens. A display driving method is used for a splicing screen display device, wherein the splicing screen display device comprises a display screen, a plurality of data drivers, and a frame rate control circuit, wherein the display screen is formed by splicing a plurality of sub-screens, the display driving The method includes: configuring the data drivers to respectively drive the screens; and the frame rate control circuit increases the original frame rate by a K factor according to an original frame rate of the received image, where K is greater than or An integer equal to 2, such that during a frame determined by the original frame rate, K frames are generated for the data drivers; by the frame rate control circuit, an original gray for each pixel The order value is corrected, and it is determined that a number of frames in the K frame are displayed by adding a gray scale value to the original gray scale value, and the number is one of 0 to K-1. And the image is pre-allocated to the screen, and then stored in multiple frame memories corresponding to the screen. A display driving method is used for a splicing screen display device, wherein the splicing screen display device comprises a display screen, a plurality of data drivers, and a frame rate control circuit, wherein the display screen is formed by splicing a plurality of sub-screens, the display driving The method includes: configuring the data drivers to drive the screens separately; By the frame rate control circuit, according to an original frame rate of the received image, the original frame rate is increased by K multiple, and K is an integer greater than or equal to 2, so that a picture corresponding to the original frame rate is determined. During the frame, K frames are generated for the data drivers; and the frame rate control circuit corrects an original grayscale value of each pixel, and determines that there is a quantity in the K frames. The frame is displayed by adding a gray scale value to the original gray scale value, and the number is 0 to K-1, wherein the original frame rate is 60 Hz or 50 Hz, the K The frame rate of the frame is 240Hz or 200Hz.