JPS6333178Y2 - - Google Patents

Description

[Detailed explanation of the invention] [Industrial application field] This invention is based on a display screen that displays fish detection information from a fish finder installed on a fishing boat. The present invention relates to a fish school/fishing net detection/display device capable of displaying detection information in a combined manner and displaying one of them independently.

[Conventional technology]

In cathode ray tube display type fish finders, this is a new type of display device that provides a continuous recording type display, similar to the record paper type, and uses fish detection signals obtained by transmitting and receiving ultrasonic waves underwater. There are devices that display on one display line in the depth direction for each detection cycle, and that can be displayed while shifting so that the display line is sequentially displayed on a new display line for each detection cycle. On the display screen of such a fish finder, it is possible to display the detection information under display conditions different from the display conditions of the detection information currently being displayed, or to display the detection information in combination with other detection information, and to display only one of them independently. Such a device is disclosed in Japanese Patent Application No. 51-1380 (Japanese Unexamined Patent Publication No. 53-63053) filed by the applicant of the present application.

[Problem to be solved]

In devices that can perform the above display, if the detection information that should be combined and displayed is fishing net detection information sent from the net monitor, this information may have a different detection cycle than the fish finder information. The synchronization relationship is also completely unrelated, so displaying this on the same display line requires a rather complicated configuration.
It has to be expensive.

Therefore, there is a problem in that it is desired to provide a practical and inexpensive device with a relatively simple configuration.

[Means for solving problems]

This idea collects information within one detection period of the fish detection signal.
For capturing fish detection information that stores the amount of memory required to capture the time point obtained based on the oscillation signal for obtaining the fish detection signal and display it on the full width of one display line in the depth direction. The information within one detection cycle of the fishing net side detection signal is based on the synchronization signal in the fishing net side detection signal immediately after the storage contents of the one display line information acquisition memory described later are loaded into the display screen memory. A memory for capturing fishing net detection information and a memory for capturing fish detection information, which stores the amount of memory necessary to capture the information based on the time point obtained by the method and display it on the entire width of one display line in the depth direction. The amount of memory required to display one display line in the depth direction by importing only the memory content or the memory content of both the memory for capturing fish detection information and the memory for capturing fishing net detection information. Only the memory contents of the memory for capturing display line information and the memory for capturing fish detection information are stored in one memory.
Fish detection display line storage means for capturing and storing the memory contents of the fish detection information capture memory as is in the display line information capture memory; and Fish detection display line storage means. The memory contents of the memory for capturing and the memory contents of the memory for capturing fishing net detection information are
In order to display the information cascaded along the display lines of the book, the contents of the memory for capturing fish detection information are intermittently imported according to the required compression ratio, and then the contents of the memory for capturing fishing net detection information are imported intermittently according to the required compression ratio. a fish school detection/fishing net detection display line storage means for intermittently capturing data according to a necessary compression rate and storing it in a memory for one display line information acquisition; and a circuit or fish school for operating the fish school detection display line storage means. The above problem is solved by providing a selection switch for selecting either one of the circuits for operating the detection and fishing net detection display line storage means, This invention is based on the fish school and fishing net detection display component of the device disclosed in Japanese Patent Application No. 51-138029 (Japanese Unexamined Patent Publication No. 53-63053) by the applicant mentioned above.

〔Example〕

Examples will be described below with reference to the drawings.

First, to explain the configuration of the basic parts of a fish finder, as shown in Figure 1, the transmitter/receiver section 11 of the fish finder.
The transmitter/receiver 23 is excited at a constant cycle from the transmitter 1 in the transmitter/receiver via the transmitter/receiver circuit 2. As a result, ultrasonic pulses from the transducer 23 are radiated toward the seabed 3. The reflected wave is received by the transducer 23 and received by the receiver 4 through the transmitter/receiver circuit 2. This received signal consists of an oscillation pulse 25, a reflected signal 26 from the fish school 5, a reflected signal 27 from the seabed 3, etc., as shown in FIG. 2A. This received signal is
It is converted into, for example, a 4-bit digital signal in the AD converter 28, and the digital signal is written into the data acquisition memory 34. The data acquisition memory 34 is, for example, a shift register, and can simultaneously write as many digital signals as the number of parallel bits output from the AD converter 28. In this writing, a write pulse (FIG. 2B) generated in the write pulse generation circuit 6 from a signal from an oscillator (not shown) in the transmitter 1 is passed through the OR circuit 56 to the memory 3.
4 and is carried out.

On the other hand, a color cathode ray tube display 82 is provided,
The display surface of the display 82 is scanned by an electron beam controlled by a line synchronization signal and a surface synchronization signal from the cathode ray tube control circuit 7. The readout signal from the main memory 81 passes through the color converter 177 to the display 8.
2. The main memory 81 is made up of, for example, a shift register and has a capacity to store information on one screen of the display surface of the display device 82, and for easy understanding, the line scanning lines l ₁ , l _{2 . . . lo} There are shift register sections F ₁ , F ₂ , ...F _o corresponding to
These register sections are connected sequentially and continuously. At a certain point in time, the digital information in register portions F ₁ , F ₂ , . . . F _o is displayed on scan lines l ₁ , l _{2 ,} . The output of the latter stage of the shift register section F _o is supplied to the color converter 177 and is fed back to the first stage of the shift register section F ₁ through the gate circuit 8 , so that the one cycle period is the same as the surface scanning period of the display 82 . The shift speed is selected.
In this state, the contents of the main memory 81 are displayed on the display 8.
2 is displayed as a still image. Each stage of the shift register sections F ₁ to F _o can each store a parallel 4-bit digital signal. The color converter 177 performs signal conversion to cause the display 82 to emit a predetermined color according to the input digital signal, that is, the level of the signal.
The output shows the red color on the color cathode ray tube display 82;
Green and blue electron guns are controlled.

In the transmitter/receiver section 11, a received signal corresponding to one oscillation pulse is captured into a data capture memory 34, and the signal in this memory 34 is transferred to the main memory 81 as information on one display line. This new signal is then displayed at a predetermined position on the display. For example, in the figure, the newest signal is displayed on the first scanning line _l1 . The data acquisition memory 34 has one of each shift register section F ₁ to F _o of the main memory 81.
It is assumed that the capacity is the same as the one. When writing to the memory 34 is completed, a signal indicating this is supplied to the read pulse generation circuit 9. This circuit 9 includes a control circuit 7
A surface synchronization signal Pv and a line synchronization signal Pl shown in FIG. 2C are supplied from. The read pulse is set to 1 as shown in FIG.
Occurs during the line sync signal period. This read pulse is synchronized with the shift pulse of the main memory 81 and is the same number as the write pulse number. Read pulse is OR circuit 5
6 to read out the acquisition memory 34, and its output is supplied to the first stage of the shift register _F1 through a gate circuit 8. When the transfer from the memory 34 to the main memory 81 is completed, the output of the main memory 81 is returned to the first stage shift register section _F1 through the shift register 124 for delaying one scanning line. The feedback through the delay shift register 124 is during the period from the end of reading from the memory 34 until the next surface synchronization signal, as shown in FIG. 2E. In this way, once the signal is transferred from the memory 34 to the main memory 81 and input to the register section _F1 ,
The oldest data that had been in the shift register section F _o until then is moved to the delay shift register 124,
Since the return time from the shift register 124 to the main memory 81 is shorter than the one-line scan period Tv as shown in FIG. Removed from 81.

In this way, each time data is transferred from the memory 34 to the main memory 81, the newest data is displayed on the line scanning line _l1 , the oldest data is removed from the main memory 81, and the display line on the display surface is Move one line at a time in the direction perpendicular to that line, toward the older one,
The second newest data is displayed on line scan line _l2 . As a result, the oscillation line 1 corresponding to the oscillation pulse 25
55 corresponds to seabed 3 and display 153 is fish school 5
A display 154 corresponding to each appears on the display surface of the display 82. In other words, a display similar to the record on the record paper of a conventional fish finder is obtained, and the display moves from right to left in the same way as when the record paper is moved from right to left in FIG.

The above is the basic configuration for displaying only the fish detection information over the entire width of the display line.Hereinafter, the configuration for displaying expanded information of the fish detection information or fishing net detection information in combination will be explained. Figures 3 to 5
The figure is a divided view of what should originally be shown as a single drawing, and the symbols in circles attached to the ends of each lead wire indicate that the same wires are connected to each other. In FIG. 3, the transmitting/receiving section 11 is almost the same as that of a conventional fish finder. That is, the reference signal from the reference oscillator 12 is frequency-divided by the range frequency divider 13, and the frequency division ratio is changed by selecting the range switch. In other words, the detection range is 0-100m, 0-200m, 0-400m, 0-800m.
The frequency division ratio of the frequency divider 13 is changed depending on which of the above is selected, and the deeper the search is performed, the higher the frequency division ratio is and the lower the frequency of its output is.

The output frequency-divided in this manner is selected by the display time switching circuit 15 as one of three frequency division ratios, for example, the standard, double the standard, or 1/2 of the standard. This circuit is unique to this fish finder using a cathode ray tube, and when the three-point switch 16 is selected to select one of the switching positions, the normal display is displayed.
When in the other switching position, the display is fast-forward and the output frequency is doubled, and when it is in another switching position, the display is slow-forward and the output frequency is 1/2 of the normal display. That is, the changeover switch 16 can be used to speed up or slow down the rewriting time of information in the main memory 81 that stores display information for the cathode ray tube display 82, which will be described later.

The output of the display time switching circuit 15 is further frequency-divided by a repetition period counter 17, thereby creating a trigger oscillation period. The output of this repetition period counter 17 is shown, for example, in FIG. 6A, and this output is differentiated by a differentiating circuit 18, and, for example, its rising pulse (FIG. 6B) is extracted. This rising pulse is generated by the stuttering correction circuit 19 for a time equal to the propagation time of the ultrasonic pulse at a depth below the water surface where the transducer 23 is attached, using, for example, a monostable multivibrator, as shown in FIG. 6C. converted into a pulse of time T ₁ . The converted output is supplied to the transmission trigger generation circuit 21, and as shown in FIG. 6D, a trigger signal delayed by the time _T1 from the differential pulse (FIG. 6B) is obtained.

This trigger signal drives the transmitter 22, and its output excites the transducer 23, so that ultrasonic pulses are emitted toward the ocean floor. Based on the transmission of this ultrasonic pulse, the reflected signal is received by the transducer 23 and received by the receiver 24,
For example, as shown in FIG. 6E, an oscillation pulse 25, a reflected signal 26 from a school of fish, and a seabed reflected signal 27 are received. The output of the receiver 24 is converted by an AD converter 28 into, for example, a parallel 4-bit digital signal, which is then supplied to each of a plurality of data acquisition sections.

As the data acquisition section, a normal display data acquisition section 31, a partially enlarged display data acquisition section 32, and an enlarged seabed display data acquisition section 33 are provided, and the data acquisition memory 34 of these data acquisition sections 31, 32, and The output of the AD converter 28 is supplied to 35 and 36, respectively.

Further, as shown in FIG. 7, a transducer 23 of a fish finder is attached to the seabed of the fish boat 37, thereby transmitting and receiving ultrasonic waves as described above. At the same time, a fishing net 39 is pulled by the rope 38, and a net monitor 41 is attached to the upper part of the fishing net near the opening. Ultrasonic waves are transmitted to the upper and lower sides of this net monitor 41, and the reflected waves are received.
The wave is received by 3.

That is, the signal from the net monitor 41 received by the receiver 43 in FIG. 4 is received by the receiver 42. The upper detection signal part and the lower detection signal part in the received signal are separated by data acquisition sections 44 and 45, respectively. The received signal from the receiver 42 is converted into a digital signal by an AD converter 48 and supplied to data acquisition memories 46 and 47 for these, respectively.

In the normal display data acquisition section 31, the gate signal generation circuit 50 is driven by the pulse from the differentiating circuit 18 as shown in FIG. 6F to generate a gate signal, and the shift pulse counter is controlled by this gate signal. 49 starts a counting operation, and this counter 49 counts the output pulses of the range frequency dividing circuit 13. The count value of the counter 49 is decoded by a decoder 51, and a shift selection switch 52 selects output terminals of the decoder at appropriate intervals. Decoder 5 of shift selection switch 52
As shown in FIG. The gate signal generating circuit 53 is selected, and the sixth gate signal generating circuit 53 is driven.
A gate signal is generated as shown in Figure H. For example, if the second pulse is selected by the switch 52 with the range switch 14 set at 0 to 100 m, the depth range of water between 50 m and 150 m will be detected. The shift pulse counter 49 is configured to count a predetermined number and reach a full count with an interval corresponding to at least one shift distance, in this example 1100 m, before the next trigger pulse is generated. This full count output stops the gate signal generation circuit 50 from sending out the gate signal, and as shown in FIG. 6F, the output becomes low level and the counting operation of the counter 49 is stopped. The gate signal generating circuit 50 is, for example, a flip-flop circuit, and is set by the output of the differentiating circuit 18 and reset by the output of the counter 49. Other gate signal generation circuits are also configured similarly to this gate signal generation circuit 50.

When the output of the gate signal generation circuit 53 becomes high level, the frequency dividing circuit 54 and the data acquisition counter 55
is in an operating state, the frequency of the output of the range frequency dividing circuit 13 is further divided by the frequency dividing circuit 54, and the frequency-divided output is counted by the data acquisition counter 55. Also, the output of the frequency dividing circuit 54 is an OR circuit 56.
The output of the AD converter 28 is applied to the OR circuit 5 for each pulse.
7 to the memory 34. This counter 55 reaches a full count when the number of pixels in one display line on the display 82 is 256, for example, and the gate signal generation circuit 53 is controlled by its output, and its output becomes low level. Therefore, the operations of the frequency dividing circuit 54 and the counter 55 are stopped. In other words, frequency dividing circuit 5
4 to 6I, a data acquisition pulse as shown in FIG. 6I is generated, and the data acquisition memory 34 is, for example, a shift register, and data corresponding to 256 of the data acquisition pulse is acquired.

In the partial enlargement display data acquisition section 32, an arbitrary section is selected and enlarged while the counter 55 is operating, that is, while data is being acquired in the normal display data acquisition section 31.
The count contents of the counter 55 are supplied to a decoder 58, and one of the output terminals of the decoder 58 is selected by an enlargement position selection switch 59. For example, the section of the output gate signal of the selection gate signal generation circuit 53 is divided into five equal parts, and pulses whose phases are sequentially shifted corresponding to each of the five parts are sent to the five fixed terminals of the selection switch 59 as shown in FIG. One of the pulses is selected by the switch 59. This selected pulse causes the output of the gate signal generation circuit 61 to go to a high level as shown in FIG. 6K, and this output causes the frequency dividing circuit 62 and the data acquisition counter 63 to be activated. The output pulse from the reference oscillator 12 is supplied to the frequency dividing circuit 62,
The frequency division ratio of this frequency dividing circuit 62 is changed by an expansion width selection switch 64, and when the expansion width is increased, that is, the expansion rate is increased, the frequency division ratio is small, so that a high frequency output can be obtained. .
This pulse is counted by a data acquisition counter 63 and drives the data acquisition memory 35 through an OR circuit 65, and the output of the AD converter 28 is read into the memory 35 through an OR gate 67.

The counter 63 is similar to the counter 55, for example.
A full count is reached at 256 bits, and the gate signal generation circuit 61 is controlled by the full count output, and its output becomes a low level, and the frequency dividing circuit 62,
Both counters 63 become inactive. In this way, while the output of the gate signal generation circuit 61 (K in FIG. 6) is at a high level, the AD-converted output of the corresponding received signal is generated as 256 sample information, that is, the pixels of one display line. Memory 35 as information
is read into.

In the bottom enlarged display data acquisition unit 33, the gate signal generation circuit 68 is driven by the differential pulse shown in FIG. 6B from the differentiator circuit 18, and the frequency dividing circuit is driven by this output signal (FIG. 6L). 69 is in the operating state. The frequency dividing circuit 69 divides the frequency of the reference signal from the oscillator 12, and the frequency division ratio is changed according to the expansion rate set by the expansion width selection switch 71. Similar to the frequency divider circuit 62, when the frequency is to be significantly expanded, high-speed pulses with a small frequency division ratio are output. The output of the frequency dividing circuit 69 drives the data acquisition memory 36 through the OR circuit 72, and the output of the AD converter 28 is read every pulse. The capacity of this memory 36 is the same as that of the memories 34 and 35, so it becomes full with 256 pulses, but when more data is written than this, each time new data is written, the oldest data is sequentially written. disappears into

On the other hand, the output of the receiver 24 is detected by the low signal detection circuit 73.
This circuit 73 can be a conventional one, and detects, for example, a high signal of a predetermined level or higher from the transmission of an oscillation pulse to the transmission of the next oscillation pulse as a low signal. This bottom signal is a pulse as shown in FIG. The data retrieval operation of the memory 36 is also stopped. The latest data captured at this time is the signal reflected from the ocean floor.
Since such data is always captured, the seabed is always at a constant position on the display line, the seabed line is displayed as a straight line, and the portion above the seafloor is enlarged and displayed according to the frequency division ratio of the frequency divider 69. .

Data import unit 44, 4 for net monitor
The data fetching operation in step 5 will be described later for convenience of explanation, but as described above, the data fetching memories 34, 35, 36, 46,
The data fetched into the buffer memory 79 is fetched into a common buffer memory 79 according to the selection state in the selective reading stages 74 to 78 provided correspondingly thereto. The data taken into buffer memory 79 is transferred to main memory 81, which is repeatedly read out and supplied to cathode ray tube display 82 to be displayed as an image.

Control of the cathode ray tube display 82 is performed as follows. The output signal from the oscillator 83 is passed through the frequency dividing circuit 84 to the line (horizontal) on the cathode ray tube display 82.
The frequency is divided to a scanning period, and its output is supplied to a line synchronization signal generation circuit 85, and this output is supplied to a display 82. The output of the frequency divider 84 is also supplied to a plane (vertical) synchronization signal generation circuit 86, which divides the frequency to produce a plane synchronization signal, which is supplied to the display 82. Information corresponding to one display line of this display 82 is stored in the buffer memory 79, and information for that one display line is transferred to the main memory 81 as described above.

Buffer memory 7 for data from the data import section
9 is done using the clock on the display 82 as a reference.

First, the selective reading means 74 will be described.
The output of the data acquisition counter 55 and the output pulse of the surface sync signal generation circuit 86 are supplied to the sync selection circuit 87. This picture synchronization pulse signal is, for example, the one shown in FIG. 6N, and the next picture synchronization pulse after the trailing edge of the full count output of the data acquisition counter 55, that is, the gate signal shown in FIG. 6H, is selected as shown in FIG. 6O. Ru. The synchronous selection circuit 87 has JK as shown in FIG.
It is a flip-flop, and the write end signal from the counter 55, that is, the full count output is JK.
The signal is supplied to the J terminal of the flip-flop FF ₁ , the Q terminal of the flip-flop FF ₁ goes high, and this is supplied to the clear terminal CL of the JK flip-flop FF ₂ , making the flip-flop FF ₂ ready for operation. Since the plane sync pulse from the plane sync signal generation circuit 86 is supplied to the J terminal of the flip-flop FF ₂ , the flip-flop FF ₂ is set by the plane sync pulse following the write end pulse, and the output of the Q terminal becomes high level. , and its output is supplied to the clear terminal CL of flip-flop _FF3 , enabling this flip-flop to operate. An inverted pulse of a plane synchronous pulse is given to the J terminal of flip-flop _FF3 , and its rise and
In other words, the flip-flop occurs at the trailing edge of the surface synchronous pulse.
FF ₃ is set, and its output resets flip-flops FF ₁ and FF ₂ , which causes the terminal of flip-flop FF ₂ to go low, the terminal of flip-flop FF ₃ to go low, and the write end signal is output from this Q terminal. This means that a pulse at the trailing edge position of the plane synchronous pulse immediately after is obtained.

The gate signal generation circuit 88 is driven by this selected plane synchronization pulse, and from this circuit 88 the sixth
A signal as shown in FIG. A line synchronization signal from the frequency dividing circuit 84 is supplied to the frequency dividing circuit 89, and the frequency division ratio of the frequency dividing circuit 89 is changed by selection of the display width selection switch 92.

For example, there are four fixed terminals of this switch 92, a to d, and when connected to a, the frequency division ratio of the frequency divider circuit 89 is set to 1/8, and when connected to b, the frequency division ratio is set to 1/8. When connected to c, the frequency division ratio is set to 1/2, and when connected to d, it is not connected to the frequency dividing circuit 89 and this selective reading means is not selected. Each negative output of the fixed terminals a to c is supplied to the OR circuit 93, and the output clears the gate signal generation circuit 88.
The output of is held at a low level. When terminal a is selected with the display width selection switch 92, the selected data is displayed as one display line on the display 82, that is, it is displayed across the entire width of the display, and when terminal b is selected, the selected data is displayed as one display line on the display 82. 1/2 width, terminal c
If you select , each will be displayed at 1/4 the width.

The frequency division output of the frequency dividing circuit 89 is output from the read counter 91.
This counter 91 reaches a full count with 256 pulses, similar to the data acquisition counter 55 and the like. As mentioned above, display width selection switch 9
Reference numeral 2 also serves as a switch for selecting or not selecting the selective readout means, and when the switch 92 is located at the terminal d, this selective readout means is not selected, and the output of the gate signal generation circuit 88 is high. It doesn't reach the level. However, if the selective reading means is selected, the switch 92 is connected to the terminal a.
-c, a frequency divided output is obtained from the frequency dividing circuit 89, and not only the counter 91 counts this output pulse, but also the data acquisition memory 34 corresponding to the selective reading means 74 is driven. Data is read from this, and the read data is supplied to buffer memory 79 through OR gate 94.

Writing to buffer memory 79 is performed in synchronization with the slowest pulse among the output pulses of frequency divider circuit 89. That is, the pulse from the frequency dividing circuit 84 is divided into 1/8 by the frequency dividing circuit 95, and the divided output is sent to the buffer memory 79 through the OR circuit 96.
The data from the OR circuit 94 is written into the buffer memory 79 under its control. In order to control this writing, the output of the synchronization detection circuit 89 is also supplied to the gate signal generation circuit 97, which generates a gate signal as shown in FIG. 6Q.
The output of this gate signal causes the frequency divider circuit 95 and the counter 98 to become operational, and the counter 98 counts the output of the frequency divider circuit 95, and when it counts a predetermined number, 256 in this example, the gate signal generation circuit 97 is activated by the output. controlled and its output is at a low level.

The selective reading means 75, 76, 77, and 78 have almost the same configuration as the aforementioned selective reading means 74, and therefore each includes a gate signal generation circuit 88, a frequency dividing circuit 89, a reading counter 91, a display width selection switch 92, and an OR circuit. 93, and these have similar connection relationships. A selection circuit 99 is provided in place of the synchronization detection circuit 87.
The selection circuits 99 of the selection reading means 75 to 78 are sequentially connected in cascade, and the synchronization detection circuit 8 is provided at the preceding stage.
7 is connected. Further, the output of the OR circuit 93 is supplied to the next stage selection circuit 99 via the inverter 101, and the output of the OR circuit 93 is further supplied to the selection circuit 99 at the next stage.
1 and the output of the gate signal generation circuit 88 are also supplied to a selection circuit 99 at the next stage.

As shown in FIG. 9, the selection circuit 99 operates when the output of the inverter 101 at the previous stage is at a low level, that is, when the display width selection switch 92 at the previous stage
Inverter 1 if connected to either c.
Since the output of 01 is at a low level and 102 is closed, the synchronization detection circuit 8 of the selection reading means in the previous stage
7 or the output of the selection circuit 99 cannot pass through the gate 102. However, when the display width selection switch is selected to the terminal d, that is, when the selective reading means is not selected, the output of the inverter 101 of the selective reading means becomes high level, and the gate 102 is opened to open the previous stage selection circuit 99 or the selective reading means. In the case of 75, the activation signal from the synchronization detection circuit 87 passes through the gate 102 and further passes through the OR gate 103 to become the output of the selection circuit 99.

On the other hand, when the display width selection switch 92 is selected to any one of the terminals a to c, the gate 10
2 is closed as described above, and the gate 104 is opened by the output of the gate signal generation circuit 88 at the previous stage.
The final output pulse of read counter 91 is output through gate 104 and further through OR gate 103. In other words, when the selective reading means is not selected, the activation signal from the previous stage is sent as the activation signal to the next stage through the gates 102 and 103, and the display width selection switch 92 selects one of the terminals a to c. If the read counter 9
A full count output of 1 is supplied to the next stage as a start signal.

For example, the activation signal is applied as shown in FIG. 10A, and the output of the gate signal generation circuit 88 becomes high level as shown in FIG. 10B. Assuming that the frequency division ratio of the frequency circuit 89 is large, the readout counter 91 reaches a full count, and the gate signal from the gate signal generation circuit 88 ends as shown in FIG. When the switch 92 is connected to the terminal a, the frequency division ratio of the frequency divider circuit 89 becomes 1/4, so the output frequency is twice that when the switch 92 is connected to the terminal a, and therefore the counter operates at twice the speed. 91
The output width of the gate signal generation circuit 88 reaches the 10th count as shown in FIG.
It will be 1/2 of Figure B.

Assuming that the switch 92 in the selection readout means 74 and 77 is set to terminal b, and the selection switch 92 in the other selection readout means is connected to terminal d, the gate 104 of the selection circuit 99 of the selection readout means 75 is set to the terminal b. The full count output of the readout counter 91 of 74 passes through and is applied to the gate signal generation circuit 88, but since the selective readout means 75 is not selected, the output of the gate signal generation circuit 88 does not rise. The full count output of the counter 91 is the selective reading means 7.
5, 76 and is input to the selective reading means 77, and the output of the gate signal generating circuit 88 is the 10th
Since the frequency dividing ratio of the frequency dividing circuit 89 is set to 1/4 as shown in FIG. Then, as shown in FIG. 10D, the output signal of the gate signal generation circuit 88 becomes low level.

As mentioned above, the frequency dividing circuit 95 is selected to be the same as the frequency dividing ratio in the frequency dividing circuit 89, and the full count of the counter 98 is selected to be the same as that of the counter 91, so that the writing time to the buffer memory 79 is This is the same length as the gate signal when the selection switch 92 shown in FIG. 10B is set to the full width terminal a. Therefore, when the display width selection switches 92 of the selective reading means 74 and 77 are set to terminal b, the outputs shown in FIGS. 10C and 10D are generated from each gate signal generating circuit 88 of the selective reading means 74 and 77. , the corresponding data acquisition memory 3 during these periods.
All data of 4 and 46 are read out and written into buffer memory 79, respectively. buffer memory 7
As shown in FIG. 10E, the contents of the memory 34 are written as 105 in a half portion of the memory 9, and the contents of the memory 46 are written as the other half portion 106. Actually memory 34-36, 46, 4
Since each capacity of 7 and 79 is the same, depending on the compression ratio when writing to buffer memory 79, that is,
The data stored in the memories 34 to 36, 46, and 47 is skipped intermittently depending on the compression rate required to display the data sequentially on one display line, that is, the data is intermittently captured and stored. The data will be written to the buffer memory 79 as shown in FIG.

The information of one display line of the display 82 transferred to the buffer memory 79 in this way is stored in the main memory 8.
Moved to 1. The main memory 81 is the cathode ray tube display 8
For example, it is a shift register having a capacity for one screen of 2. The output of the oscillator 83 is the clock generator 1
11, the main memory 81 is shifted by the clock therefrom, and its output is supplied to the cathode ray tube display 82 and fed back to the main memory 81 through the gate 112 and further through the OR gate 113. In this example, one scanning line of the cathode ray tube display 82 is used as one display line, and when the data from the data acquisition section is transferred to the buffer memory 79, the counter 98 reaches the full count.
The output (FIG. 11A) is the gate signal generator 11
4, thereby obtaining the gate signal as shown in FIG. 11B. This signal opens gate 115 so that the output of buffer memory 79 can be supplied to main memory 81 through gates 115 and 113. The frequency divider circuit 116 and the counter 117 are activated by the gate signal from the gate signal generation circuit 114.
The output of the oscillator 83 is frequency-divided by the frequency dividing circuit 116 to obtain a clock signal having the same speed as the clock signal of the clock generator 111. This clock signal is applied as a read clock to buffer memory 79 through OR circuit 96. Therefore, the read clock from buffer memory 79 and the write clock of main memory 81 are synchronized.

When the counter 117 counts pixels for one scanning line, 256 in this example, the count becomes full and the gate signal generation circuit 114 is controlled, its output becomes low level, and the frequency dividing circuit 116 and counter 117 operate. stops. The output of the counter 98 is also supplied to the gate signal generation circuit 118, and this output becomes a high level as shown in FIG. signals are counted by this counter 119. counter 11
9 counts the number of scanning lines on one screen of the display 82 and reaches a full count, which causes the output of the gate signal generation circuit 118 to go to a low level, and the operation of the counter 119 is also stopped. Therefore, a high level output having a length of one screen as shown in FIG. 11C is obtained from the gate signal generating circuit 118. In addition to this, the 11th gate signal generation circuit 114
The output shown in FIG. 11B is ANDed by the inverter 121 and the output shown in FIG. This signal opens the gate 123 and the main memory 81
The output is passed through the delay circuit 124 for one scanning line,
Furthermore, it is fed back to the main memory 81 through the gate 123 and the gate 113.

When new information is input to the main memory 81 from the buffer memory 79 in this way, the newest information in the main memory 81 up to that point is delayed by one scanning line by the delay circuit 124 and then transferred to the main memory 81.
It will be returned to 1. The gate circuit 123 closes one pixel scanning period after the gate circuit 115 opens, that is, after the transfer of information from the buffer memory 79 to the main memory begins. Therefore, when the information in the buffer memory 79 is transferred to the main memory 81, the information on one of the oldest display lines is transferred to the delay circuit 124 and erased from the main memory 81. For the gate circuit 112, the output of the gate signal generation circuit 118 is connected to the inverter 12.
A signal shown in FIG. 11E, which is inverted at step 5, is applied, and only gate 112 is open while information is not being transferred from buffer memory 79 to main memory 81. Note that the clock generator 111 is supplied with a plane synchronization signal and a line synchronization signal, and the display 82
Generation of the clock signal is stopped during the electron beam retrace interval.

As mentioned above, the cathode ray tube display 82 is a color display, and the output of the main memory 81 is supplied to the color matrix circuit 177. The color matrix circuit 177 outputs a color signal according to the level of digital information input thereto, and has an amplitude (intensity) of 1 to control the electron gun that controls the red color of the display 82. Terminal R ₁ , terminal R ₂ with amplitude 2, terminal G 1 with amplitude 1 which controls the green color, terminal G ₂ with amplitude 2, terminal B ₁ with amplitude ₁ which also controls the blue color, terminal B 2 with amplitude ₂ Depending on the input digital information from the main memory 81, an output is generated at one or two of these six terminals. In order to further increase the variety of colors, even in the case of the same color, control is performed for bright and dark cases. That is, the least significant bit of the input digital information is supplied to the brightness control terminal of the display 82. Output 4-bit information of main memory 81 B ₄ , B ₃ ,
The relationship between B ₂ and B ₁ and the output terminal of the color matrix circuit 127 is as shown in FIG. Such a color matrix circuit 127 can be easily achieved by assembling a diode matrix circuit, for example, so that the digital input from the main memory produces the output shown in FIG.

When the least significant bit _B1 is 0, it is dark, and when it is 1, it is bright, modulating the brightness of the cathode ray tube. As a result, in this example, the reflected signal 100 has a strong level, such as from the ocean floor.
0 is displayed in red, and the no-reflection state 0000 is displayed in blue, indicating an intermediate level of reflection signal 0, such as from a school of fish.
110 is displayed in yellow, making it relatively conspicuous.

Next, we will discuss how to import data from the Net Monitor. Regarding the net monitor, as described with reference to FIG. 7, the detection of the upper and lower sides of the net monitor 41 is carried out in a time-division manner near the opening of the seine 39. For example, as shown in FIG. 13, the upper detection section Tu and the lower detection section Tl appear alternately, and the lower terminal section Tl is selected to be longer so that these sections can be distinguished. The information from this net monitor is given as negative pulses, such as synchronization pulses Psu and Ssl, which indicate the transmission trigger, whereas reflected signals 128 from schools of fish, etc., reflected signals 129 from the seabed, etc. are given as positive pulses.

This signal (the signal in FIG. 13) is transmitted by an ultrasonic carrier wave, is received by the receiver 43, and is sent to the receiver 42.
When received by the upper synchronization detection circuit 13 in FIG.
0, the upper synchronization pulse Psu is detected, and the lower synchronization detection circuit 131 detects the lower synchronization pulse Psl. Since the detection distance of the Netmonitor is relatively short, that is, the detection distance to the seabed on the Netmonitor side is shorter than the detection distance to the seafloor on the fish finder side, so each transmission trigger that corresponds to the detection period The period is short, and the period with the fish finder side is not taken, so the periodic pulse
If data is loaded into the buffer memory 79 based only on the time points obtained from Psu and Psl, a synchronous relationship will occur, such as the relationship between the information acquisition operation on the fish finder side and the acquisition operation of the buffer memory 79. Since there is no circuit system to take the data, while the contents of the buffer memory 79 are being transferred to the main memory 81, the data acquisition memories 46 and 47 are started to acquire data due to the synchronization pulses Psu and Psl, and new data cannot be read. There is a possibility that the data may not be completely captured from the start point to the end point, but may be rewritten in a half-finished state where it is partially captured. When the output of the counter 98 indicating that the data has been transferred to the buffer memory 79 is obtained, the synchronization pulses Psu and Psl immediately thereafter are detected and the subsequent data are respectively taken into the data acquisition memories 46 and 47. That is, in the upper data acquisition section 44, the synchronization detection circuit 132 detects the upper synchronization pulse immediately after the output pulse of the counter 98.
Psu is detected, and the output of the gate signal generation circuit 133 is set to a high level based on the output. The frequency divider circuit 134 and counter 135 are put into operation by the output. The frequency dividing circuit 134 has its frequency dividing ratio changed by the write width setting switch 136, divides the frequency of the signal from the oscillator 12, and supplies the divided signal to the counter 135.

The counter 135 is the number of pixels for one display line,
When 256 pieces are counted, the output of the gate signal generating circuit 133 is controlled to a low level, and the operation of the frequency dividing circuit 134 and the counter 135 is stopped.

The output of the frequency dividing circuit 134 is supplied to an up-down counter 137 for up-counting, and the output of an AD converter 48, which digitally converts the output of the receiver 42 to the net monitor using the contents of the up-down counter 137 as an address, is stored in a data acquisition memory. 46. This data acquisition memory 46 is a so-called random access memory.
When data is retrieved from this memory 46, that is, when the selective reading means 77 is selected, the output of the frequency dividing circuit 89 is sent to the up-down counter 135.
The output of the memory 46 is read out depending on the contents. In other words, the newest data among the data written in this manner is read out, that is, the order of the data is reversed. This is because the detection signal for the upper side of the net monitor is a reflected signal from something closer to the sea surface as the received information is slower than the oscillation trigger, so the display is made to match this.

Similarly, for the lower side detection data acquisition means 45 of the net monitor, the lower side synchronization pulse Psl immediately after the upper side synchronization pulse Psu when the information following the upper side synchronization pulse Psu is written into the memory 46 is detected by the synchronization detection circuit 138. The output of the gate signal generating circuit 139 is set to high level, and the frequency dividing circuit 141 and the counter 142 are activated. supply to. This frequency division ratio is changed by setting the switch 143, and the frequency division output drives the data acquisition memory 47 through the OR circuit 144, and the output of the AD converter 48 is written therein.

In this way, the detection information on the lower side is written into the memory 47, and when the counter 142 counts the number of pixels for one display line, it reaches a full count and controls the gate signal generation circuit 139, which operates with its output at a low level. stops. The data in this data acquisition memory 47 is read out by selective reading means 78.

Next, the various display states of the fish finder described above will be explained with reference to FIGS. 14 and 15, and its operation will be explained. In FIG. 14, the line scanning direction of the display 82 is the vertical direction, and the rightmost position 1
In this example, the newest information is displayed at the position 51, and the oldest information is displayed at the leftmost position 152. In contrast to the display on the far right of this display screen, the oldest display on the left is information from 30 minutes ago.
is set to 800 m, and only 74 is selected as the selection readout method, the seabed display is 153 and the fish school display is 1.
54, and an oscillation line 155 also appears. Depth scales 156 are displayed every 100 meters in the figure. Furthermore, at the bottom of the display screen, the time scale 15
7 is displayed as a dot every two minutes, for example.

To provide a depth scale 156, the output of frequency divider circuit 13 is applied to a depth scale generator 158 in FIG. The depth scale generator 158 is operated by the output of the gate signal generation circuit 50, and the output of the frequency divider circuit 13 is frequency-divided to divide the entire display width of the display 82, that is, one display line, into eight equal parts in this example. , generates a pulse corresponding to each division position, and each pulse is expressed as a numerical value indicating a predetermined level, for example, on the depth scale 1.
56 is expressed as a white level, it is taken into the data taking memory 34 through the OR circuit 57 as a digital signal of a level representing the white level. Therefore, the information of one display line is stored in the memory 34. For example, in the figure, the memory 34
The rightmost end corresponds to the top of the display screen of the display 82, that is, the shallowest position in the selected range, and the leftmost part of the memory 34 corresponds to reflection information at a deep position in the selected depth range. Information is stored. In this example, since 0 to 800m is displayed, 0m is displayed on the rightmost side of the memory 34, and 800m is displayed on the leftmost side of the memory 34.
m, and white information indicating the depth scale is stored at each position of the memory 34, which is divided into eight equal parts.

Since the time scale 157 is generated in synchronization with the operation of the display 82, the output of the oscillator 83 is frequency-divided by the time scale generator 159, and is a digital signal that is displayed in white every two minutes, for example. is applied to the buffer memory 79 through the OR circuit 94 so as to be at a position corresponding to the lowest position on the display line.

The display in FIG. 14 is a case in which detection information for a range of 0 to 800 m 19 minutes before the current time is displayed in parallel with an enlarged display of a portion of 400 to 500 m. The enlargement range of 400 to 500 m is selected by selecting the output of the decoder 58 with the enlargement value selection switch 59, and the enlargement width, that is, 100 m, is selected with the switch 64 of the partial enlargement capture section 32. In the selection reading means 74 and 75, the display width selection switch 92 is set to terminal b so that the selection reading means 74 and 75 are selected and their displays are displayed on the upper half and the lower half, respectively. .

In this case, information from 0 to 800 m is captured as one display line segment into the capture memory 34, as in the previous case, and information about 400 to 800 meters is captured into the memory 35.
The 500m section is captured as one display line segment.

The contents of the memory 34 are compressed by the selective reading means 74, and the first half of the buffer memory 79 is
The data is written to the right half in the figure, and the contents of the memory 35 are compressed and taken into the second half.

Therefore, as shown in FIG. 14, the seabed is displayed as 161 and the school of fish is displayed as 162, and their enlarged views are further enlarged and displayed as the seabed 163 and the school of fish 164. The depth scale 156 is compressed and displayed as a depth scale 160.

Further, a gate signal generation circuit 6 indicating this enlarged position
1 is supplied to an enlarged mark generator 169;
At positions corresponding to the rising and falling edges of the gate signal of the gate signal generation circuit 61, a digital signal corresponding to the display color (for example, white) is output to the OR circuit 57.
The data is captured into the data capture memory 34 through.
This allows the enlarged position display line 165 to indicate the enlarged position.
is displayed, indicating that this part is enlarged below. Further, the enlarged depth mark generator 166 is operated by the output of the gate signal generation circuit 61.
The enlarged depth mark generator 166 divides the output of the frequency divider 13 and generates a depth mark for the enlarged display area, and the output is used as a digital signal indicating the level corresponding to the display color to display the enlarged part through the OR circuit 67. The data is written into the data acquisition memory 35 of the data acquisition section 32. As a result, an enlarged depth mark 167 is displayed on the display.

Further, in order to provide a boundary line 168 indicating the boundary between the normal display in the upper half and the enlarged display in the lower half, the output of the read counter 91 of the selective read means 74 passes through the OR circuit 169, and further passes through the OR circuit 94 to the buffer memory 79. written to. Similarly, when the selective reading means 74 to 77 etc. are selected, the output of the reading counter 91 of the selective reading means is supplied to the OR circuit 169, and the signal indicating the boundary of the display is used as a boundary line signal. The data is written to the buffer memory 79.

Furthermore, in this example, 11 minutes before the current time, the normal display remains as it is, and the magnification switch 64 is selected to further increase the magnification rate. This is a case where enlarged display is selected.

As a display example, as shown in Figure 15, 20
Minutes ago, the normal display from 0 to 600 m was selected by the selection switch 14, and after that, the portion from 500 to 600 m was selected by the enlarged position selection switch 59,
This is the case where the selective reading means 74 and 75 are selected and displayed, and the seabed display 161 and the fish school display 16
2 are respectively displayed as a seabed display 163 and a fish school display 164 in the enlarged display. When the selection readout means 74, the selection readout means 76 for seafloor expansion, and the selection readout means 77 and 78 for net monitor information are selected and their respective display width selection switches 92 are set to terminal c, the above-mentioned operation will result in the following operations. buffer memory 79
The information in each of the memory 34 and memories 36, 46, and 47 is compressed to 1/4 and written. Therefore, the normal display is performed in the upper 1/4 part of the display screen, the seabed display 171 and the fish school display 172 are displayed, and the display from the seafloor enlarged data acquisition part is displayed in the next 1/4 part. Display line 173 indicating the seabed
is displayed as a straight line, and a school of fish display 172 is displayed above it.
A display 174 corresponding to the above appears. Furthermore, in the upper half of the lower half of the display screen, an upper display of the net monitor appears, a display 175 indicating the position of the net monitor and a school of fish 176 are displayed above it, and further below, information on the lower side of the net monitor is displayed. Accordingly, a seabed display 177 and a school of fish display 178 are displayed.

In the above configuration, display can be performed in various display modes by selecting the selective readout means 74 to 77 as described above, but in that case, the selection circuit 99 of the selective readout means may be provided in cascade. For example, in the embodiments shown in FIGS. 3 to 5, even if all the selection reading means are in the selected state, Depending on the setting state of the first selection readout means 74, it is determined whether or not the subsequent selection readout means can read and display.In other words, if the switch 92 is set to the full width display terminal a, the other selection readout means This information is not displayed regardless of whether it is selected or not. In addition, when the selection readout means 74 is set to the half width terminal b, information of any one of them or a combination thereof is selected depending on the selection state of the selection readout means 75 to 78. Is displayed. The determination of this priority order is not limited to the above example, and can be arbitrarily selected. Further, the amount of data to be displayed can be increased or decreased.

By the way, as shown in Fig. 7, the transducer 23 of the fish finder and the net monitor 41 are separated by a distance _L1 , but if the display is performed using the configuration shown in Figs. They will be displayed in the same position above. It is possible to easily display the image on the display screen by shifting it by a distance corresponding to _L1 . For example, as shown in FIG. 16, only the main parts thereof are shown, the upper data acquisition memory 46 and lower data acquisition memory 47 of the net monitor are connected to the third
The signal is supplied to the buffer memory 182 through an OR circuit 181 that is different from the OR circuit 44 in FIGS. Writing to this memory 182 is performed by the frequency dividing circuit 9 in the same way as for the buffer memory 79 in FIG.
A write pulse of 5 is performed by driving memory 182 through OR circuit 183. As understood from the above description, the selective reading means 74-
Information in the memories 46 to 47 is transferred to the buffer memory 182 depending on the selection state of the memory 78. On the other hand, in FIG. 5, a pulse (FIG. 11A) indicating completion of writing to buffer memory 79 is obtained from counter 98, and this pulse is also supplied to variable delay circuit 184 and delayed by time _D1 . This time D ₁ is the period between the net monitor 41 and the transducer 23 in FIG.
The distance L ₁ between the two is selected as the time required for the fishing boat 37 to sail, and the delay amount D ₁ can be changed by changing the sailing speed of the fishing boat 37 or the length of the rope 38. The delay circuit 184 is configured. The line synchronization pulse (FIG. 11G) immediately after the delayed pulse shown in FIG. 11F is selected by the synchronization selection circuit 185 as shown in FIG. 11H. The gate signal generating circuit 186 is driven by the pulse to generate a gate signal having a width of one line scanning period as shown in FIG. 11I, and this gate signal is supplied to the gate circuit 187. The gate circuit 187 is supplied with a signal indicating that the net monitor information is being selected from the output of the buffer memory 182, the output of the gate signal generation circuit 186, and a terminal 188. A signal indicating this selection can be easily obtained from the set position of each switch 92 of the selection reading means 77, 78 in FIG. On the other hand, a pulse from clock generation circuit 111 is applied as a read pulse to buffer memory 182 through OR circuit 183, and the information in memory 182 is cyclically held. When the gate circuit 187 is opened by the gate signal shown in FIG.
The output of
The data is transferred to the main memory 81 through. In this case, the buffer memory 182 includes selective reading means 74 to 7.
As can be understood from the previous explanation of 8, there is no signal in the first half of the readout, and only the information from the net monitor is stored in the second half. In this way, the information from the net monitor is sent to the main memory 81 with a delay of time D ₁ relative to the information from the buffer memory 79.
is transmitted to the transducer 2 on the display screen.
The information from 5 and the information from the net monitor 41 are displayed shifted by an amount corresponding to the distance _L1 ,
It becomes easy to analyze the relationship between these two pieces of information.

In FIGS. 3 to 5, shift register units F ₁ to F _o are connected in series as _the main memory 81, and data is circulated within the series connection _. It can also be circulated. Figure 17 shows an example, and Figures 3 to 5
The same reference numerals are given to the parts corresponding to those in the figure, and the line synchronization signal from the line synchronization signal generator 85 is supplied to the counter 191, and the counter 191 is fully counted by the number of line scanning lines on the display surface. The count contents are decoded by a decoder 192, and gate pulses having a width of a line scanning period are sequentially applied to gates Ga ₁ to _{Ga o} as decoded outputs for each line scanning period. These gates Ga ₁ to Ga _o are given pulses from the clock generator 111, and the pulses passed through these gates are OR gates.
The driving pulses are applied to the shift register units F ₁ to _{F o} through Gb ₁ to Gb _o , respectively. Each output of each shift register section F ₁ -F _o is fed back to its own initial stage through gates Gc ₁ -Gc _o and Gd ₁ -Gd _o , respectively, and is also supplied to the color matrix circuit 177 as an output of the main memory 81. . Therefore, during the first line scan of surface scanning, the gate Ga ₁ is opened, and the contents of the shift register section F ₁ are outputted from the main memory 81 and fed back to the shift register section F ₁ .
During the second line scan, the gate Ga ₂ is opened, and the contents of the shift register section F ₂ are outputted from the main memory 81 and returned to the register section F ₂ . Thereafter, when the gate Ga _o is opened in the same manner and the shift register section F _o is read out, one-plane scanning is completed and the gates are opened again sequentially starting from the gate Ga ₁ . When writing to the main memory 81, the gates Ge ₁ to Ge _o are opened by the output of the gate signal generation circuit 114, and the gate Ge ₂
The shift register units F ₁ -F _o are connected in series through ~Ge _o and Gd ₂ ~Gd _o , respectively. At this time, the output of the gate signal generation circuit 114 is inverted by the inverter 193 and supplied to the gates Gc ₁ to _Gco , and these gates are closed. Further, the output of the gate signal generation circuit 114 is given to the gate 194, and through this gate the clock from the clock generator 111 is sent to the buffer memory 79 and the gate _Gb1.
~ Gb _o respectively given, shift register section F ₁
~F _o is also driven. Therefore, buffer memory 79
The contents of the shift register section _F1 are transferred to the shift register section F1, the contents of the shift register section _F1 are transferred to the shift register section _F2 , and the contents are sequentially transferred to the next shift register section.

In the above description, one display line is displayed as one line scanning line on the display 82, but it can also be displayed at right angles to the line scanning line. FIG. 18 is a block diagram for this purpose, and only important parts are shown with the same reference numerals assigned to parts corresponding to those in FIGS. 3 to 5. A write end pulse (FIG. 19A) for the buffer memory 79 is given to the synchronization selection circuit 195, and the circuit 19
In step 5, the immediately subsequent surface synchronous signal is selected from the surface synchronous signal generating circuit 86, and a signal that continues during the whole surface scanning synchronization Tv is obtained as shown in FIG. 19B. This signal is applied to a pulse generation circuit 196, and this circuit 196 is provided with a clock from the clock generator 111 and a line synchronization signal (FIG. 19C) from the line synchronization signal generator 85. During the signal period, immediately after the line synchronization signal, the clock
The selection is made as shown in Figure 9D. The buffer memory 79 is driven by this clock, and its readout output is provided by the clock from the circuit 196 and the gate circuit 1.
A match is found in step 97 and written to the first stage m ₁₁ of the shift register section F ₁ of the main memory 81 through the OR circuit 198 . The inverted clock signal from circuit 196 and the gate signal from circuit 195 are ANDed in circuit 199 to produce the gate signal shown in FIG. 19E, which opens gate circuit 201. The output of the main memory 81 is the delay circuit 202
After being delayed by one line scanning period, the gate circuit 20
1, and is further returned to the first stage of the shift register section _F1 through the OR circuit 198. Therefore, the signal written by the first clock P ₁ (FIG. 19D) becomes the second clock when the contents of the buffer memory 79 are written to the first stage _m11 of the main memory by the second clock P ₂ . It is moved to the first stage _m21 of the shift register section _F2 . In this way, when the contents of the buffer memory 79 are written into the main memory 81 by the last clock P _o , the contents written by P ₁ are transferred to the first stage _mo1 of the last shift register PF ₁ . When this writing is completed, the gate circuit 197,
201 is closed, and the gate circuit 204 is opened by a signal obtained by inverting the gate signal from the circuit 195 at the inverter 203, and the output of the main memory 81 passes through the gate circuit 204 without passing through the delay circuit 202. First stage through OR circuit 198
Returned to m ₁₁ . In this cyclic hold state, the storage stages m ₁₁ , m ₂₁ , . . . of the main memory 81 are initialized.
The contents e ₁₁ , e ₂₂ , ... e _o1 located at m _o1 are displayed at one end of each of the line scanning lines l ₁ , l ₂ ... _lo on the display surface of the display 82, as shown in FIG. . Next, when writing to the main memory 81 is performed in the same manner, in the initial state, each register section F ₁
~ The contents of the first stage of F _o are the second stage m ₁₂ , m ₂₂ ……
They each move to m _o2 , and on the display screen, they each move by one pixel to the left in FIG. 20 on the line scanning line. In this way, a display with display lines perpendicular to the line scanning lines can be obtained.

As described above, by displaying the received reflected signal in different colors according to its level on the display, even small level differences can be determined, but unnecessary component colors can be selectively removed by looking at the display on the display 82. By doing so, it is also possible to analyze the displayed image more accurately. To do this, for example, as shown in FIG.
A color selection circuit 105 is inserted between the main memory 81 and the color matrix circuit 177, and the output of the main memory 81, for example, a 4-bit binary digital signal, is sent to a decoder 206.
It is decoded so that an output is obtained at one of the output terminals t ₁ to t ₁₆ according to its size. Terminals t ₁ to _{t 16} are connected to gate circuits Gf ₁ to Gf ₁₆ in the color selection circuit 205.
are supplied with the output of each gate circuit.
The other input of Gf ₁ to Gf ₁₆ is the switch S ₁ to
Grounded through S ₁₆ . The respective outputs of the gate circuits Gf ₁ to _{Gf 16} are supplied to the encoder 207 , where they are again converted into 4-bit binary digital signals and supplied to the color matrix circuit 177 . For example, in the initial state, all switches S ₁ to _{S 16} are turned off and all gate circuits Gf ₁ to Gf ₁₆ are allowed to pass, which is the same state as when the output of the main memory 81 is directly supplied to the color matrix circuit 177. Observe the display on the display 82 _as
By selectively turning off one or more of S ₁₆ to remove levels corresponding to plankton in the received signal, it is possible to clearly display fish schools in plankton. Furthermore, if one becomes accustomed to such operations, it is possible to turn on the switches S ₁ to _{S 16} for unnecessary level components in the reflected received signal from the beginning, so that a display that makes it easy to make a correct judgment can be immediately obtained.

In order to prevent both ends of the display surface of the display device 82 from being hidden by masks and becoming invisible, for example, when the switch 92 in each selection readout means is set to the full width position a in FIGS. 3 to 5, the frequency dividing circuit 89 is The output pulses can be set at a slightly higher speed than the output pulses of the frequency dividing circuit 95 so that, for example, when all of the data in the data acquisition memory 34 is written into the buffer memory 79, the buffer memory 79 is only about 90% full.

Alternatively, to prevent the display from being hidden in the vertical and horizontal directions, it is also possible to slightly lengthen the period during which the clock in the clock generator 111 is stopped.

When displaying on a color display at a remote location, the reception signal and transmission trigger signal from the transmitting/receiving section 11 are transmitted as radio waves, which are received at the remote location, and these signals are used in the same manner as explained in Fig. 1 and elsewhere. You may also display it as Further, for example, in FIG. 1, various synchronization signals from the control circuit 7 and the color converter 17
It is also possible to transmit each color signal from 7 by radio wave and display it on a color display at a remote location. in this case,
If it is transmitted as a signal using the same method as color television broadcasting in that country, for example, each color signal of the color converter 177 is made to correspond to each output of a three-primary color camera, and from this signal and the synchronization signal of the control circuit 7, a luminance signal and a By creating a color difference signal and further creating a color subcarrier and transmitting it as a so-called NTSC signal, a receiver that receives color television broadcasting can be used as the reception display 82.

[Effect of idea]

According to this invention, as described above, the storage contents of the data acquisition memory of the fishing net side detection information and the fish school detection information are intermittently selected and imported into the buffer memory for one display line to perform the required display compression. After obtaining the data, the display scale for the merged display is performed by importing it into the main memory for the display screen, so there is no need for complicated calculation means, stable operation is obtained, and the configuration is simple and inexpensive. It has features such as being able to

[Brief explanation of the drawing]

The drawings show an embodiment, and FIG. 1 is a block diagram showing the schematic configuration of the device, FIGS. 2A to 2E are operational waveform diagrams of the main parts of FIG. 1, and FIGS. 3 to 5 are diagrams of the device. FIG. 6 is a waveform diagram for explaining the operation of the embodiment shown in FIGS. 3 to 5. FIG. 7 is a diagram showing the relationship between the fishing boat and the net monitor. 8 is a circuit diagram showing a specific example of the synchronous selection circuit 87, FIG. 9 is a diagram showing an example of the selection circuit 99, and FIG. 10 is a waveform diagram for explaining the operation of the selective reading means. , FIG. 11 is a waveform diagram for explaining the operation of the gate control circuit for the main memory, FIG. 12 is a diagram showing an example of conversion in the color matrix circuit, and FIG. 13 is a waveform diagram showing an example of the received signal of the net monitor. , Figures 14 and 15
The figures show an example of the display of the fish finder according to this invention, Fig. 16 is a block diagram showing the main parts for displaying the signal from the net monitor by shifting its position, and Fig. 17 shows the main memory. A diagram showing another example and its gate control circuit, FIG. 18 is a diagram showing an example of the main memory and its gate control circuit when the display line is perpendicular to the line scanning line, and FIG. 19 is an explanation of its operation. Waveform diagram for use in, No. 20
The figure shows a display process by the main memory of FIG. 18, and FIG. 21 shows an example of a color selection circuit.

Claims (1)

[Scope of Claim for Utility Model Registration] A fish detection signal obtained with a detection cycle (hereinafter referred to as a fish detection cycle) and a detection cycle that is short and unrelated to the fish detection cycle (hereinafter referred to as a fishing net detection cycle) Information from each digital signal obtained by AD converting the fishing net side detection signal obtained with a period (referred to as a period) is displayed in tandem on one display line in the depth direction, and the display line is sequentially A detection and display device having a display screen which is scanned so that the display is lined up and removed from the oldest one, and the display screen is also switched so that only information from the fish detection signal is displayed over the entire width of the display line. In a fish detection/fishing net detection display device capable of displaying the information, the information within one fish detection period of the fish detection signal is based on the time point obtained based on the oscillation signal for obtaining the fish detection signal. a fish detection information acquisition memory that stores the amount of memory required to capture and display the fish school detection information in the full width; b) a fish school detection information acquisition memory that stores the information within one fishing net detection cycle of the fishing net side detection signal; Memory necessary for displaying the contents of the display screen memory at the full width by importing the contents based on the synchronization signal in the fishing net side detection signal immediately after importing the stored contents of the display screen memory to be described later. a memory for capturing fishing net detection information that stores the amount; a 1-display line information capture memory that captures the memory content and stores the amount of memory necessary to display the one display line; d) only the memory content of the fish detection information capture memory is stored as described above; Fish detection display line storage means for capturing and storing the stored contents of the fish detection information capture memory as is in the one display line information capture memory in order to capture the data into the one display line information capture memory; e In order to display the storage contents of the fish detection information acquisition memory and the storage contents of the fishing net detection information acquisition memory in tandem on the one display line, the fish detection information acquisition memory After intermittently importing the memory contents of the fishing net detection information acquisition memory according to the necessary compression rate, the one display line information is acquired by intermittently acquiring the memory contents of the fishing net detection information acquisition memory according to the necessary compression rate. a fish school/fishing net detection display line storage means stored in the built-in memory; and f) either a circuit for operating the fish school detection/fishing net detection display line storage means or a circuit for operating the fish school/fishing net detection display line storage means; a selection switch for selecting either one of the circuits; What is claimed is: 1. A fish school and fishing net detection display device, characterized in that it is equipped with a display screen memory whose contents are erased first.