JPS6255632B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention displays detection information signals such as fish detection signals on a display screen of a cathode ray tube display device formed by horizontal main scanning and vertical sub-scanning. This relates to a cathode ray tube display detector.

[Conventional technology]

For example, in a fish finder, information from one detection is displayed as a vertical line on one end of the display screen of a cathode ray tube display, and older information is displayed as a vertical line on the other end of the display screen. Recording is performed in a format similar to display using recording paper, by displaying information and sequentially erasing the oldest information so that new information is always displayed at one end of the display surface.

By using a cathode ray tube, this display method can display more information than recording paper, and in particular uses a color cathode ray tube to display different colors depending on the level of the detection signal. When used and displayed, a large amount of information is displayed. By making the displayed colors stand out even when there is a difference in level, it becomes possible to distinguish them, and the readability can be significantly increased.

With such a cathode ray tube display device, it is easy to enlarge and display a portion of the image, which is extremely convenient.

In order to provide such a cathode ray tube display detector with a horizontally long display surface, it is more convenient and inexpensive to configure it using the cathode ray tube display device part of a general commercially available television, and it is of stable quality. This has the advantage that the distance from the reference position of the display surface corresponds to the detection distance, so that signals corresponding to within one detection period of the detection period in the display signal are displayed above and below the display surface. In order to display the direction in a single line, the direction in which the detection information is stored in the memory and the readout direction in which the stored contents are read out and given as a display signal to the display screen must be different from each other in orthogonal directions. Therefore, some kind of configuration is required.

As a method for this purpose, a method using a shift register as in Japanese Patent Laid-Open No. 52-141262 has been disclosed.

[Problem that the invention seeks to solve]

However, the loading/reading means as disclosed in Japanese Patent Laid-Open No. 52-141262 has a complicated configuration, and if a memory point in the memory element 1 becomes defective, the entire loading/reading itself stops.
There is a problem in that it is desired to provide a simple structure that uses (random access memory) as a storage element and stabilizes its operation.

In addition, as mentioned above, when the cathode ray tube detection display is used as an ultrasonic detection device, the ultrasonic detection information may contain noise from the ship's navigation, noise from minute objects in the water such as plankton, etc. This includes noise generated depending on the conditions on the water surface and the conditions on the underwater side, and the degree of this noise varies depending on changes in the sea area, etc., so it is necessary to make adjustments for noise removal while observing the display status. There is,
One effective means for removing this noise is a method based on signal correlation processing, and correlation processing means conventionally used for processing radar detection information is generally used.

However, in the case of radar, the speed of radio waves is fast, so it takes only one screen to display the detection information for one screen.
Since it only takes ~2 seconds, the adjustment for noise removal can be completed in several times that time, and the detection information that is overlooked during that time is not a big problem in terms of the application, but The speed is much slower than the speed of radio waves, and even if the detection depth is 750 m and the number of display scans is 256, it takes 256 seconds, or more than 4 minutes, to obtain the detection display for one display screen. Detection information over a period of time is not processed by noise or is displayed in an insufficiently processed state, which often results in important detected objects being missed during this period.This has been improved. There is a problem in that the emergence of ultrasonic detection and display devices is expected.

[Means for solving problems]

This invention converts the count of the counter that takes in information within one detection cycle among the address counters that designate the position at which the storage is taken into the RAM into a signal corresponding to the vertical sub-scanning of the display surface. When the counter has counted the scheduled number, a carry signal is output, and a counter corresponding to the number of detection cycles counts based on the carry signal, thereby capturing the detection information signal. After counting the carry signal, the counter that takes in the information within one detection cycle starts counting, and the counter that takes in the information within one detection cycle starts counting, and the counter that takes in the information corresponding to the horizontal main scanning starts counting the signal corresponding to the number of detection cycles. The above-mentioned problem can be solved by providing a reading means for reading for display by counting with a counter.

In addition, in the above-mentioned correlation processing means, in the prior art, after the detection information is once correlated, the processed detection information is stored for a display screen, and the stored contents are read out to obtain a display signal. In this invention, the raw signal before correlation processing is changed to be stored, and the stored content is also changed to store information obtained by converting the detection information signal into a plurality of digital values, and this stored content is read out. By providing a correlation means for correlating adjacent read signals in the read signals using digital values of multiple digits, correlation can be performed at any time regardless of the acquisition of detection information. The above-mentioned problems can be solved by allowing the processing method to be changed as desired.

〔Example〕

Next, an embodiment of the cathode ray tube display and detection device according to the present invention will be described with reference to the drawings. This example is applied to a fish finder, in which a carrier wave pulse of an ultrasonic frequency is emitted from a transmitter 11 into the sea via a transducer 12, and is emitted from a seabed 13 or a school of fish 14 on the way. The reflected wave is received by the transducer 12. The received signal is converted into an electrical signal and amplified and detected by the receiver 15.

The transmission trigger that drives the transmitter 11 is transmitted at a cycle of _T1 and radiated into the water as shown in FIG. reflected wave 18
is received as shown in FIG. 2B.

This detection information is transmitted to the receiver 1 for each ultrasonic pulse.
5, which is converted by the AD converter 19 into, for example, a 4-bit digital signal, that is, a signal of a plurality of digit digital values, according to its level, and the buffer memory 21 stores, for example, 256 sampling points. . That is, the output of the receiver 15 is sampled from the beginning of the trigger pulse to the buffer memory 21, and as shown in FIG. 2, the period _T2 , which is shorter than the period _T1 , is taken in as 256 samplings, for example. Digital information in buffer memory 21 is transferred to main memory section 22 and stored therein. The main memory section 22 has a storage capacity for displaying one screen of the cathode ray tube display device 23, and is read out periodically and displayed on the cathode ray tube display device 23. The display is performed, for example, on the display screen 24 as shown in FIG.
5 is scanned from the left end to the right end, that is, horizontal main scanning, and sub-scanned from top to bottom, that is, vertical sub-scanning, and one detection information is displayed in the upper and lower direction of the right end. be done. Therefore, since the number of sampling points for one detection information time _T2 is 256 in this example, the number of display lines 25 is also 256.

The newest detection information is displayed on the right edge of the display screen 24, the oldest information is displayed on the left edge,
As the display gets older, it moves to the left side and shows on the display screen 24 a transmission line 26 showing a transmission pulse 16 which is a leakage of a transmission pulse, a display 27 showing a reflected wave 17 from a school of fish, and a display showing a reflected wave 18 from the seabed. 28 are displayed respectively.

In this example, a color cathode ray tube is used as the cathode ray tube 23, and the signals are displayed in different colors depending on the input signal level.For example, the zero level, in this case, reflected waves from underwater are displayed in blue, and the largest level, for example, the ocean floor, etc. The reflected waves can be displayed in red. The trigger pulse period T ₁ is changed depending on the detection distance range, so-called range. For example, the output of a reference oscillator 29 such as a crystal oscillator is frequency-divided by a frequency divider 31, and this frequency-divided output is supplied to a variable frequency divider circuit 33. Variable frequency divider circuit 3
One of the three different frequency division ratio outputs is selected by the range selector switch 34, and the frequency divider 35
The frequency is divided by

The output of the frequency divider 35 is given to the transmitter 11 as a trigger pulse, and is also given to the buffer memory 21 as a data acquisition start signal. The range selector switch 34 has, for example, eight ranges from 0 to 20 m,
0-40m, 0-80m, 0-160m, 0-320m, 0
The detection range is switched to ~640m, 0~1280m, and 0~2560m, and as this range is increased, the period _T1 of the transmission pulse is lengthened. Since the number of samplings for one detection information is constant (256 in this example), as the range is lengthened, the clock frequency for loading data into the buffer memory 21 is also lowered. Therefore, frequency divider 3
The output of 1 is also given to a frequency divider 37, and as the output of this frequency divider 37, eight different frequency division ratio outputs are obtained. Information is given from the command circuit 39 to the selection circuit 38 according to each set value of the detection range, and the selection circuit 38 selects one signal from the eight outputs of the frequency dividing circuit 37, and this selects the data into the buffer memory 21. Provided as a clock for reading.

In order to control the cathode ray tube display 23, the output of the reference clock oscillator 29 is frequency-divided by a frequency divider circuit 41 and a frequency divider circuit 42 to produce a horizontal synchronization signal, and this horizontal synchronization signal is then applied to a frequency divider circuit 44. The vertical synchronization signal is created by dividing the frequency by .

These horizontal synchronizing signals and vertical synchronizing signals are applied to the cathode ray tube display 23 to control the electron beam of the display 23, so that the display screen is main-scanned and sub-scanned by the electron beam.

Furthermore, the output obtained by dividing the output of the reference oscillator by the frequency dividing circuit 41 is supplied to the transfer control circuit 43 in order to transfer the stored information of the buffer memory 21 to the main memory section 22, and the output is stopped after the period _T2 in FIG. The information in the buffer memory 21 is controlled to be written into the main memory section 22 during the retrace period of the vertical synchronization signal.

The output of the frequency dividing circuit 41 is also directly supplied to the main memory section 22 as a reading clock, and the information in the main memory section 22 is sequentially read out, passed through a signal processing circuit 48, a code conversion circuit 45, and then further to a decoder 47. The signal is converted into an analog signal and supplied to the cathode ray tube display device 23.

As a result, the display shown in FIG. 3 is always obtained as a still image, and when the detection information is obtained in the buffer memory 21, the information in the buffer memory 21 is transferred to the main memory during the retrace period of the next vertical synchronization signal. 22. As a result, as described above, the display contents of the display screen 24 are moved from the right end to the left end. The number of detection information lines displayed in vertical lines on the display screen 24 is determined by the capacity of the main memory section 22, but in this example,
256. That is, the number of pixels displayed on the display screen 24 is 256 in both the vertical and horizontal directions, so the number is 65,536.

In this invention, as shown in FIG. 3, the display line 25 of the cathode ray tube display device 23 is displayed in the horizontal direction, whereas the one detection information line is displayed in the vertical direction. If the part indicated by is shown in more detail, it is constructed as surrounded by a dotted line 22 in FIG.

A signal is applied to the terminal 22e in order to transfer and write information from the buffer memory 21 to the main memory section 22. In this example, a RAM (random access memory) 75 is used as a storage element, and address counters 73 and 74 are provided corresponding to addresses A ₀ to _{A 15} to specify storage addresses. When writing the information in the buffer memory 21 to the RAM 75, the vertical synchronizer 6 is connected to the terminal 22b as shown in FIG. 6A.
3, that is, a signal corresponding to vertical sub-scanning, is added to the AND gates 67 and 70.
is opened and AND gates 68 and 71 are closed.

At this time, 256 clock pulses shown in FIG. 6B from the transfer control circuit 43 are applied to the address counter 73 through the terminal 22c, the AND gate 67, and the OR gate 69 for counting. When the address counter 73 counts 256 pulses, one carry pulse is output from the counter 73. In other words, when the counter 73 counts the scheduled number, a carry signal is output, which is sent to the address counter 74 through the AND gate 70 and the OR gate 72. considered to be counted.

While the address counter is operating in this manner, information from the buffer memory 21 is applied to the input terminal DIN of the RAM 75 through the terminal 22e, and the negative output of the inverter 66 is applied to the read/write terminal of the RAM 75.
Since it is applied to the write control terminal R/W, a write operation is performed.

Next, during a read operation, the terminal 22b becomes low level, AND gates 67 and 70 are closed, and AND gates 68 and 71 are opened. On the other hand, inverter 6
The positive output of 6 is applied to the read/write control terminal R/W of the RAM 75 to switch to read control.

The read address clock is gated from the terminal 22d with the horizontal (main scanning) synchronizing signal 60 by the AND gate 76. The signal shown enlarged in FIG. 6E is as follows.
Since the address is added to the address counter 74 through the AND gate 71 and the OR gate 72, the address
The dependent order of A ₈ to _{A 15} and addresses A ₀ to _{A 7} is reversed from that at the time of writing. Then, instead of the carry pulse of the address counter 74, a main scanning synchronization signal is applied to the address counter 73 from the terminal 22a through the AND gate 68 and the OR gate 69. That is, since the outputs A ₈ to _{A 15} of the address counter 74 take the value of a certain address at the beginning of reading, a carry pulse is generated in the middle while the address counter 74 counts 256 (during one main scan). is output, but regardless of this, the address counter 73 is counted by 1 with a signal corresponding to the end point (or start point) of the main scan, that is, the horizontal main scan, and the address counter 73 is
When it counts 256, scanning for one screen is completed.

Writing, reading and address A ₀ ~
The relationship of _A15 is shown in Figure 7. buffer memory 2
The first 256-bit information of 1 is transferred to RAM 75.
For multiple writes, change addresses A ₀ to A ₇ and start from address 0.
It is written to address 255, and then becomes address 256, where it is in a standby state for reading. Next, during the first scanning line of reading, A ₀ to A ₇ are all 0, and the addresses of A ₈ to _{A 15} change.
Addresses A ₀ to A ₇ are added one by one in correspondence to the second scanning line and the third scanning line.

Further, the second write is performed from address 256 to address 511, and the next read is performed from address 512. By doing this, the shallowest information of the first detection information is written at address 0 and displayed at the 256th position of the first scanning line, that is, at the upper right corner of the display screen 24,
The information at the next shallowest address 1 is displayed at the 256th position on the second scanning line. Also, the second written information, i.e.
The information at address 256 is displayed at the 256th position on the next first scanning line, at the upper right corner, in the same way as the first write information. The first writing information at address 0 is displayed at the 255th position on the next main scanning line.

In this way, the address counters 73 and 74 are simply up counters, and by simply changing the input/output connections through write and read control, the oldest information on the display screen 24 can be rewritten to the latest information. Display information can be sent to the left on the display screen 24, and the latest information can be displayed on the right end.

As can be seen from the above explanation, the address counter 73 corresponds to a counter that counts to capture digital signals of detection information within one detection cycle, so this is called a 1 detection compatible counter. Since 74 corresponds to a counter for counting the number of detection cycles of detection information, this can be called a counter corresponding to the number of detections.

The differentiating circuit 77 differentiates the vertical (sub-scanning) synchronizing signal and resets the address counter 73. Under normal operation, the reset circuit is not required, but if for some reason the address counter 73 is reset.
This is provided to prevent this from occurring if the relative positions in the depth direction on the display screen 24 are miscounted. The signal processing circuit 48 includes a 2-bit shift register 79 and a 2-bit shift register 79 as shown in FIG.
It is composed of a ROM 78, and a shift pulse is applied from a terminal 48a. The information read from the ROM 75 passes through a shift register 79, and the D ₁ output of the shift register 79 and the D ₂ output delayed by 1 bit are provided to the ROM 78. The ROM 78 is a code converter and converts two pieces of information D ₁ and D ₂ into other information.

As an example, shown in FIG. 8, a value from 0 to 7 is output for each value from 0 to 15 for _D1 and _D2 . This value is approximately 1/2 of the average value, but D ₁ , D ₂
If any one of them is 0 or 1, they are all 0, and there is an interference removal effect. In other words, in a fish finder, the normal reflected reception signal does not have an extreme difference between one detection information and the next detection information, so it is unlikely that the previous detection information will be received with no signal and the current one will be received at a strong level. . On the other hand, interference noise caused by the direct reception of signals transmitted by other fish finders is generally strong, so if either D ₁ or D ₂ has no signal, forcing it to have no signal will effectively eliminate interference. be. 8th
In the example shown in the figure, the RAM 75 is stored at levels 0 to 15, and the display is displayed at half the level 0 to 7, which seems wasteful, but the characteristic changeover switch 49 By changing _the address _of
In this way, effective display characteristics can be obtained depending on the purpose. Although the shift register 79 may have a 1-bit register, a 2-bit register is used to also serve as waveform shaping.

This cathode ray tube display detector further includes a distance scale on the display screen 24, as shown in FIG. The counter 80 in FIG. 1 is reset by the vertical period signal 63 and counts the horizontal synchronizing signal 60 which is the output of the frequency dividing circuit 42, as shown in FIG. 9C. The counter 80 in this example is composed of six stages, and its outputs are _Q1 to _Q6 .

The decoder 92 receives the outputs Q ₁ to _{Q 4} of the counter 80.
are connected to the decoder 91, and the outputs _Q1 to _Q6 of the counter 80 are connected to the decoder 91, and the outputs of both decoders appear when all inputs become 0. Therefore, the output of the decoder 91 is output during the reset period of the counter 80 and for one cycle of the horizontal synchronizing signal every time the counter 80 counts 64 horizontal synchronizing signals, as shown in FIG. 9E.

Similarly, the output of the decoder 92 is determined by the reset period of the counter 80 and the reset period of the counter 80 as shown in FIG. 9D.
is output for one cycle of the horizontal synchronizing signal every time the horizontal synchronizing signal is counted 16 times. The output of decoder 91 is led to code conversion circuit 45 via OR gate 94 and AND gate 89. On the other hand, decoder 9
The output of 2 is controlled by an AND gate 93 and then similarly led to an OR gate 94.

A horizontal synchronizing signal 60 shown in FIG. 10F is applied to the one-shot multivibrator 83, and the one-shot multivibrator 83 operates for a period _T3 as shown in FIG. 10G. This operating period T ₃ is designed to be arbitrarily changed by a variable resistor 84.

Since the output of the one-shot multivibrator 83 resets the frequency divider 86, the frequency divider 86 becomes ready for operation after the _T3 period ends. At this time, the output of the frequency divider 86 is positive as shown in FIG. 10J, so the output of the frequency divider circuit 41 is applied to the frequency divider 86 through the AND gate 85 and is frequency-divided. When the output of the frequency divider 86 becomes negative, the AND gate 85 is closed and the operation is stopped. During this period, the Qm output of the frequency divider 86 becomes as shown in FIG. 10H, and since this output controls the AND gate 93, the signal for dividing the display screen 24 into 16 shown in FIG. As shown in FIG. 4, it appears as a broken line. The code conversion circuit 45 is an AND gate 8
9 is output, the circuit forcibly converts it into a specific code regardless of the information content of the signal processing circuit 48, for example, the distance scale 5 on the display screen 24.
When 1 and 52 are displayed in white, they are converted into a code compatible with white display. Scale connection/disconnection switch 88
If the contact point is set to the b side, the output of the AND gate 89 is suppressed, and the display is instantly turned off. Also, by changing the division ratio with the output Qm of the frequency divider 86, the fine scale display 52 in FIG.
Needless to say, the number and width of broken lines can be changed.

〔Effect of the invention〕

According to this invention, as mentioned above, main memory is
In the case of a RAM configuration, among the address counters for storing memory, the detection number counter counts the carry signal of the 1 detection counter and advances the address, so the address is automatically set in the order of the oldest detection cycle. In addition to being able to arrange and import the data, reading out the display operation can be started from that point without providing any special configuration for display, and the data can be arranged and displayed in the order of the oldest detection cycle.

In addition, since raw detection information is always stored in the main memory of the correlation processing means, it is possible to handle not only cases where the noise situation at the start of detection is unknown, but also cases where the noise situation suddenly changes in the middle of the display screen. However, by turning correlation processing on and off or changing the correlation processing conditions, you can arbitrarily and at any time adjust to the optimal processing state, and the currently displayed detection information will disappear. In addition, it eliminates the inconvenience of unnecessarily overlooking detected information, and simply correlates adjacent read signals without using the troublesome method of correlating the detected information by returning it chronologically in relation to its detection cycle. As a result,
It has the advantage of being able to perform the same processing as when correlating information in time series corresponding to the same distance point within each detection cycle.

[Brief explanation of the drawing]

The drawings show an embodiment, and FIG. 1 is a block diagram, FIG. 2, FIG. 6, FIG. 9, and FIG. 10 are waveform diagrams for explaining the present invention, and FIGS. 3 and 4 are display screens. FIG. 5 is a partially detailed view of an embodiment of the present invention, and FIGS. 7 and 8 are tables for explaining the present invention. 11...Transmitter, 12...Transducer, 13...
Seabed, 14...Fish school, 15...Receiver, 16...
Leakage of transmitted pulse, 17...Reflected wave of fish school, 18
...Reflected waves from the ocean floor, 19...AD converter, 21...
...Buffer memory, 22...Main memory section, 23...
...Cathode ray tube display device, 24...Display screen, 25...
... Display line, 26 ... Display transmission line, 27 ... Display of fish schools, 28 ... Seabed display, 29 ... Reference oscillator, 31 ... Frequency divider, 33 ... Variable frequency division circuit, 3
4... Range selection switch, 35... Frequency divider, 3
7... Frequency divider, 38... Selection circuit, 39... Command circuit, 41... Frequency division circuit, 42... Frequency division circuit, 4
3... Transfer control circuit, 44... Frequency dividing circuit, 45...
...Code conversion circuit, 46...Signal processing circuit, 47
... Decoder, 48 ... Signal processing circuit, 49 ...
Characteristics selection switch, 51... Coarse scale display, 52...
...Fine scale display, 60...Horizontal synchronization signal, 61...
Coarse scale signal, 62... Fine scale signal, 63... Vertical synchronization signal, 66... Inverter, 67... AND gate, 68... AND gate, 69... OR gate, 70... AND gate, 71... AND Gate, 72...OR gate, 73...Address counter, 74...Address counter, 75...
RAM, 76...AND gate, 77...Differential circuit, 78...ROM, 79...Shift register,
80...Counter, 81...Switching circuit, 82...
Differential circuit, 83... One-shot multivibrator, 84... Variable resistor, 85... AND gate, 86... Frequency divider, 87... Display position determining circuit, 88... Scale connection/disconnection switch, 89... Inverter, 90... Frequency divider, 91... Decoder, 92
...Decoder, 93...And gate, 94...
Orgate.

Claims (1)

[Claims] 1. Detection information having a detection period is converted into a digital signal, and one screen of the display surface formed by horizontal main scanning and vertical sub-scanning of a cathode ray tube display device is stored in the main memory. A display signal obtained by capturing and storing the stored contents and reading out the stored contents according to the display cycle of the display surface is displayed in such a manner that the distance from the reference position of the display surface corresponds to the detection distance. A display in which signals corresponding to one detection period of the detection period are displayed in a single line in the vertical direction of the display surface, and the display is arranged in order of oldest detection period. In a detector having: (a) the main memory is configured with a RAM, and is an address counter for capturing, storing, and reading the digital signal, which corresponds to capturing the digital signal within the one detection cycle (hereinafter referred to as a counter);
(1) means for providing a counter corresponding to the number of detection cycles (hereinafter referred to as a detection number corresponding counter); b. starts counting write clock pulses, and imports the memory by counting the detection number corresponding counter based on a carry signal output when the count reaches a scheduled number; c After the carry signal is counted by the detection number counter in the capture counting means, the detection number counter counts readout clock pulses, and the signal corresponding to the horizontal main scanning is counted by the 1 detection counter. A cathode ray tube display detector characterized in that it comprises readout counting means for performing the reading. 2. Converts ultrasonic detection information with a detection period into a multi-digit digital signal, and imports one screen of the display surface formed by horizontal main scanning and vertical sub-scanning of the cathode ray tube display device into the main memory. A display signal obtained by reading out the stored contents according to the display period of the display surface is stored in the display signal in such a manner that the distance from the reference position of the display surface corresponds to the detection distance. has a display in which signals corresponding to one detection cycle of the detection cycle are displayed in a single line in the vertical direction of the display surface, and the display is arranged in order of oldest detection cycle. In the detector, a. The main memory is configured with a RAM, and is an address counter for capturing, storing, and reading the digital signal, and is a counter (hereinafter referred to as a counter) corresponding to capturing the digital signal within the one detection cycle.
(1) means for providing a counter corresponding to the number of detection cycles (hereinafter referred to as a detection number corresponding counter); b. starts counting write clock pulses, and imports the memory by counting the detection number corresponding counter based on a carry signal output when the count reaches a scheduled number; c After the carry signal is counted by the detection number counter in the capture counting means, the detection number counter counts readout clock pulses, and the signal corresponding to the horizontal main scanning is counted by the one detection counter. readout counting means for performing said readout; d readout signal correlation means for obtaining a correlation signal in which readout signals adjacent to said readout are correlated by digital values of said plurality of digits of each of said readout signals; and e. An ultrasonic detection device comprising: correlation changing means for changing the correlation output value of the correlation signal by changing the combination of correlations based on digital values of the read signal.