JPS582627B2 - image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention enables relatively slow signals, such as reflected sound waves in fish finders, echo sounders, etc., to be recorded on a cathode ray tube in the same manner as recorded on recording paper in conventional fish finders, etc. The present invention relates to an image display device for displaying images, and particularly to a device for adding markers to the display.

Conventionally, graphical displays in fish finders and echo sounders are recorded on recording paper, and this is only recorded as black and white shading, or a part of it can be enlarged and displayed.
Recording multiple signals in parallel is relatively troublesome.

However, by displaying on a cathode ray tube, it is relatively easy to enlarge a part or display multiple related signals in parallel. When converted to color and displayed, the resolution is further improved, making it possible to easily distinguish signals that were previously indistinguishable.

In such an apparatus, the present invention simultaneously displays the marker on the display cathode ray tube.

The image display device according to the present invention will be explained below with reference to the drawings.

In the figure, reference numeral 11 indicates a color cathode ray tube for display, and this cathode ray tube 11 is controlled based on a clock signal from an oscillator 12.

That is, the output of the oscillator 12 is frequency-divided by a frequency divider 13, the frequency-divided output is further divided by a line-scanning signal generation circuit 14 to generate a line-scanning signal, and the output of the frequency divider 13 is used for area-scanning. The signal is also supplied to a signal generation circuit 15 and frequency-divided to produce a surface scanning signal.

The isoline scanning signal and the surface scanning signal are supplied to the cathode ray tube 11, which deflects the electron beam and scans the display surface.

A main memory 16 is provided which stores enough information to display one screen of the display surface of the cathode ray tube 11.
is, for example, a shift register whose output is the gate 17
The light is circulated through the camera and is supplied to the cathode ray tube 11 to be displayed as an image.

In this example, different colors are displayed depending on the signal level, and in the color converter 18, the digital signal indicating the level of information input from the main memory 16 is converted into a color signal, that is, the output terminal 19
An output is selectively generated at one or more of R, 19G, and 19B depending on the input level, and these terminals 19R, 19G,
The red electron gun of the color cathode ray tube 11 is activated by the output of 19B.
The green electron gun and blue electron gun are controlled respectively.

Furthermore, a luminance signal component can be detected and luminance modulation can be applied if necessary.

Note that the shift control for the main memory 16 is controlled by the output from the main oscillator 12 supplied to the clock generator 21, and the clock generated by the clock generator 21.

Input signals to be displayed are stored in the main memory 16, and the storage is such that information for one display line of the color cathode ray tube 11, in this example, one scanning line, is rewritten. Ru.

For this rewriting, a reference trigger for the input signal is given from the trigger terminal 22, and the input signal from the terminal 23 is then stored in the buffer memory 24 as display information for one display on the cathode ray tube 11.

Therefore, the write control signal generation circuit 25 is set by the trigger signal from the trigger terminal 22, and the low-speed write clock generator 26 is operated by the output thereof, and this clock generator 26 receives the divided signal from the frequency divider 13. is divided and a slow clock is started, and this clock is connected to the OR circuit 27.
The buffer memory, for example, the shift register 24, is shifted and controlled through the buffer memory, for example, the shift register 24.

The input signal from the terminal 23 is converted into a digital signal by the AD converter 28, and this is written into the buffer memory 24 through the OR gate 29.

This write clock is counted by the write counter 31, and when this count value counts the number of pixels for one display line, an output is generated and the write gate signal generation circuit 25 is reset.

Therefore, low speed write clock generator 26 stops operating and writing to buffer memory 24 is stopped.

The output of the low-speed write counter 31 is also supplied to a circuit 32, which detects the vertical synchronization signal immediately after the low-speed write is finished, and sets the second write gate signal generation circuit 33 by this detected synchronization signal. .

This causes the medium speed clock generator 34 to operate and generate a medium speed clock pulse as the divided output from the frequency divider 13. This medium speed clock pulse is supplied to the OR gates 27 and 35 to read out the contents of the buffer memory 24. At the same time, this is written into the buffer memory 36.

This medium speed clock is also counted by the read/write counter 3γ, and when the information transfer from the buffer memory 24 to the buffer memory 36 is completed, an output is generated from the counter, and the second write gate signal generation circuit 33 is reset, thereby generating a medium speed clock pulse. will be stopped.

After this writing is completed, the contents of the buffer memory 36 are transferred to the main memory 16, in which case the oldest information in the main memory 16 is erased and the contents of each display line are sequentially shifted one by one toward the oldest.

Therefore, an output is generated from the read/write counter 3γ, that is, when writing to the buffer memory 36 is completed,
The gate signal generating circuit 38 is set and its output becomes logic ``1'' which is inverted by the inverter 39 and the gate 17 is closed.

On the other hand, the readout gate signal generation circuit 41 is set by the output of the counter 37, which generates a signal to the readout gate 1 to open the gate 42, and the readout clock generator 43 operates. The clock signal is formed into a clock signal synchronized with the clock generator 21, and this clock signal is sent to the buffer memory 36 through the OR gate 35.
The read output is written into the main memory 16 through the gate 42 by the clock of the main clock generator 21.

The clocks from the read clock generator 43 are counted by a read counter 44, and when a value sufficient to transfer all the information in the buffer memory 36 to the main memory 16 is counted, an output is generated and the read gate generating circuit 41 is reset.

The gate signal from the read gate control signal generation circuit 41 is also supplied to an AND circuit 45 through an inverter, the AND circuit 45 matches the output of the gate signal generation circuit 38, and the output is supplied to an AND gate 46. Ru.

Therefore, when the information from the buffer memory 36 has been transferred to the main memory 16, the gate 42 closes and the gate 46 opens, and the output of the main memory 16 passes through the delay memory 47, which has a delay amount corresponding to one scanning line, and further passes through the gate 46 to the main memory 16. It is returned to memory 16.

Therefore, new information is written to main memory 10 while old information is shifted by one scan line.

A counter 48 is operated by the output of the gate signal generation circuit 38, and when the number of line scanning lines for one screen from the frequency divider 13 has been counted, the gate signal generation circuit 38 is reset.

Gate 17 is therefore opened, the output of main memory 16 is circulated through gate 17, and gate 46 is closed.

In this way, new information is written to main memory as one line scan signal.

This writing is performed every time a trigger signal is generated from the terminal 22.

Generally, the operating speed of the cathode ray tube 11 is much faster than the generation of this trigger signal, and therefore, under normal conditions, information in the main memory 16 is displayed on the cathode ray tube 11 as a still image.

As shown in FIG. 2, for example, new information is displayed as one line scanning line 48 at the right end of the display screen of this cathode ray tube, and each time new information is input, the display line increases by one line.
Move each book to the left.

In this way, for example, in a fish finder, the transmission line 49 in FIG. 2 is displayed, the seabed line 51 is displayed, and furthermore, the school of fish 52 is displayed.

As a whole, such a screen gradually moves from the right to the left in the figure, and new information is displayed at the right end.

In addition, if the color display is used as described above, the underwater part is displayed in blue, relatively large levels such as the transmission line 49 and the seabed line 51 are displayed in black, and relatively high levels such as the fish school 52 are displayed in black. Low values can be displayed in red to make them more visible.

In such a display, for example, as shown in FIG.
This allows the depth of the displayed image to be read.

Fig. 2 shows a case where the marker 54 also moves with the display, so in the figure, sufficient time has not passed since the image display started and no image appears on the left half; A marker 54 is also displayed only in that part.

In such a case, the power information is stored in the main memory 1.
6, but this is done in synchronization with the input signal.

In FIG. 1, the output of frequency divider 13 is supplied to frequency divider 55, which divides the frequency, and the output is differentiated by differentiation circuit 56, and its falling pulse is supplied to gate circuit 57, for example.

Gate circuit 57 is opened by a gate signal from write gate signal generation circuit 25.

Therefore, for example, as shown in FIG. 3A, a trigger signal is generated at the terminal 22, and in response, a received signal 49a1 corresponding to the transmission line 49 is transmitted from the input terminal 23 as shown in FIG. 3B, and a reflection corresponding to the school of fish is generated. The reflected signals 51a corresponding to the signals 52a1 and 52a1 are sequentially received.

The write gate signal generation circuit 25 generates a gate signal as shown in FIG.
A frequency-divided output as shown in FIG. The data is not taken out and supplied to the buffer memory 24 through the OR gate 29.

In the AD converter 28, each sample value of the input signal is output as a 4-bit parallel digital signal depending on whether it belongs to one of 16 levels, for example, and as shown in FIG. 28b, 28
The 4-bit parallel signals of c and 28d are sent to the OR gate 29a,
29b, 29c, and 29a, and shift registers 24at24b and 24 constituting the buffer memory 24, respectively.
c and 24d in parallel.

Dividing each sample value of the input signal into 16 levels in this way allows the color cathode ray tube 11 to display each level in 16 different colors.

It is only necessary to decide which one or more of the OR gates 29a to 29d the OR gates 29a to 29d are to be supplied with the MARG signal from the gate 57 depending on whether the MARGAR signal 54 is to be displayed as a different color.For example, in FIG. This is a case where the marker 54 is displayed as a red line.

The marker 54 is changed by changing the detection range.

For example, if you are applying maca every 10m at a depth of 50m and you change the detection distance to 100m, then
Markers may be placed every 0m, or markers may be placed every 10m.

If the number of markers to be displayed is always constant regardless of the range, the frequency dividing ratio of the frequency dividing circuit 55 may be changed in conjunction with changing the write clock generating circuit 26 according to the distance.

As mentioned above, when an ultrasonic pulse is transmitted in synchronization with a trigger signal, its reflected signal is written into the buffer memory 24 from the terminal 23, but writing to the buffer memory 24 is performed by the write clock generation circuit 26. This is performed for a fixed number of clocks, for example, 256 clocks.

When the detection range is 50 m deep and the write clock generation circuit 26 divides the output of the frequency divider 13 into 17H, if the detection range is 100 m, the write clock generation circuit 26 divides the frequency by 2N. The period during which the reflected signal from the terminal 23 is written into the buffer memory 24 by 256 clocks is doubled.

In this manner, the frequency division ratio of the write clock generation circuit 26 is changed in accordance with the change in the detection range.

Therefore, if the detection range is 50 m and markers are displayed every 10 m, the frequency division in the frequency dividing circuit 55 is set to 1/5N.
When the number of clocks written into the buffer memory 24 is 256, a marker signal may be written into the buffer memory 24 every 51 clocks.

When the detection range is 100 m, the number of macaques to be displayed is the same, and when macaques are displayed every 20m, the frequency division in the frequency dividing circuit 55 is set to 1/ION.

However, if you want to display it every 10m, you can leave it at 1/5N.

Both the write clock generation circuit 26 and the frequency dividing circuit 55 divide the output of the frequency divider 13, and these circuits 26, 55
By resetting the frequency dividing operation for each trigger signal, the phase relationship between the trigger signal and the marker signal becomes desired.

Also, when the range is changed in this way, the writing clock cycle to the buffer memory 24 changes, so for example, the differentiating circuit 5
When the pulse width of the output from the differentiating circuit 56 is kept constant, depending on the range, the output pulse width of the differentiating circuit 56 may correspond to one pixel or to a plurality of pixels, and the thickness of the marker 54 may vary depending on the range. It will be different.

Therefore, the marker can always have a constant thickness regardless of such range changes.

For example, as shown in FIG. 5, the output of the marker frequency divider 55 is supplied to the clock terminal of the JK flip-flop 61, the J and K terminals are left open, and the Q and frequency outputs are supplied to the J and K clock terminals of the JK flip-flop 62. Supplied to each terminal.

Reading to the flip-flop 62 is performed by supplying the write clock from the write clock generation circuit 26 to the clock terminal, and the page output is used to read the data from the flip-flop 61.
Clear.

When doing this, an output whose pulse falls according to the next clock pulse of the write clock 26 than the fall of the output of the frequency divider 55 is obtained at the output terminal of the flip-flop 62, that is, one pulse of the clock pulse 26 is always output. A width of 0 is generated every time the marker frequency divider 55 falls, and this is supplied to the gate 5γ.

Therefore, a line corresponding to one pixel is always displayed regardless of the range change.

Next, when fine markers 54b are inserted into the coarse markers 54a as shown in FIG. 6, it is preferable to distinguish between the fine markers 54b, for example, so that they can be placed in different colors.

For this purpose, as shown in FIG. 7, the output of the range frequency divider 55 is differentiated by the differentiating circuit 56a as described above, and the output is supplied to the gate circuit 57a, from which a marker signal 63a is obtained. This is supplied to all of the OR gates 29a to 29d to display red as a marker 54a, for example.

Further, in the marker frequency divider 55, an output is taken from an intermediate frequency division stage and differentiated in a differentiating circuit 56b, and this differentiated output is selected by the write gate signal by the AND gate 5γb, thereby, for example, the marker signal 63a. A marker signal 63b having a period of 1/5 of the period is obtained and is supplied only to the OR gate 29d, so that the marker 54b in FIG. 6 can be displayed in white.

Alternatively, the markers 54a and 54b shown in FIG. 6 may be distinguished by their thickness.

As shown in FIG. 8, the output of the marker frequency divider 55 is differentiated by a differentiation circuit 56a, and the output from an intermediate frequency division stage is differentiated by a differentiation circuit 56b. The configuration is similar to that shown, but the differentiating circuit 56b
In this case, the clock from the clock generator 26 is supplied to the flip-flop at the subsequent stage to obtain the marker signal 63b shown in FIG. 7 having a width corresponding to one pixel.

On the other hand, for the differentiating circuit 56a, a signal is applied from a terminal 64 to a clock terminal at the latter stage of the flip-flop, and a signal having a period, for example, three times as long as the clock period of the clock generating circuit 26 is applied to this terminal 64. The pulse width of the marker signal 63a shown is, for example, three times the pulse width and the same period is obtained, and the outputs of these differentiating circuits 56a and 56b are supplied to the gate 57 through an OR gate.

In this way, for example, the marker 54a can be displayed thick and the marker 54b can be displayed thin.

The marker does not need to be displayed over the entire width of the display screen, but may be displayed partially as shown in FIG.

In this case, for example, in FIG. 1, the output of the oscillator 12 is controlled by the time control circuit 65, and the marker generation frequency divider 55 is operated periodically for a certain period of time, for example, every time a trigger pulse is generated. The marker may be generated during some trigger signals, and the operation of the frequency dividing circuit 55 may be stopped during other times.

In this case, at least one set of markers 5 on the display screen
The time control circuit 65 is configured so that 4 is displayed.

In the above description, the marker signal was stored in the main memory 16, but
It is also conceivable to create a marker signal separately, add it simultaneously with the output of the main memory 16, and supply it to the cathode ray tube.

For example, as shown in FIG.
Synchronize with the line synchronization signal of 4 twists, for example, Part 1
Five pulses are generated at intervals that divide the line scanning line of the book into five equal parts, and this output is combined with the output of the main memory 16 by an OR gate 68 via a switch 67 as needed, and is supplied to the color conversion circuit 18. do.

For example, if the switch 67 is turned on, each scanning line is
Maca 54 is generated at each equally divided position.

However, in this case, when switching the detection range, detection signals with different detection ranges will be displayed on one half of the left and right sides of the display screen and on the other half until the detection signals in the main memory are for the new range. However, the power is compatible with the new range, and there is a risk of misreading the display of the detection signal of the old detection range.

However, according to the present invention, since the marker force signal is written in the main memory, a marker corresponding to each display is displayed corresponding to each detection range, and a new reading can be performed.

In addition, when a marker is generated partially as shown in Figure 9, as explained in Figure 7, if new information is displayed at the right end, for example, the marker overlaps with that information and becomes difficult to see. It is also possible to shift the marker from the new information position and create a marker slightly to the left in FIG. 2 to avoid this.

In this case, for example, in FIG. 10, the marker signal generator 66 is gated by a gate signal generated from the output of the surface synchronization signal, and in the portion where new information is displayed, the marker signal is transmitted to the cathode ray tube. All you have to do is prevent it from being supplied.

In the above description, the transmission trigger signal is used as the trigger signal from the terminal 22 for writing the reception signal into the main memory.
For example, depending on which part of a certain detection range is displayed, for example, 50m from the water surface, and further 20m from the water surface.
It is also possible to detect an arbitrary range, such as a range of ~70 m or a range of 40 m to 90 m.

Such a display may be performed, for example, as shown in FIG.

That is, the output of the oscillator 71 is divided by a frequency divider 72, further divided by a frequency dividing circuit 73 to obtain a period similar to the trigger period, this output is differentiated by a differentiating circuit 74, and this differential The output is, for example, a delay circuit 7 that provides a delay corresponding to the depth from the sea surface at which the transducer of a fish finder is installed.
5 to the transmission trigger pulse generation circuit 76,
This is driven, and the transducer 77 is excited.

A flip-flop 80 is connected to the output pulse of the differentiating circuit 74.
is set, and the counter 78 is activated by its output.

For example, a terminal 79a for selecting a clock for displaying a 50m section.
and a terminal 79b for selecting the clock for displaying the 100m section.
is selected by the switch 81, and the selected clock is counted by the counter 78 from the frequency dividing circuit 72.

The count contents of the counter 78 are decoded by a decoder 82, and pulses whose phases are sequentially shifted and whose repetition frequency is the same as the transmission trigger period are obtained from the terminals 83a to 83n.

Therefore, by switching the output terminals of these decoders using the switch 84 and applying them to the trigger terminal 22, it is possible to determine in which detection range the received signal is to be displayed.

In other words, if you select the first terminal 83a, you can obtain the transmission pulse at the same time, so this is for example 50m from the water surface.
If the second terminal 83b is selected with the switch 8, the range from 20 m to 70 m, for example, will be displayed.

Therefore, in the case of the marker described above, it is possible to insert the marker regardless of such shift selection.

When the counter 82 becomes full, the flip-flop 80 is reset and the counter 82 stops operating.

As described above, according to the present invention, an image can be displayed on a cathode ray tube in a state similar to that of conventional recording paper, and moreover, color display can be easily performed and display with good resolution can be performed.

In this case, the distance marker can be attached, and it is possible to attach it as various distance markers.

Conventionally, with recording paper, a cursor with a distance marker was placed across the recording paper to read the distance of the image recorded on the recording paper, but since the markers differ depending on the distance range, it is difficult to use different types of cursors. However, according to the present invention, there is no need for such replacement, and it is only necessary to switch the dividing ratio of the marker frequency divider at the same time as switching the distance range. There is no need to provide a cursor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of an image display device according to the present invention, FIG. 2 is a diagram showing an example of its display state, and FIG. 3 is a waveform diagram for explaining the operation of the marker signal generation portion in FIG. 2. 4 is a block diagram showing an example of a portion where a marker signal is written, FIG. 5 is a block diagram showing an example of the differentiation circuit 56, FIG. 6 is a diagram showing another example of marker display, and FIG. is a block diagram showing another example of marker display signal generation and its writing generation part, FIG. 8 is a block diagram showing still another example thereof, FIG. 9 is a diagram showing one other example, and FIG. This figure is a block diagram showing another example of marker signal insertion, and FIG. 11 is a block diagram showing a circuit for obtaining a trigger signal in a shift operation. 11: Cathode ray tube, 12: Main oscillator, 13: Frequency divider, 16
: Main memory, 22: Trigger terminal, 23: Input signal terminal, 18: Color conversion circuit, 24, 36: Buffer memory, 55: Marker generation frequency divider, 56: Differential circuit, 57:
Gate, 54: Marker.

Claims (1)

[Claims] 1 A display cathode ray tube, a main memory that stores information for one screen of the display, is repeatedly read out in synchronization with the scanning of the display surface of the cathode ray tube, and supplies the input signal to the display cathode ray tube; A buffer memory for storing the amount of information for one display line of the display cathode ray tube, and the contents of the buffer memory are predetermined on the display surface of the display cathode ray tube in synchronization with a vertical synchronization signal of the display cathode ray tube. At the same time, the vertical synchronization signal and the timing for reading out the contents already stored in the main memory are set relative to each other by the horizontal scanning period. means to shift the display on the display screen one by one to the old display line, and an input method for the buffer memory in order to display a marker of a line perpendicular to the display line of the display cathode ray tube. An image display device comprising means for periodically writing a magnetic signal in synchronization with writing of the signal.