JPS586153B2 - Ultrasonic detection and display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION In an ultrasonic detection display device such as a fish finder, the present invention displays the detection information of one time as one display line, which is sequentially displayed on a cathode ray tube through the display 1. The present invention relates to a display device capable of displaying a display screen similar to that of a conventional recording paper, and particularly to a display device in which display information is stored in a random access memory, read out from the memory, and displayed on a cathode ray tube.

For example, in a fish finder, one detection information is displayed as a vertical display line at one end of the display screen of a cathode ray tube display device, and the oldest display information is displayed as a vertical display line at the other end of the display screen. The oldest information is displayed, and the oldest information disappears.
By ensuring that new information is always displayed at the same end of the display screen, a display similar to that on conventional recording paper is provided.

By using cathode ray tubes, these display devices can display more information than recording paper records.
In particular, when a color cathode ray tube is used as a display device to display different colors depending on the detection signal level, the display has very high resolution. By making the colors conspicuously distinguishable even with a slight level difference, it is possible to clearly display the colors, which is the case when the colors cannot be distinguished at all depending on the recording on the recording paper.

Further, with such a cathode ray tube display device, it is easy to enlarge and display a particular portion, which is very convenient.

When displaying using a cathode ray tube display device, each position on the screen on the cathode ray tube, that is, each pixel position, is assigned an address, and information on each of these positions is stored at the corresponding address in memory. At first, it is conceivable to perform display by reading out the memory in the order of the addresses and scanning the cathode ray tube display in synchronization with the reading.

However, if the address is associated with each position on the screen of each cathode ray tube in the random access memory in this way, each time new detection information is obtained, it is written to a fixed address.
Although it is easy to understand at first glance, the disadvantage is that it is necessary to sequentially shift all the information previously stored at each address by one display line, and the operation of rewriting the address of this pre-stored information is complicated and takes time. An object of the present invention is to use a random access memory as a storage device for display information in an ultrasonic detection display device that displays detection information as a single display line on a display screen, and to constantly store new information in advance on the display screen. To provide an ultrasonic detection and display device that displays information in a predetermined position, and allows the old screen to disappear and the older information to move sequentially by one display line to the older side with a simple operation. It's about doing.

According to the present invention, an address counter for a random access memory in which detection information is stored is incremented in synchronization with the main scanning of the cathode ray tube display, and moreover, the counting of the address counter is repeated in synchronization with the sub-scanning of the cathode ray tube display. It is done synchronously.

The address counter stops incrementing during the main scanning retrace line interval and the sub-scanning retrace line interval.

In other words, during one main scan, information for one display line is read out from the main memory by the increment of the address counter, and is given to the cathode ray tube display device, for example, as one display line in the vertical direction. Is displayed.

The oldest information is read out at the beginning of each sub-scan.

New detection information is written to main memory during the blanking interval of the vertical or sub-scan.

Therefore, the new information is written to the main memory at the address position of the old detection information, and at the start of the next sub-scanning, the address counter changes by one main scanning line from the previous display. Since the information has progressed, the next oldest information will be read, and the last information read will be the newest information written this time.

In this way, each time new information is written, the oldest information is erased and the new information is always displayed at one predetermined end, that is, on the last main scanning line in the sub-scanning direction.

In this way, when writing, the display on the screen can be easily shifted without converting the address of information that has already been written.

Next, an embodiment of the ultrasonic detection and display device according to the present invention will be described with reference to the drawings.

In the figure, a clock signal from a clock oscillator 11 is divided by a variable frequency divider 12 to produce a trigger pulse shown in FIG. 2A, and the trigger pulse obtained at a terminal 13 drives a transmitter 14. The transmitter 14 is the transducer 1
5 to emit ultrasonic pulses toward the seabed 16.

The reflected waves from the seabed 16 or a school of fish 17 on the way are transmitted and received as reflected waves 19 from the school of fish and waves 21 from the seabed 16 after a pulse 18 corresponding to the transmitted wave pulse, as shown in FIG. 2B. The wave is received by the wave transmitter 15 and then received by the receiver 22.

The received detection information is converted into a digital signal by the AD converter 23.

The detection information is periodically sampled, and the level of each sampling point is quantized into 3 bits, ie, 8 levels, and converted into a digital signal, which is stored in the buffer memory 24.

The information stored in this buffer memory 24 is arranged so that one detection information has the same number of sample points, for example, always 256 sample points.

Therefore, when the detection distance is long, that is, when detecting a deep place, the sampling period in the AD converter 23 becomes long, and when the detection information is shallow, that is, when the detection distance is short, the sampling period for the detection information becomes short. Ru.

The detection information stored in the buffer memory 24 is stored in the main memory 2.
Transferred to 5.

The main memory 25 stores display information for one screen of the cathode ray tube display 26, is always read out in synchronization with the scanning of the cathode ray tube display 26, and is given to the cathode ray tube display 26 as display information.

The output of the clock oscillator 27 is divided by a frequency dividing circuit 28 to produce a main scanning line signal, so-called horizontal scanning line signal, which is supplied to the cathode ray tube display 26. This main scanning line signal is also applied to a frequency dividing circuit 29. The sub-scanning line signal, so-called vertical scanning line signal, is frequency-divided and supplied to the cathode ray tube display 26.
Main and sub-scanning are performed.

The display screen of the cathode ray tube display 26, for example, as shown in FIG. 3, has main scanning in the vertical direction from top to bottom, and sub-scanning in the horizontal direction, which is scanning from left to right in the figure. .

On this display screen, the newest detection information is displayed as a display line 31 at one end of the display screen, the right end in the figure, that is, by the last main scan of the sub-scans.

The oldest information is displayed on the vertical display line at the left end of the diagram.

In this way, the display 32 corresponding to the seabed 16 in FIG. 1, the display 33 corresponding to the school of fish 17, and the transmission line 34 corresponding to the transmission pulse are displayed.

In order to make this display a color display using a color cathode ray tube, a color conversion circuit is provided to display colors according to the level, but in this FIG. Things are built in.

In the present invention, a random access memory is used as the main memory 25.

Next, the control for writing new detection information into this random access memory 25 and reading it from this memory will be explained.

The main scanning synchronizing signal from the frequency dividing circuit 28 is shown in FIG. 4A, and the sub-scanning synchronizing signal from the frequency dividing circuit 29 is shown in FIG. As shown, a gate signal that is at a high level only during each main scanning period Tl is generated, and thereby the gate circuit 36 is controlled to open and close.

A clock from the clock oscillator 27 is also supplied to the gate circuit 36, and a read clock as shown in FIG. 4D is supplied from the gate circuit 36 to the address counter 37 only during each main scanning period Tl.

The readout clock generated in each main scanning period T7 is selected to have the number of pixels constituting one display line, for example 256, and is synchronized with the main scanning. are read out to form one display line.

The address of the start of main scanning of the oldest detection signal currently stored in the main memory 25 is A1, the address of the start of main scanning of the next oldest detection signal is A2, and the following addresses are given in the same manner. The starting address of the main scan of the signal is A256, and as shown in FIG. 5a, the oldest detection information is displayed as a display line from the top to the bottom of the left edge of the display screen.

Therefore, the top pixel information of the display line L1 is stored in the main memory 2.
5 is read from address A1.

Next, the oldest detection information is displayed as the display line L2 to the right of the display line L1, and the top pixel information is that read from the address A2.

In this way, the display line moves to the right as new information is added, that is, the sub-scanning direction is from left to right, and the newest information is displayed as the rightmost display line L256.

Therefore, when the sub-synchronization signal shown in FIG. 4B ends, that is, after the sub-scanning blanking time ends, the first address to be read in the next main scan is A1 in this example, as shown in FIG. 4E. Therefore, the start address of the main scanning immediately before the sub-scanning synchronization signal is A256.

In this way, information on one display screen is read out and displayed in synchronization with scanning, and this is repeated to appear on the display screen as a still image.

Next, when new detection information is written into the main memory 25, the writing is performed within the blanking interval of the sub-scanning.

That is, a clock pulse from the terminal 39 of the control circuit 38 is applied to the buffer memory address counter 41 to read new detection information from the buffer memory 24, and this clock pulse is also applied to the main memory address counter 37 through the OR gate 42. , writing is performed to this.

At this time, from the terminal 43 of the control circuit 38 to the main memory 25, the fourth
A write command as shown in Figure G is given.

At this time, the clocks given to the memory 25 are as shown in FIG.

As mentioned above, the address counter 37 at the beginning of the sub-scanning synchronizing signal, that is, after one scan of the screen is completed, always becomes the address for the beginning of the oldest display line L1.

Therefore, in FIG. 5a, the address is A1, and the detected information in the buffer memory 24 is sequentially written into the main memory 25 from this address A1.

As shown in FIG. 4F, the address at the start of writing is A1, and the address advances by one display line by writing, and when the sub-scanning synchronization signal ends and the next read clock is applied, it starts from address A2. .

Therefore, as shown in FIG. 5b, the leftmost display line L1 displays detection information starting from address A2.

Detection information starting from address A3 is displayed on the second display line L2, and the display information is shifted to the left side in the figure by one display line toward the older display relative to Figure 5a. , since the counter 37 makes one cycle in the sub-scanning, in the last main scanning of the sub-scanning, the information from the address A1 of the newly written information is read out and displayed on the display line L256, that is, the new information is displayed on the rightmost side. Ru.

In this state, the display shown in FIG. 5b continues until new detection information is written.

Next, when new information is written, the display sequentially moves to the left in the same way, and the new information is displayed on the rightmost display line L256. This will be explained with reference to FIGS. 1 and 6, together with the control for writing and reading thereof.

When the transmit trigger occurs at the terminal 13, it is also supplied to the control circuit 38, and the flip-flop 4 in the control circuit 38
4 is reset, the output of flip-flop 44 becomes low level, which is inverted by inverter 45, becomes high level as shown in FIG. 2C, and gate 46 is opened.

A write clock having a period corresponding to the current detection distance, that is, the selected range, is supplied from the output terminal 47 of the frequency dividing circuit 12 through the gate 46 and further from the output terminal 48 through the OR gate 49 to the address counter 41 of the buffer memory 28.

This write clock is shown in FIG. 2D.

The address counter 41 is reset in advance by a trigger pulse from the terminal 13 before the clock is supplied, and always counts from the first address.

As a result, the digital signal from the AD converter 24 is written into the buffer memory 24.

Also, at this time, the output of the inverter 45 (FIG. 2C) is applied to the buffer memory 24, and this memory is placed in the write mode.

As this writing progresses, the buffer memory address counter 4
When 1 is the address for the end of information on one display line segment to be stored in the buffer memory 24, the address counter 41
An output is generated from terminal 51 of , which sets flip-flop 44, thus closing gate 46 and also stopping the supply of the write clock to address counter 41.

From this state, the information in the buffer memory 24 is transferred to the main memory 25 by the next sub-scanning synchronization borrow.

Therefore, the Q output of flip-flop 44 is applied to the clear terminal of flip-flop 52, and when this goes high, flip-flop 52 becomes operational.

Therefore, while the buffer memory 24 is being written, the flip-flop 52 is inoperable, but when the writing is completed, it becomes operational and the output of the sub-synchronization signal generation circuit 29 is supplied to the flip-flop 52 through the terminal 53. , this is set, its Q output becomes a high level, the flip-flop 54 is set, and its output also becomes a high level, and this and the high level of the Q output of the flip-flop 44 are supplied to an AND gate 55 and this gate 55 will be held.

A clock having a constant period from the frequency dividing circuit 12 passes through the terminal 56 and passes through the gate 55, and is further applied to the address counter 41 through the terminal 39 and the OR gate 49, as well as to the address counter 37.

That is, as shown in the enlarged waveform of FIG. 2C, when a sub-scanning synchronizing signal is generated immediately after writing to the buffer memory is completed as shown in FIG. 2E, the flip-flop 52 is set and the flip-flop 54 is also set. The output becomes a high level as shown in FIG. 2F, and this is supplied to the main memory 25 from the terminal 43 as a write command and opens the gate 55. Therefore, the output from the terminal 56 becomes high level as shown in FIG. 2G. Address counters 41, 37 as shown
are supplied respectively.

When an output is generated from the terminal 51 of the address counter 41,
That is, when all the new information written in the buffer memory 24 is read out, the flip-flop 54 is reset and the gate 5
5 is closed, and the main memory 25 returns to the read state.

In this way, the writing of new information to the main memory 25 is completed, but even if a sub-scanning synchronizing signal is generated before the new information is read out, the flip-flop 52 remains in the set state, so this is set again and the flip-flop 52 is set.
There is no way that 4 will be at a high level.

That is, once writing to the buffer memory 24 is completed, the contents of the buffer memory 24 are transferred to the main memory 25 during the immediately subsequent sub-scanning synchronization signal.

As described above, according to the ultrasonic detection and display device according to the present invention, the detected information is displayed in the same manner as recorded on conventional recording paper, and the resolution is excellent. However, by using a random access memory, there is no need to rewrite all the addresses when writing new information to the main memory 25. In other words, the display position on the display screen and the main memory By changing the relationship between the display position and the address by one display line each time new information is added, instead of fixing the relationship with the address No. 25,
There is no need to rewrite the addresses of all information, and the operation is simple and can be done in a short time.

The configuration of the control circuit 38 for this purpose can be of various configurations, and is not limited to the above-mentioned example. When applied to this cathode ray tube display, scanning starts from the bottom of the left edge and scans from bottom to top. In such a scanning case, for example, after writing to the buffer memory 24, it is read out. In other words, if the address counter 41 is operated as a reversible counter, it is possible to read the buffer memory 24 in the reverse direction when transferring it to the main memory. It can be displayed in the opposite direction.

In order to scan a display such as that shown in FIG. 5, it is sufficient to reverse the connection of the coils of the scanning circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of an ultrasonic detection and display device according to the present invention, FIG. 2 is a waveform diagram for explaining its operation, FIG. 3 is a diagram showing an example of a display screen, and FIG. 4 is a diagram showing an example of the display screen. FIG. 5 is a waveform diagram for explaining the operation of FIG. 1, FIG. 5 is a diagram showing the relationship between the detected information address of the main memory by writing information and the display line, and FIG. 6 is a concrete diagram of the control circuit of FIG. 1. FIG. 2 is a block diagram illustrating an example. 24: buffer memory, 25: main memory, 26: cathode ray tube display device, 37, 41: address counter, 28: main scanning synchronization signal generation circuit, 29: sub-scanning synchronization signal generation circuit.

Claims (1)

[Claims] 1 A scanning display whose display surface is scanned by main scanning and sub-scanning to display the display signal as an image, and which has the same number of addresses as the number of pixels on the display surface of the scanning display, and a main memory of a random access memory capable of storing information and supplying the read memory table as a display signal to the scanning type display; a first address counter for instructing an address to access the main memory; And in synchronization with the sub-scanning, a clock having a cycle of scanning one pixel in the main scanning is supplied to the first address counter, and the address is read by 1 in the sub-scanning cycle.
a readout clock generating means for circulating, an AD converter for converting ultrasonic detection information into digital information, a buffer memory, and a digital information converted by the AD converter;
means for writing the same number of samples as the number of pixels in the main scan;
Transfer means for supplying a clock equal to the number of main scanning pixels to read out the buffer memory, supplying the clock to the first address counter to increment it, and writing the digital information read from the buffer memory to the main memory. An ultrasonic detection and display device comprising: