JPS6075870A - Crt display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a cathode ray system that superimposes and displays video signals controlled by an interlaced display control circuit having an interlace ratio of 2:1 and a non-interlaced display control circuit on the same display section. It relates to a tube display device.

Conventionally, it is well known that when two or more display circuits are superimposed on the same display section for display, the superimposition is only possible if their respective horizontal scanning frequencies and vertical scanning frequencies are the same. Therefore, it is basically impossible to superimpose the displays of the interlace display control circuit and the non-interlace display control circuit and display them on one screen. This is because, if n is an arbitrary integer, the number of interlaced vertical rasters is (n-1-o,s), and the number of non-interlaced vertical rasters can only be n. Therefore, when trying to display the above-mentioned screens in a superimposed manner, since the horizontal scanning time is the same, there is a drawback that the interlaced and non-interlaced displays are shifted by 0.5 lines for every - vertical scanning.

The present invention includes a clock correction circuit configured to change a basic clock for generating a display signal of a non-interlace display control circuit during a retrace period, generates a pseudo-interlace signal, and superimposes it on an interlace display signal. An object of the present invention is to provide a cathode ray tube display device capable of displaying images.

The configuration of the present invention includes a cathode ray tube display section, an interlaced display control circuit, and a basic clock generation circuit.

It includes a video signal conversion circuit, a non-interlaced display control circuit, and a synchronization correction circuit.

The cathode ray tube display section includes a CRT and is used for displaying images. The interlace display control circuit is for interlacing and supplying video signals so that interlace display can be performed on a cathode ray tube display section. The basic clock generation circuit is for supplying a basic clock that determines the timing of display on the cathode ray tube display section. The video signal conversion circuit converts the video signal to be suitable for display on the cathode ray tube display and drives the cathode ray tube display. The non-interlaced display control circuit is designed to enable non-interlaced display as well as interlaced display.

The synchronization correction circuit is for correcting synchronization during non-interlaced display. The present invention makes use of the fact that the rask display shifts by 0.5 lines every - vertical scans when superimposing and displaying the video signals of the non-interlaced display control circuit. By lengthening the clock cycle input to the interlaced display control circuit and delaying the video signal by a time equivalent to one horizontal scanning period during the vertical retrace period, the synchronization correction circuit can perform one vertical scanning for every two vertical scannings. It is configured to take cycles.

The operating principle of the present invention will be explained below. It is well known that one vertical scanning period in the interlace method is represented by the number of (n + o, s) scans, and one vertical scan period in the non-interlace method is also represented by the number of n scans. It is well known. Therefore, for two vertical scan synchronizations in the interlace method, (n+0.5)X'2
= (2n+1) scanning lines are included, and in the non-interlaced method, (n)X2=2n scanning lines are included.

Therefore, if the interlaced method and the non-interlaced method are used in common, there is a problem that the display screen will be shifted. Therefore, in order to make the period of (2n+1) and 2n equal, one of the two vertical retrace times is
It is only necessary to extend the horizontal scanning period by a time corresponding to a scanning line segment.

The above is the principle of the present invention.

First, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram illustrating one embodiment of the present invention. In FIG. 1, 1 is a basic clock generation circuit, 2 is an interlaced display control circuit, 6 is a video signal conversion circuit,
4 is a cathode ray tube display section, 5 is a synchronization correction circuit, and 6 is a non-interlaced display circuit. In FIG. 1, an interlace display control circuit 2 operates based on the output clock of a basic clock generation circuit 1, and the output of the interlace display control circuit 2 is inputted to a cathode ray tube display section 4 via a video signal conversion circuit 6. On the other hand, the period correction circuit 5 is based on the same basic clock; it is taken out from the link generation circuit 1 and inputted to the non-interlaced display control circuit 6 according to the above-determined method.

FIG. 2 is a diagram showing an example of the operation timing of the cathode ray tube display device of the present invention according to FIG. 1. In the example shown in Figure 2, 1
The vertical period consists of 6.5 horizontal scanning lines. Although the number of horizontal scans is reduced in FIG. 2 for ease of understanding, the number of horizontal scans is actually the same as that of a normal rask scan. Interlaced display control horizontal synchronization signal H8YNC, vertical synchronization signal VS
YNC.

The part marked * for non-interlaced display control is extended by 0.5 lines to match the timing of the video signal VIDEO, etc., and is synchronized with interlaced display control. At this time, signals on the twin interlace side such as H8YNC and VSYNC are input to the display section, but signals on the non-interlace side are not input to the display section.

As explained above, in the present invention, by interpolating and correcting the output of the interlaced display control circuit and the output of the non-interlaced display control circuit within the vertical retrace period using a correction circuit, the above eraser φd is The present invention has the advantage that it is possible to simultaneously superimpose and display a non-interlace signal and a non-interlace signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a cathode ray tube display device according to the present invention. FIG. 2 is a timing chart showing an example of the operation of the cathode ray tube display device shown in FIG. 1...Basic clock generation circuit 2...[Co., Ltd.] Interlace display control circuit 3...Video signal conversion circuit 4...Cathode ray tube display section 5...Synchronization correction circuit 6...Fist non-interlace display circuit

Claims (1)

[Claims] A cathode ray tube display section including a CRT for displaying, an interlace display control circuit for supplying interlaced video signals so that the cathode ray tube display section can perform interlaced display, and a basic circuit for determining the timing of the display. a basic clock generation circuit for supplying a clock; a video signal conversion circuit for converting the video signal to be suitable for display on the cathode ray tube display section and driving the cathode ray tube display section; A non-interlaced display control circuit for supplying a video signal in a non-interlaced manner to enable non-interlaced display in addition to interlaced display, and a synchronization correction circuit for correcting synchronization during the non-interlaced display,
When performing the display by superimposing the video signal of the non-interlaced display control circuit, 0.
Taking advantage of the fact that the raster display shifts by five lines, the clock cycle input to the non-interlaced display control circuit is lengthened every two vertical scans, so that the vertical retrace period of the vertical scan is equal to one horizontal line period. A cathode ray tube display device, characterized in that the synchronization correction circuit takes one period for the two vertical scans by delaying the video signal by a corresponding amount of time.