JPS625769U - - Google Patents
Info
- Publication number
- JPS625769U JPS625769U JP9644685U JP9644685U JPS625769U JP S625769 U JPS625769 U JP S625769U JP 9644685 U JP9644685 U JP 9644685U JP 9644685 U JP9644685 U JP 9644685U JP S625769 U JPS625769 U JP S625769U
- Authority
- JP
- Japan
- Prior art keywords
- storage section
- signal
- scanning lines
- computer
- displayed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 1
Description
第１図は本考案に係わるコンピユータの実施例
を示すブロツク図、第２図Ａ〜Ｅは同コンピユー
タ内における各部の信号のタイミングを例示する
タイミングチヤート、第３図は飛越し走査を例示
する図、第４図は順次走査を例示する図である。
１……パソコン、２……モニターテレビ、３…
…垂直帰線期間検出回路、５……記憶部。
Fig. 1 is a block diagram showing an embodiment of a computer according to the present invention, Figs. 2 A to E are timing charts illustrating the timing of signals of various parts in the computer, and Fig. 3 is a diagram illustrating interlaced scanning. , FIG. 4 is a diagram illustrating sequential scanning. 1...PC, 2...Monitor TV, 3...
. . . Vertical retrace period detection circuit, 5 . . . Storage section.
Claims (1)
記憶部に記憶され、奇数走査線で表示される情報
が第２記憶部に記憶されてなるコンピユータにお
いて、 モニターテレビからＮＴＳＣ信号が入力され、
このＮＴＳＣ信号から垂直帰線期間を示す信号が
検出され、この信号に同期する一定周期の２値信
号に同期して前記第１記憶部と第２記憶部との内
容が交互に出力されるようになされたことを特徴
とするコンピユータ。[Scope of claim for utility model registration] Information displayed on even-numbered horizontal scanning lines is the first
In a computer in which information stored in a storage section and displayed on odd-numbered scanning lines is stored in a second storage section, an NTSC signal is input from a monitor television,
A signal indicating a vertical retrace period is detected from this NTSC signal, and the contents of the first storage section and the second storage section are alternately output in synchronization with a binary signal of a fixed period synchronized with this signal. A computer characterized by what has been done to it.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9644685U JPS625769U (en) | 1985-06-24 | 1985-06-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9644685U JPS625769U (en) | 1985-06-24 | 1985-06-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS625769U true JPS625769U (en) | 1987-01-14 |
Family
ID=30962200
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9644685U Pending JPS625769U (en) | 1985-06-24 | 1985-06-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS625769U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59221172A (en) * | 1983-05-31 | 1984-12-12 | Sony Corp | Interlace converting circuit |
-
1985
- 1985-06-24 JP JP9644685U patent/JPS625769U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59221172A (en) * | 1983-05-31 | 1984-12-12 | Sony Corp | Interlace converting circuit |
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