JPS6352354U - - Google Patents
Info
- Publication number
- JPS6352354U JPS6352354U JP14510786U JP14510786U JPS6352354U JP S6352354 U JPS6352354 U JP S6352354U JP 14510786 U JP14510786 U JP 14510786U JP 14510786 U JP14510786 U JP 14510786U JP S6352354 U JPS6352354 U JP S6352354U
- Authority
- JP
- Japan
- Prior art keywords
- display
- generated
- information signal
- video signal
- display circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 6
Description
第１図はこの考案に係る表示回路の一実施例を
示すブロツク回路図、第２図及び第３図は第１図
の動作を説明するための動作説明図、第４図はこ
の考案による重ね表示の一例を示す説明図、第５
図は従来の表示回路の一例を示すブロツク回路図
、第６図は従来の重ね表示例を示す画面図である
。
１１……ＣＲＴ表示管、１２……水平ドライブ
回路、１３……垂直ドライブ回路、１４……キヤ
ラクタジエネレータ、１５……表示管ドライブ回
路、１６……分周回路、１７……一水平走査期間
遅延素子。
Fig. 1 is a block circuit diagram showing one embodiment of the display circuit according to this invention, Figs. 2 and 3 are operation explanatory diagrams for explaining the operation of Fig. 1, and Fig. 4 is a superimposed circuit diagram according to this invention. Explanatory diagram showing an example of display, fifth
The figure is a block circuit diagram showing an example of a conventional display circuit, and FIG. 6 is a screen diagram showing an example of a conventional overlapping display. 11...CRT display tube, 12...Horizontal drive circuit, 13...Vertical drive circuit, 14...Character generator, 15...Display tube drive circuit, 16...Frequency dividing circuit, 17...One horizontal scanning Period delay element.
Claims (1)
等のキヤラクタ情報信号を重ね表示する表示回路
において、 前記キヤラクタ情報信号を一水平走査置きに所
定区間発生するとともに、前記情報信号を発生し
ない走査期間には該情報信号の発生区間に対応し
て前記映像信号に対しブランキングを行うキヤラ
クタ発生手段を用いて重ね表示したことを特徴と
する表示回路。[Claims for Utility Model Registration] In a display circuit that superimposes character information signals such as characters and figures on a CRT screen on which a video signal is displayed, the character information signal is generated for a predetermined period every other horizontal scan, and 1. A display circuit characterized in that during a scanning period in which no information signal is generated, character generation means for blanking the video signal corresponding to the interval in which the information signal is generated is used to display an overlapping display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14510786U JPS6352354U (en) | 1986-09-24 | 1986-09-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14510786U JPS6352354U (en) | 1986-09-24 | 1986-09-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6352354U true JPS6352354U (en) | 1988-04-08 |
Family
ID=31056338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14510786U Pending JPS6352354U (en) | 1986-09-24 | 1986-09-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6352354U (en) |
-
1986
- 1986-09-24 JP JP14510786U patent/JPS6352354U/ja active Pending
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