JPS63146588A - Video signal converter - Google Patents

Abstract

PURPOSE:To realize a compact converter with a low cost by storing video data in a line buffer memory by 2 lines so as to reduce a memory capacity. CONSTITUTION:A control section 6 wires the data 11 of a 1st line counted from the start point of frame by the control of the signal 23, that is the #1 line into a memory 4a and reads the data 1 in the # line by the control of the signal 24 at the speed of a half of the write speed and the read out data 25 is outputted as a data 12 via a switch 5. The data 11 of the #2 line is disregarded. Similarly, in an odd number field, the data 11 of the # line is neglected and the data 11 of the #2 line is written in the memory 4a and then read out, then the data 11 of the #3 line is disregarded and the data 11 of the #4 line is written in the memory 4b and read out, and then outputted as the data 12 via the switch 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal conversion IFC device for converting a high-density video signal into an NTSC video signal.

In this specification, the high-density video signal has a horizontal sweep frequency of 31.5 kHz and is non-interlaced.
interlace) scanning, frame frequency 60 Hz
(Since it is non-interlaced scanning, frame frequency =
This means a video signal with a field frequency of 15.75 kHz, which is converted into an NTSC video signal with a horizontal sweep frequency of 15.75 kHz, interlaced scanning, and a frame frequency of Hz (field frequency 60 Hz), and is used as a high-density video signal. An object of the present invention is to improve a video signal conversion device that converts signals into a format that can be processed and displayed by N'rSC video equipment.

[Traditional skill beast]

FIG. 3 is a block diagram showing the configuration of a conventional video signal conversion device, in which (1) is a frame memory that stores one frame of high-density KGB video signal data;
2) is an NTSC signal generation section, (3) is a control section, and (
11) is high-density type 1 (GB video signal data (horizontal sweep frequency 15.75 kHz x 2 = 31.5 kHz)
Hz).

(12) is NTSC signal type RGB image signal data (horizontal sweep frequency 15.75 kHz), (13) is N
TSC signal, (14) is a read control signal, (15) is a fill-in control signal, and (16) is a memory control signal.

The memory control signal (16) is generated according to the read control signal (14) and the write control signal (15), and controls writing to and reading from the frame memory (11) as well as interlaced scanning in reading.

Writing and reading to frame memory (1) are performed alternately in a time-division manner, so that data (11) and (1)
2) is input/output intermittently. The data (12) in which a predetermined number of bits are output in parallel and intermittently is converted into serial and continuous data (horizontal and vertical (excluding blanking period) is converted into data (13) and output. Also, data (11)
When the data (11) is sent serially and continuously, this data (11) is converted into parallel data every predetermined number of bits and then stored in the frame memory (1) during the fill cycle.

Since the horizontal sweep frequency when displaying data (L2) is A of the horizontal sweep frequency when displaying data (11), data (11) written to the frame memory fil is
) is read out as data (12). In other words, out of two consecutive lines of data (11), only one line of data is the data (11).
12). Of the data (11) stored in the frame memory (1), whether to read data on odd numbered lines or data on even numbered lines is determined by N.
The data is alternately switched for each field of the TSC signal, and data on odd lines is read out in even fields, and data on even lines is read out in odd fields, thereby performing interlaced scanning in the NTSC signal. Control for this interlaced scanning is carried out by a memory control signal (
16).

[Problem that the invention seeks to solve]

Since the conventional video signal converter is configured as described above, it does not have a frame memory for one screen (necessarily, it has a problem in that the required memory capacity is large).

This invention was made in order to solve the above-mentioned problems.
The goal is to construct a video signal conversion device that can convert to an SC type video signal.

[Means to solve the problem]

In this invention, the line buffer memory for one line is
The high-density RGB video signal data is N' rS
We decided to obtain C signal type RGB video signal data, and decided which one line of data to write from among the two lines of high density type 10B video signal data.
Interlace control was performed by changing each field of the C signal.

[Effect]

Since the memory of %Ht for one frame required in the conventional device can be replaced with a buffer memory of capacity for two lines, the memory capacity can be significantly reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and the same reference numerals as in FIG. 3 indicate the same or the same signals. Also, (4a), (4b
) are line buffer memories each storing 1947 minutes of video signals, and temporarily the first line buffer memory (4a
), the second line buffer memory (4b), and (51
can alternately switch back read data (25) and (26) from line buffer memories (4a) and (4b)
A switch that outputs C signal type RGB video signal data (12), (6) is a control unit corresponding to the control unit (3) of the conventional device, and (21) and (23) are high-density RGB, respectively.
The video signal data write control signals (abbreviated as high-density write signals), (22), and (24) are each N.
TSC type RGB video signal data readout control signal (N
(abbreviated as TSC type read signal). - Fig. 2 is an operation time chart showing the operation of each part in Fig. 1. The 21st prisoner is the data (11) in the same figure (Bl is the reading and writing of the line buffer memory (4a) when outputting an even field. (C1 is the signal indicating the R/W cycle of the line buffer memory when outputting an even field, and D) is the signal indicating the R/W cycle of the line buffer memory when outputting an even field. Also, in the same figure, [F] and C1 indicate signals corresponding to T1, C1, and G)1, respectively, when outputting an odd field.

As shown in FIG. 2, in the device of the present invention, data for one line is continuously written and read out continuously, so serial data is input as high-density RGB video signal data (11). Even in the case where one line of data is written, one line of data can be written continuously, and one line of serial data can be continuously output as NTSC signal type RGB video signal data (12). Alternatively, similarly to conventional devices, a predetermined number of bits may be written in parallel, a predetermined number of bits may be read out in parallel, and the NTSC signal type RGB video signal data (12) read out in parallel may be converted to NTSC signal generation. It can also be converted into an NTSC signal (13) in section (2).

The operation of the circuit shown in FIG. 1 will be described below with reference to FIG. When outputting an even field, the control unit (6) outputs a signal (2
Under the control of 3), note down the data (11) of the first line counting from the frame start point, that is, the φ1 line! J
(4a), and then under the control of the signal (24), data (11) divided by 1 line is read out at a speed equal to the writing speed, and this read data (25) is transferred to the switch (5).
) The data (11) on the φ2 line that will be output as data (12) is ignored.

÷ 3 lines of data (11) are written to the memory (4b) under the control of the signal (21), then ◆3 lines of data (11) are read out at a speed equal to the writing speed under the control of the signal (22), This read data (26) is output as data (12) through the switch (51). Similarly, when the even field ends and the odd field begins, as shown in FIG.
1) and memo IJ (
4a), read it, then ignore the φ3 line data (11) and write the 4th line data (11).
) is written into the memory (4b) and then output as data (12) via the readout switch (5).

The data (12) is processed by the NTSC signal generator (21) and output as an NTSC signal (13).

〔Effect of the invention〕

As described above, according to the present invention, video data can be stored in two ways.
Since this is performed using a line buffer memory for each line, the memory capacity can be reduced and a compact and inexpensive device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an operation time chart showing the operation of each part in FIG. 1, and FIG.
The figure is a block diagram showing a conventional device. +21 is an NTSC signal generator, (4a) and (4b) are line buffer memories, respectively, 151 is a switch, (6)
is a controller, (11) is high-density RGB video signal data,
(12) is NTSC signal type RGB video signal data, (1
3) is an NTSC signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] The NTSC system uses a high-density video signal obtained by performing non-interlaced scanning at a horizontal sweep frequency that is twice the horizontal sweep frequency of the NTSC system and a field frequency that is the same as the field frequency of the NTSC system. A video signal conversion device for converting into a video signal, comprising: first and second line buffer memories each capable of storing data for one line of high-density RGB video signal data; A switch that inputs the read data read from the buffer memory and outputs either one of the read data, and sequentially lines 1, 2, 3, 4, 1, 2, 3, 4, for one field of the high-density video signal from the top to the bottom. ..., when outputting an even field, the even numbered lines are ignored and the high density RGB video signal data of the odd numbered lines is stored one line at a time in the first and second line buffer memories. Data is written alternately to the line buffer memory after one line of data has been written to 1/1 of the writing speed.
The read data is read out at a speed of 2, and the read data is controlled to be output from the switch as NTSC signal type RGB video signal data, and when outputting an odd field, the odd numbered lines are ignored, and the even numbered lines are high-density type. RG
The B video signal data is alternately written one line at a time in the first and second line buffer memories, and the line buffer memory in which one line of data has been written is read out at half the writing speed. A video signal conversion device comprising: a control unit configured to control the read data to be output from the switch as NTSC signal type RGB video signal data.