JPH04273685A - Non-interlace conversion circuit for video signal - Google Patents

Abstract

PURPOSE:To reduce the manufacture cost of a device employing the non- interlace conversion circuit. CONSTITUTION:An interlace analog video signal is converted into a digital video signal by an A/D converter 1 and written in a field memory 4 and a line FIFO memory 3 by a timing signal of a write signal generating section 2. Then the voltage is read alternately in the unit of horizontal lines from the field memory 4 and the line FIFO memory 3 based on a timing signal of a read signal generating section 7. Thus, the interlace digital signal is read while being subject to non-interlace processing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-interlace conversion circuit for video signals, and more particularly to a non-interlace conversion circuit for video signals that converts interlaced still image signals into high-definition non-interlace conversion circuits.

0002

2. Description of the Related Art Conventionally, in a non-interlace conversion circuit for video signals, after quantizing the video signal, all the video signals of one frame consisting of two fields are temporarily stored in a frame memory, and Two fields of video signals are alternately read out from the frame memory in units of horizontal lines at twice the period.

0003

[Problems to be Solved by the Invention] However, in the conventional non-interlace conversion circuit for video signals,
It is necessary to use a large number of large-capacity frame memories that can store video signals for frames. Since such a frame memory is expensive, there is a problem in that the manufacturing cost of a device using this type of non-interlace conversion circuit for video signals becomes extremely high.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a non-interlace conversion circuit for video signals that can reduce the manufacturing cost of a device using a non-interlace conversion circuit. do.

[0005]

[Means for Solving the Problems] A non-interlace conversion circuit for video signals according to the present invention includes an A/D converter that quantizes an interlaced analog video signal and converts it into a digital video signal, and a digital video signal. A field memory that stores fields; a line FiFo memory that stores one horizontal line of the digital video signal; and a write signal generator that generates a write timing signal necessary for writing to the field memory and the line FiFo memory. a read signal generating section that generates a read timing signal necessary for alternately reading out the field memory and the line FiFo memory in units of horizontal lines at a speed cycle that is double the cycle of the write timing signal; The present invention is characterized in that it includes a determining section that determines whether a signal is an even field or an odd field, and a switching device that switches and reads out the field memory and the line FiFo memory based on the determination result of the determining section.

[0006]

In the present invention, an interlaced analog video signal is converted into a digital video signal by an A/D converter. This digital video signal is written into a field memory and a line FiFo (first-in-first-out) memory by a write timing signal supplied from a write signal generator. The digital video signals written in the field memory and the line FiFo memory are read out from the field memory and the line FiFo memory horizontally in units of horizontal lines at a speed period twice the write period according to a read timing signal supplied from the read signal generator. They are read out alternately. Thereby, an interlaced digital signal can be read out without interlacing. In this case, the determination section determines whether the digital video signal is an even field or an odd field, and based on the determination result, a switch reads out which of the field memory and the line FiFo memory is read out first. switch appropriately. This results in
At the time of reading, it is possible to prevent the vertical relationship of the horizontal lines of the digital video signal from being reversed.

According to the present invention, a field memory can be used to construct a non-interlaced conversion circuit. This field memory has a smaller capacity and is cheaper than a frame memory. Therefore, it is possible to reduce the manufacturing cost of a device using a non-interlace conversion circuit for video signals.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a video signal non-interlace conversion circuit according to an embodiment of the present invention.

The A/D converter 1 receives an interlace-scanned analog video signal, quantizes it, and converts it into a digital video signal. Line FiFo memory 3 is A/
One horizontal line of the digital video signal output from the D converter 1 is stored. Field memory 4 stores one field of the digital video signal output from A/D converter 1. The synchronization signal processing unit 5 determines whether the digital video signal of the A/D converter 1 is an even field or an odd field. The field counter 6 detects the write signal generator 2 based on the determination result of the synchronization signal processor 5.
and supplies a predetermined signal to the read signal generator 7. The write signal generator 2 supplies a write timing signal to the line FiFo memory 3 and the field memory 4 in response to the signal from the field counter 6. The read signal generator 2 generates a line FiFo according to the signal from the field counter 6.
A read timing signal is supplied to the memory 3 and the field memory 4 at a cycle twice the cycle of the write timing signal, and a switching signal is supplied to the switch 8. Switcher 8
is the line Fi according to the switching signal of the read signal generator 2.
Either the Fo memory 3 or the field memory 4 is read first. The D/A converter 9 receives the digital video signal output from the switch 8 and converts it into an analog video signal. The CRT 10 displays the analog video signal output from the D/A converter 9.

Next, the operation of the above-mentioned video signal non-interlace conversion circuit will be explained. First, an interlaced analog video signal is converted into a digital video signal by an A/D converter 1. This digital video signal is judged whether the field is even or odd in the synchronization signal processing section 5, and is sent to the field memory 4 and line FiFo memory 3 according to the write timing signal supplied from the write signal generation section 2.
are written at the same time. Field memory 4 and line F
The digital video signal written in the iFo memory 3 is read into the field memory 4 at a cycle twice the write cycle by a read timing signal supplied from the read signal generator 2.
and are read out alternately from the line FiFo memory 3 in horizontal frequency units. At this time, from field memory 4, 1
The video signal before the field+1/2 writing horizontal frequency is read out, and then the video signal before the 1/2 writing horizontal frequency is read out from the line FiFo memory 3. In this way, the read frequency is twice the write frequency, and by alternately reading the field memory 4 and the line FiFo memory 3 in units of horizontal frequency, the interlaced digital video signal can be made non-interlaced and read out sequentially. Can be done. However, if the digital video signal is not properly switched between the field memory 4 and the line FiFo memory 3 to read the first line first in even and odd fields, the vertical relationship of the lines will be reversed for each read line. become. Therefore, based on the even-odd signal of the field counter 6, the readout order of the field memory 4 and line FiFo memory 3 is switched line by line by the switch 8. The non-interlaced digital video signal is converted into an analog video signal by the D/A converter 9 and displayed on the CRT 10.

In this embodiment, a field memory is used to configure a non-interlaced conversion circuit.
This field memory has about half the capacity of a frame memory, and is cheaper than a frame memory. Therefore, it is possible to reduce the manufacturing cost of a device using a non-interlace conversion circuit for video signals.

[0013]

As explained above, according to the present invention, after an interlaced analog video signal is quantized into a digital video signal, this digital video signal is transferred to the line FiFo for one horizontal line and the field memory for one field. By simultaneously writing data into the field memory and reading the data from the field memory and the line FiFo memory horizontally in units of horizontal lines at a rate twice the write cycle, the digital video can be read out in a non-interlaced manner. In this way, it is possible to configure a non-interlaced conversion circuit for video signals using field memory.
The manufacturing cost of a device using a video signal non-interlace conversion circuit can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a video signal non-interlace conversion circuit according to an embodiment of the present invention.

[Explanation of symbols]

1; A/D converter 2; Write signal generator 3; Line FiFo memory 4; Field memory 5; Synchronous signal processing section 6; Field counter 7; Read signal generation section 8; Switcher 9; D/A converter 10; CRT

Claims (1)

[Claims] 1. An A/D converter that quantizes an interlaced analog video signal and converts it into a digital video signal, a field memory that stores one field of the digital video signal, and a field memory that stores one field of the digital video signal, and a field memory that stores one field of the digital video signal. a line FiFo memory for storing data; a write signal generation unit that generates a write timing signal necessary for writing to the field memory and the line FiFo memory;
a read signal generating section that generates a read timing signal necessary for alternately reading data from the iFo memory horizontally line by horizontal line at a rate twice the cycle of the write timing signal; a determination unit that makes a determination; and a determination unit that determines the field memory and the line FiF based on the determination result of the determination unit.
o A non-interlace conversion circuit for a video signal, comprising a switch for switching and reading out a memory.