JPH0698275A - Video signal converter - Google Patents

Abstract

PURPOSE:To provide a video signal converter capable of obtaining a high definition output video signal without generating such disturbance to form an image of one line in an image of overlapped lines or to prevent a smooth oblique line from being reproduced when an inputted video signal is a still picture of interlace system. CONSTITUTION:This converter is equipped with video memory 2 provided with capacity of at least one frame of video signal format to be read out, a scanning line structure discrimination circuit 8 which judges whether the scanning line structure of the inputted video signal is of interlace system or non-interlace system, a motion discrimination circuit 9 which judges whether the inputted video signal is a moving image or the still picture, and a memory readout control switching circuit 10 which switches memory readout control circuits 51, 52, and 53 so as to read out the information of the video signals in odd- numbered and even-numbered fields alternately to read out the video signal from the video memory 2 by converting to the one of non-interlace system when it is judged that the inputted video signal is the still picture of interlace system by both discrimination circuits 8, 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal converter for converting an input video signal into a video signal of a different scanning system.

[0002]

2. Description of the Related Art Regarding a video signal conversion apparatus of this type,
There is an invention of JP-A-1-295587 (IPC: H04N 9/00).
This prior art will be described below with reference to the block diagram of FIG. 1 showing the configuration.

In FIG. 1, a video signal input to the apparatus
(Hereinafter referred to as input video signal) is A by the A / D converter 1.
After the / D conversion, it is written in the video memory 2 which can write and read asynchronously with the size of the video signal to be output. A clock generated by a programmable PLL (Phase-Locked Loop) 3 is used as the reference clock for A / D conversion by the A / D converter 1.
The PLL 3 can transmit at an arbitrary frequency in synchronization with the sync signal of the input video signal.

The memory write control circuit 4 outputs a write control signal for the video memory 2 from the synchronizing signal of the input video signal, and the memory read control circuit 5 outputs a video signal to be output from the device.
A read control signal for the video memory 2 is asynchronously generated from a sync signal (hereinafter referred to as an output video signal). Therefore, the input video signal after A / D conversion by the A / D converter 1 is once written in the video memory 2 by the write control signal generated by the memory write control circuit 4, and generated by the memory read control circuit 5. Video memory 2 by read control signal
Read from.

The video signal read from the video memory 2 in accordance with the read control signal is supplied to the programmable interpolation filter 6 and filtered, and then the D / A converter 7 performs D / A conversion.
To be converted. The output from the D / A converter 7 is an output video signal and is a display device corresponding to the video signal format.
(Not shown) to display the image.

Here, an example of a converted image in the case where the input video signal is an interlaced system and is a still image is shown in a schematic view of FIG. Note that FIG. 2 shows a case where two scanning lines are generated from one scanning line as an example of converting the scanning line structure of the input video signal into the scanning line structure of the output video signal.

In the example shown in the schematic view of FIG. 2,
It is assumed that the original image A has one diagonal line. Since the odd field B1 and the even field B2 of the interlaced system signal of the original image A are individually filtered by the programmable interpolation filter 6, interpolation images C1 and C2 obtained by interpolating between the respective fields are obtained. To be When these interpolated images C1 and C2 are viewed as one frame, D
In the original image A, one slanted line becomes a triple slanted line, or a smooth slanted line is not reproduced, which causes interference and is converted into a low-quality video signal. Will end up.

[0008]

As described above, in the conventional video signal converting apparatus, the original image A has one slanted line but is reproduced as a triple slanted line, or a smooth slanted line is not reproduced. However, there is a problem in that it is converted into a low-quality video signal due to the interference of.

The present invention has been made in view of the above-mentioned problems of the prior art. When the input video signal is an interlaced still image, an image of a line in which one line overlaps It is an object of the present invention to provide a video signal conversion device that can obtain a high-quality output video signal without causing any interference such as the occurrence of a broken line or the reproduction of smooth diagonal lines.

[0010]

The first invention of the present invention is as follows:
A clock generator that oscillates at an arbitrary frequency to generate a reference clock in synchronization with the horizontal synchronizing signal of the input video signal, and an A / D converter that A / D-converts the video signal using the reference clock generated by this clock generator. The D converter, the video memory that stores the A / D converted video signal by this A / D converter, and the input and output by asynchronously writing and reading the video signal to and from this video memory A memory control means for scanning and converting a video signal into a video signal of a different format, an interpolating means for interpolating the video signal read from the video memory, and a D / A conversion for the video signal interpolated by the interpolating means. In the video signal conversion device including the / A converter, the video memory has a capacity of at least one frame of the video signal format to be read, and scans the input video signal. A scanning line structure discriminating means for discriminating whether the structure is an interlace system or a non-interlace system, and a motion discriminating means for discriminating whether the input video signal is a moving image or a still image, When both the discriminating means judge that the inputted video signal is an interlaced still image, the video signal of both odd and even fields should be read from the video memory by converting the video signal to the non-interlaced system. Memory control switching means for switching the memory control means so as to alternately read the information.

According to a second aspect of the present invention, in addition to the first aspect, the non-interlace type video signal interpolated by the interpolating means is converted into an interlace type video signal and D
A / A converter performs D / A conversion to obtain standard speed video signal output, and non-interlaced video signals interpolated by interpolating means are D / A converted. And a D / A converter different from the above-mentioned D / A converter that obtains a double-speed video signal output by outputting the output.

[0012]

In the first aspect of the video signal converting apparatus of the present invention,
The memory control switching means alternately reads the even and odd fields of the video signal from the video memory to convert the input video signal into a non-interlaced system, and further the interpolating means performs inter-field interpolation processing.

In the second invention, the non-interlace type video signal interpolated by the interpolating means is converted into the interlace type video signal by the non-interlace / interlace type converting means and further D / A converted. A standard speed video signal output is obtained by D / A conversion by the converter, and the non-interlaced video signal interpolated by the interpolation means is different from the above D / A converter. A D / A converted signal is output by and is output as a double speed video signal.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings showing the embodiments thereof.

FIG. 3 is a block diagram showing an example of the configuration of a video signal converting apparatus according to the present invention. The same reference numerals as those in FIG. 1 referred to in the above description of the conventional example indicate the same or corresponding portions. . First, the first invention will be described.

In FIG. 3, the video signal input to the video signal converter of the present invention (hereinafter referred to as the input video signal) is
After being A / D converted by the A / D converter 1, it is written in the video memory 2. The video memory 2 is different from the conventional example.
It has a capacity of at least one frame of the format of the video signal to be read from the video memory 2. The reference clock for A / D conversion by the A / D converter 1 is a programmable PLL (Phase-Locked) as a clock generation means.
The clock generated by Loop 3 is used, and this programmable PLL 3 is generated from the synchronizing signal of the input video signal.

Reference numeral 4 indicates a memory write control circuit, and reference numerals 51, 52 and 53 indicate memory read control circuits, respectively, all of which function as memory control means.

The memory write control circuit 4 outputs a write control signal for the video memory 2 from the synchronizing signal of the input video signal.
The memory read control circuits 51, 52, 53 asynchronously generate read control signals for the video memory 2 from the synchronizing signals of the video signals to be output (hereinafter referred to as output video signals). However, the memory read control circuit 51 uses an interlace method when the input video signal is a non-interlace method, the memory read control circuit 52 uses an interlace method when the video signal is an interlace method. In addition, it outputs a memory read control signal for a still image.

On the other hand, the input video signal is also given to the scanning line structure discriminating circuit 8 as the scanning line structure discriminating means and the motion discriminating circuit 9 as the motion discriminating means. The scanning line structure determination circuit 8 determines whether the scanning line structure of the input video signal is the interlace system or the non-interlace system. Further, the motion determination circuit 9 determines whether the input video signal is a moving image or a still image.

The judgment result as to whether the input video signal is an interlace system or a non-interlace system, and whether it is a moving picture or a still picture is output as a memory control switching means by the discrimination circuits 8 and 9. It is given to the memory read control switching circuit 10. Memory read control switching circuit 10
Switches so that one of the memory read control signals output from each of the memory read control circuits 51, 52, 53 is applied to the video memory 2 in accordance with the result of the determination made by both the determination circuits 8, 9.

Here, the read method by each of the memory read control circuits 51, 52 and 53 when the signal written in the video memory 2 and read from the video memory 2 is in NTSC format is shown in the schematic diagram of FIG. Show.

Reference numeral A in FIG. 4 indicates the order in which the fields of the non-interlaced video signal are written in the video memory 2, from the first field to the 512th field of frame number 1. Are continuously written, and once the memory write control signal WR is stopped, each frame is similarly written for frame number 2.

Reference numeral B in FIG. 4 indicates the order in which the fields of the interlaced video signal are written in the video memory 2, starting from the first field of the odd field of frame number 1. Up to the 256th field is continuously written, and once the memory write control signal WR is stopped, the even numbered fields 257th to 512th of the frame number 1 are continuously written. And after the memory write control signal WR is stopped again,
Similarly, for frame number 2, writing of each field is performed in the order of odd field and even field.

FIG. 4C shows the reading order of each field from the video memory 2 by the memory read control circuit 51. The memory read control circuit 51 reads each field of the non-interlaced video signal stored in the video memory 2 in the order stored in the video memory 2. That is, from the first field of the frame number 1 of the non-interlaced video signal stored in the video memory 2 to the first field.
Up to 512 fields are continuously read, and once the memory read control signal RD is stopped, each field is similarly read for frame number 2.

FIG. 4D shows the order of reading each field from the video memory 2 by the memory read control circuit 52. The memory read control circuit 52 reads twice each field of the video signal of the interlaced moving image stored in the video memory 2. That is, the first field of the odd field of the frame number 1 of the video signal of the interlaced moving image stored in the video memory 2 is twice, the second field is twice, and the 256th field is twice. After the memory read control signal RD is stopped once after being read repeatedly and repeatedly, the 257th field of the even field of frame number 1 is twice, the 258th field is twice, and so on until the 512th field is twice. One frame of the output video signal is constructed by being repeatedly read out successively.

FIG. 4E shows the reading order of each field from the video memory 2 by the memory read control circuit 53. The memory read control circuit 53 alternately reads each field of the video signal of the interlaced still image stored in the video memory 2 from an odd field and an even field. That is, the first field of the odd field and the first field of the even field of frame number 1 of the video signal of the interlaced still image stored in the video memory 2
257 fields, 2nd field of odd field, 258th field of even field, and so on,
Memory read control signal by reading the 256th field of odd field and the 512th field of even field
After RD is stopped, each field is similarly read for frame number 2.

In other words, since there is no correlation between fields in a video signal of an interlaced moving image, only the information of the video signal of one field is used, and in the video signal of a still image of the interlaced system, the interfield is used. Since there is correlation, conversion to the non-interlaced system is performed using the information of the video signals of both odd and even fields.

The non-interlaced video signal read from the video memory 2 as described above in accordance with the video memory read control signal supplied from the memory read control switching circuit 10 is supplied to the programmable interpolation filter 6 as an interpolation means. After being filtered by the non-interlace / interlace system conversion circuit 11, the signal is converted again into an interlace system signal, and the D / A converter 71 performs D / A conversion.
It is output to a display device corresponding to a converted video signal format (not shown).

Here, an example of a converted image in the case where the input video signal to the video signal conversion device of the present invention is the interlace system and is a still image is shown in the schematic view of FIG. It should be noted that this FIG. 5 is similar to FIG. 2 of the above-mentioned conventional example, and as an example of converting the scanning line structure of the input video signal into the scanning line structure of the output video signal, one scanning line to two scanning lines is converted. The case where it is generated is shown.

In the conversion example by the video signal conversion apparatus of the present invention shown in FIG. 5, after converting to the non-interlaced system signal by using the information of the video signals of both odd and even fields as described above. Since field processing is performed, interpolation is performed within the frame. Therefore, in the video signal converting apparatus of the present invention, a high quality video signal is obtained without causing the interference unlike the conventional example shown in FIG.

Next, the second invention will be described. Figure 3
In the video signal converting apparatus of the present invention of the embodiment shown in FIG. 2, in addition to the above D / A converter 71, another D / A converter 72
Is provided. This D / A converter 72 D / A converts the video signal output from the programmable interpolation filter 6 before converting into the standard speed video signal by the non-interlaced / interlaced system conversion circuit 11 to convert the double speed video signal. It has been output. By providing both the standard speed video signal output and the double speed video signal output as described above, the video signal can be displayed on both the monitor corresponding to the standard speed video signal and the monitor corresponding to the double speed video signal. .

[0032]

As described above in detail, according to the video signal conversion apparatus of the present invention, even if the input video signal is a still image of the interlace system, one line is duplicated. It is possible to obtain a high-definition video signal without causing interference, such as the occurrence of a black line or a slanted line not being reproduced smoothly. Furthermore, by providing two D / A converters, it is possible to display on a monitor that supports standard speed video signals and on a monitor that supports double speed video signals.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a conventional example of a video signal conversion device.

FIG. 2 is a schematic diagram showing an example of a converted image according to a conventional example when an input video signal is an interlaced system and is a still image.

FIG. 3 is a block diagram showing a configuration example of a video signal conversion device according to the present invention.

FIG. 4 is a schematic diagram showing a read method by each of three memory read control circuits targeting an NTSC format video signal in the video signal conversion device of the present invention.

FIG. 5 is a schematic diagram showing an example of a converted image when the input video signal to the video signal conversion device of the present invention is an interlaced system and is a still image.

[Explanation of symbols]

 1 A / D converter 2 Video memory 3 Programmable PLL 4 Memory write control circuit 6 Programmable interpolation filter 8 Scan line structure determination circuit 9 Motion determination circuit 10 Memory read control switching circuit 11 Non-interlaced / interlaced system conversion circuit 51 Memory read Control circuit (for non-interlace) 52 Memory read control circuit (for interlaced video) 53 Memory read control circuit (for interlaced still image) 71 D / A converter (for standard speed output) 72 D / A converter ( (For double speed output)

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[Procedure amendment]

[Submission date] November 18, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0003

[Correction method] Change

[Correction content]

In FIG. 1, a video signal input to the apparatus
(Hereinafter referred to as input video signal) is A by the A / D converter 1.
After the / D conversion, it is written in the video memory 2 which can write and read asynchronously with the size of the video signal to be output. A clock generated by a programmable PLL (Phase-Locked Loop) 3 is used as the reference clock for A / D conversion by the A / D converter 1.
The PLL 3 can oscillate at an arbitrary frequency in synchronization with the sync signal of the input video signal.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Name of item to be corrected] 0022

[Correction method] Change

[Correction content]

[0022] Illustrated at reference numeral A in FIG. 4 is a sequence in which each field of the video signal of the non-interlaced is written in the video memory 2, the first la of the frame number 1
The lines from the IN to the 512th line are continuously written, and once the memory write control signal WR is stopped, the writing of each line is similarly performed for the frame number 2.

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] 0023

[Correction method] Change

[Correction content]

Reference numeral B in FIG. 4 indicates the order in which the fields of the interlaced video signal are written in the video memory 2, starting from the first line of the odd field of frame number 1. Up to the 256th line is continuously written, and once the memory write control signal WR is stopped, the 257th line to the 512th line of the even field of the frame number 1 is continuously written. . Then, after the memory write control signal WR is stopped again, the frame number 2
Similarly, for each line , writing is performed in the order of the odd field and the even field.

[Procedure amendment 4]

[Document name to be amended] Statement

[Name of item to be corrected] 0024

[Correction method] Change

[Correction content]

FIG. 4C shows the reading order of each line from the video memory 2 by the memory read control circuit 51. The memory read control circuit 51 reads each field of the non-interlaced video signal stored in the video memory 2 in the order stored in the video memory 2. That is,
The 512 comes from the first line of the frame number 1 of the video signal of non-interlaced, which is stored in the video memory 2
Until emission is continuously read, once the memory read control signal
After RD is stopped, the same applies to each frame for frame number 2.
The IN is read.

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0025

[Correction method] Change

[Correction content]

FIG. 4D shows the reading order of each line from the video memory 2 by the memory read control circuit 52. The memory read control circuit 52 reads twice each field of the video signal of the interlaced moving image stored in the video memory 2. That is, the first line of the video odd field of the frame number 1 of the video signal of interlaced stored in the image memory 2 twice, the second line
Down is read up to the 256 line twice by one iteratively continuously so that twice, once after the memory read control signal RD is stopped, the even field of the frame number 1 257
The line is twice, the 258th line is twice, and so on.
One line of the output video signal is constructed by repeatedly reading the lines up to twice and continuously.

[Procedure correction 6]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction content]

FIG. 4 (e) shows the reading order of each line from the video memory 2 by the memory read control circuit 53. The memory read control circuit 53 alternately reads each field of the video signal of the interlaced still image stored in the video memory 2 from an odd field and an even field. That is, the 257 La of the first line, the even field of the still picture odd field of the frame number 1 of the video signal of interlaced stored in the image memory 2
In , 2nd line of odd field, 258th line of even field
After reading the 256th line and the 512th line of the even field and once stopping the memory read control signal RD, each field is similarly read for the frame number 2.

[Procedure Amendment 7]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

[0032]

As described above in detail, according to the video signal conversion apparatus of the present invention, even when the input video signal is a still image of the interlace system, one line is duplicated. It is possible to obtain a high-quality video signal without causing any interference or the occurrence of a slanted line not being reproduced smoothly. Furthermore, by providing two D / A converters, it is possible to display on a monitor that supports standard speed video signals and on a monitor that supports double speed video signals.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Naotaka Yasuda 2-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Takahisa Ando 2-18-2 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (2)

[Claims] 1. A clock generation unit that oscillates at an arbitrary frequency in synchronization with a horizontal synchronizing signal of an input video signal to generate a reference clock, and an A / D video signal with a reference clock generated by the clock generation unit. A / D converter for D conversion, a video memory for storing the video signal A / D converted by the A / D converter, and asynchronous writing and reading of the video signal to and from the video memory The memory control means for scanning and converting the input video signal into a video signal having a different format, the interpolating means for interpolating the video signal read from the video memory, and the video signal interpolated by the interpolating means. In a video signal conversion device including a D / A converter for D / A conversion, the video memory includes at least one frame of a video signal format to be read. A scanning line structure discriminating means which has a capacity and judges whether the scanning line structure of the input video signal is the interlace system or the non-interlace system, and whether the input video signal is a moving image or A motion discriminating means for discriminating whether or not it is a still image, and a video discriminating means for discriminating the video signal from the video memory when the both discriminating means judges that the inputted video signal is an interlaced still image. A video signal conversion device, comprising: memory control switching means for switching the memory control means so as to alternately read information of video signals in both odd and even fields to be converted and read. 2. A standard speed video signal output by converting a non-interlaced video signal interpolated by the interpolating means into an interlaced video signal and D / A converting it by the D / A converter. And a non-interlace / interlace system conversion means for obtaining the above, and the D / A conversion for obtaining a double speed video signal output by D / A converting and outputting the non-interlace system video signal interpolated by the interpolating means. The video signal converter according to claim 1, further comprising a D / A converter different from the converter.