JPH02141180U - - Google Patents

Info

Publication number
JPH02141180U
JPH02141180U JP1989050417U JP5041789U JPH02141180U JP H02141180 U JPH02141180 U JP H02141180U JP 1989050417 U JP1989050417 U JP 1989050417U JP 5041789 U JP5041789 U JP 5041789U JP H02141180 U JPH02141180 U JP H02141180U
Authority
JP
Japan
Prior art keywords
signal
screen
generation circuit
display device
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1989050417U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989050417U priority Critical patent/JPH02141180U/ja
Publication of JPH02141180U publication Critical patent/JPH02141180U/ja
Pending legal-status Critical Current

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  • Studio Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、この考案の多画面デイスプレイ装置
の一実施例を示す概略回路構成図、第2,3図は
、それぞれ第1図に示した無信号検出回路の回路
図及び回路各部の信号波形図、第4,5図は、そ
れぞれ従来の多画面デイスプレイ装置の一例を示
す概略回路構成図及び回路各部の信号波形図であ
る。 3……切り替え回路、11……バツフアメモリ
、12……画像メモリ、16……アドレス制御回
路、17……親画面用同期分離回路、18……子
画面用同期分離回路、21……多画面デイスプレ
イ装置、22……無信号検出回路、23……同期
切り替え回路、24……黒信号発生回路。
FIG. 1 is a schematic circuit configuration diagram showing an embodiment of the multi-screen display device of this invention, and FIGS. 2 and 3 are circuit diagrams of the no-signal detection circuit shown in FIG. 1, and signal waveforms of various parts of the circuit, respectively. 4 and 5 are a schematic circuit configuration diagram and a signal waveform diagram of each part of the circuit, respectively, showing an example of a conventional multi-screen display device. 3... Switching circuit, 11... Buffer memory, 12... Image memory, 16... Address control circuit, 17... Synchronization separation circuit for main screen, 18... Synchronization separation circuit for child screen, 21... Multi-screen display Device, 22...No signal detection circuit, 23...Synchronization switching circuit, 24...Black signal generation circuit.

Claims (1)

【実用新案登録請求の範囲】 (1) 子画面用映像信号をその同期信号に間欠同
期しつつ、数ラインを間引いてバツフアメモリに
書き込み、画像メモリに転送したのち、親画面用
映像信号に含まれる同期信号に同期しつつ、画面
メモリから読み出し、親画面の一部に子画面とし
て挿入表示する多画面デイスプレイ装置であつて
、子画面用映像信号が無信号であることを検出す
る無信号検出回路と、この無信号検出回路の検出
出力を受け、親画面用映像信号の同期信号を前記
バツフアメモリへの書き込み同期用に振り替え供
給する同期切り替え手段を具備してなる多画面デ
イスプレイ装置。 (2) 前記無信号検出回路の検出出力を受け、親
画面に対する子画面の挿入表示を停止する子画面
消去手段を設けてなる請求項1記載の多画面デイ
スプレイ装置。 (3) 前記無信号検出回路の検出出力を受け、無
信号とされた子画面用映像信号に代わる代用子画
面信号をバツフアメモリに供給する代用子画面信
号発生回路を設けてなる請求項1記載の多画面デ
イスプレイ装置。 (4) 前記代用子画面信号発生回路は、黒信号を
発生する黒信号発生回路であることを特徴とする
請求項3記載の多画面デイスプレイ装置。 (5) 前記代用子画面信号発生回路は、静止画信
号を発生する静止画信号発生回路であることを特
徴とする請求項3記載の多画面デイスプレイ装置
。 (6) 前記代用子画面信号発生回路は、文字信号
を発生する文字信号発生回路であることを特徴と
する請求項3記載の多画面デイスプレイ装置。
[Claims for Utility Model Registration] (1) While intermittently synchronizing the video signal for the sub-screen with its synchronization signal, some lines are thinned out, written to the buffer memory, transferred to the image memory, and then included in the video signal for the main screen. A multi-screen display device that reads out a screen memory in synchronization with a synchronization signal and inserts and displays it as a sub-screen in a part of a main screen, the no-signal detection circuit detecting that there is no signal of a sub-screen video signal. and a synchronization switching means for receiving the detection output of the no-signal detection circuit and redirecting and supplying the synchronization signal of the main screen video signal to synchronization of writing to the buffer memory. 2. The multi-screen display device according to claim 1, further comprising a child screen erasing means for receiving the detection output of the no-signal detection circuit and stopping insertion and display of the child screen with respect to the main screen. (3) A substitute small screen signal generation circuit is provided which receives the detection output of the no-signal detection circuit and supplies a substitute small screen signal to the buffer memory in place of the small screen video signal which is determined to be no signal. Multi-screen display device. (4) The multi-screen display device according to claim 3, wherein the substitute small screen signal generation circuit is a black signal generation circuit that generates a black signal. (5) The multi-screen display device according to claim 3, wherein the substitute small screen signal generation circuit is a still image signal generation circuit that generates a still image signal. (6) The multi-screen display device according to claim 3, wherein the substitute small screen signal generation circuit is a character signal generation circuit that generates a character signal.
JP1989050417U 1989-04-28 1989-04-28 Pending JPH02141180U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989050417U JPH02141180U (en) 1989-04-28 1989-04-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989050417U JPH02141180U (en) 1989-04-28 1989-04-28

Publications (1)

Publication Number Publication Date
JPH02141180U true JPH02141180U (en) 1990-11-27

Family

ID=31568941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989050417U Pending JPH02141180U (en) 1989-04-28 1989-04-28

Country Status (1)

Country Link
JP (1) JPH02141180U (en)

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