JPS582039U - clock receiver circuit - Google Patents
clock receiver circuitInfo
- Publication number
- JPS582039U JPS582039U JP9368981U JP9368981U JPS582039U JP S582039 U JPS582039 U JP S582039U JP 9368981 U JP9368981 U JP 9368981U JP 9368981 U JP9368981 U JP 9368981U JP S582039 U JPS582039 U JP S582039U
- Authority
- JP
- Japan
- Prior art keywords
- clock
- input
- output
- receiver circuit
- clock receiver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Exchange Systems With Centralized Control (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、本考案のクロック受信回路の実施例のブロッ
ク図、第２図は第１図の回路の作用説明図である。
１・・、曲フリップ・フロップ、２・・聞フリップフロ
ップ、３・・・・・・レジスタ、４・・・・・・ＥＯＲ
ゲート、５・・・・・・セレクタ（ＳＥＬ）。FIG. 1 is a block diagram of an embodiment of the clock receiving circuit of the present invention, and FIG. 2 is an explanatory diagram of the operation of the circuit of FIG. 1. 1... Song flip-flop, 2... Listening flip-flop, 3... Register, 4... EOR
Gate, 5...Selector (SEL).
Claims (1)
おいて、一方は入出力が反転せす、他方は入出力が反転
するところの入出力が相互接続された２個のフリップ・
フロップを設け、一方のフリップ会フロップのセットゲ
ートに０系のクロックを、他方に一系のクロックを入力
し、その出力を監視することで片系のクロックパルスの
障害・時に障害クロック系を判別し、２系のクロックの
うち、正常系のクロックのみを受信するように構成みた
ことを特徴としたクロック受信回路。９In a circuit that receives clocks from two systems of clock circuits, one has two flip-flops whose inputs and outputs are interconnected, one inverting the input and output, and the other inverting the input and output.
A flop is provided, and the 0 system clock is input to the set gate of one flip flop, and the 1 system clock is input to the other, and by monitoring the output, it is possible to identify a faulty clock system when there is a failure in the clock pulse of one system. A clock receiving circuit is characterized in that it is configured to receive only the normal clock among the two clock systems. 9
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9368981U JPS582039U (en) | 1981-06-26 | 1981-06-26 | clock receiver circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9368981U JPS582039U (en) | 1981-06-26 | 1981-06-26 | clock receiver circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS582039U true JPS582039U (en) | 1983-01-07 |
Family
ID=29888651
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9368981U Pending JPS582039U (en) | 1981-06-26 | 1981-06-26 | clock receiver circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS582039U (en) |
-
1981
- 1981-06-26 JP JP9368981U patent/JPS582039U/en active Pending
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