JPS61113198A - Shift register circuit - Google Patents

Abstract

PURPOSE:To prevent an erroneous action due to the penetration of data by setting the transmission direction of a clock signal and inversion clock signal, both of which are impressed to gates of respective transistors, to that reverse to a data shift direction and delaying sequentially signals impressed to the gates of the transistors. CONSTITUTION:The direction where the clock signal and its inversion clock signal from a clock generator are transmitted is that for orienting from the right to left side in the figure, and is set reverse to the data shift direction (direction shifting from the right to left in such a way that to the 1st unit shift register S1 from the data input side by each clock cycle, to unit shift register S2 from the 1st unit shift registers S1,...). Moreover, whenever the clock signal or inversion clock signal passes through respective inverters 11-16, it is delayed by the prescribed time in sequence.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a shift register circuit, which is used, for example, in a drive circuit for a liquid crystal display device, and is configured to perform shift register circuits by combining outputs of predetermined bits (for example, 64 bits) read into the shift register circuit. The present invention relates to a shift register circuit that controls the display of each pixel area in a liquid crystal.

BACKGROUND ART FIG. 3 shows a conventional example of this type of shift register circuit, in which Sl+ is a first unit shift register,
A transistor 5 to whose gate a clock signal is applied
1. The inverter 61 is composed of a transistor 52 to which an inverted clock signal obtained by inverting the clock signal by an inverter 43 is applied to the gate thereof, and an invert clock 2. The output of the first unit shift register SI□ is taken as DIZ. Served. Further, SI2 is a second unit shift register, and is composed of a transistor 53 to which a clock signal is applied to its gate, an inverter 63, a transistor 54 to which the above-mentioned inverted clock signal is applied to its gate, and an inverter 64. , the output of the second unit shift register S1□ is taken out as DI4. Note that 41 and 42 are inverters constituting a hash sofa circuit inserted between the shift register circuit and a black/7 digit generator (not shown).

In such a shift register circuit, when the clock signal becomes high level in a certain clock cycle, the transistor 51 of the first unit shift register Sz is turned on, so that data rlJ is transferred from the data input terminal to the transistor 51. Suppose that the signal is transmitted to the output side of the inverter 61, further inverted by the inverter 61, and transmitted to the Dl1 point as data "0".

Subsequently, when the clock signal becomes low level in the latter half of the clock cycle, the high level inverted clock signal inverted by the inverter 43 is applied to the gate of the transistor 52 of the first unit shift register S I +. The data "0" present at the Dl1 point is transmitted to the output side of the transistor 52, and is further inverted by the inverter clock 2 to be transferred to the 012 point, that is, the first unit shift register Sl+. Data "1" is transmitted to the output side of.

In this way, during one clock cycle, predetermined data (data "1" in the above example) is shifted from the data input side to the output JD,□ of the first unit shift register Sl+.

Then, in the next clock cycle, the data "1" present in □ on the output side of the first unit shift register
is shifted to the output side DI4 of the adjacent second unit shift register SI2, while the next data (for example, data "0") is transferred to the output side DI2 of the first unit shift register SI2.
) is shifted from the data input side.

Thereafter, the operation is repeated during a predetermined clock cycle so that predetermined bits of data are sequentially loaded into adjacent unit shift registers.

However, in such a shift register circuit, in particular, the number of shift registers is large (if used, the capacitance of the gate increases, and as a result, the edge portions of the clock signal and the inverted clock signal are rounded, as shown in FIG. 4, for example). As shown in FIG.

In such a case, even after the clock signal becomes equal to or higher than the threshold voltage 71 of the transistors 51, 53, . . . operated by the clock signal, the period T continues.
During this period, the inverted clock signal is still applied to the transistors 52, 54,
... is higher than the threshold voltage 12, and during this transition period T, each transistor 51,
52, 53, 54, . There is a possibility that the signal may penetrate to the unit shift register Sl□ and cause malfunction (causing so-called racing).

In order to prevent the clock signal and its inverted clock signal from becoming dull, which causes such malfunctions, the inverter 41
, 42 and 43 had to be considerably increased in driving capacity.

Problems to be Solved by the Invention The present invention has been made to solve the above problems.
In the shift register circuit described above, the transmission direction of the clock signal and inverted clock signal applied to the gate of each transistor is reversed to the data shift direction, and the clock signal and inverted clock signal are sequentially delayed. Based on this idea, data is prevented from passing through (so-called racing) due to simultaneous conduction of each transistor when the level of a clock signal changes.

In this case, as the delay means, an inverter having a direction opposite to that of the inverter provided in the unit shift register is connected between the gates of each transistor (that is, an inverter having a direction opposite to that provided in the unit shift register is connected to each transistor). ) reduces the driving load of the inverter,
Even if the driving capacity is reduced by that much, it is possible to reliably prevent the above-mentioned data from passing through.

Means for Solving the Problems According to the present invention, a transistor controlled by a clock signal, an inverter, a transistor controlled by an inverted clock signal obtained by inverting the clock signal,
In a shift register circuit, a plurality of unit shift registers formed by sequentially connecting inverters in series are connected in series, and predetermined data is sequentially shifted to adjacent unit shift registers for each cycle of the clock signal,
The transmission direction of the clock signal and the inverted clock signal applied to the gate of each transistor in each unit shift register is reversed to the shift direction of the data, and the clock signal and the inverted clock signal applied to the gate of each transistor in each unit shift register are reversed. A shift register circuit is provided that sequentially delays signals.

Further implementation of the present invention! According to Ikou-sama, as means for sequentially delaying the clock signal and the inverted clock signal, there is provided a shift register circuit in which an inverter having a direction opposite to that of the inverter provided in the unit shift register is connected between the gates of each of the transistors. is provided.

Effect: According to the above configuration, the clock signal or its inverted clock signal transmitted in the direction opposite to the shift direction of the date and time is as follows.
Since it is delayed by a predetermined time and transmitted sequentially to the gate connection point of each transistor, the rising or falling portion of the clock waveform at each gate connection point is shifted in time. Even if there is a slight change in the area, each transistor is prevented from turning on at the same time during such a transition.
Data leakage will no longer occur.

Further, according to the configuration of the above embodiment, since the inverters with opposite directions are divided and arranged so as to correspond to each transistor, the driving load of the inverters with opposite directions is reduced, and the driving capacity thereof is reduced accordingly. Even if the clock waveform is applied to the gate of each transistor, it is possible to reduce the rounding of the clock waveform, and even with such an inverter with a small driving ability, the above-mentioned data penetration can be reliably prevented.

Embodiment FIG. 1 shows a first embodiment of a shift register circuit according to the present invention. A shift register circuit consisting of second and third unit shift registers S+, Sz, and S3 is shown.

These unit shift registers themselves have the same configuration as the conventional example described above, and 21, 23, and 25 are transistors to which a clock signal is applied to their gates;
, 33, and 35 are inverters; 22, 24, and 26 are transistors to which an inverted clock signal is applied; and 32, 34, and 36 are inverters.

A clock signal from a clock generator (not shown) is first inverted through the inverter 11 and applied to the gate of the transistor 26, and then re-inverted through the inverter 12 (as the original clock signal) and applied to the gate of the transistor 25. The inverter 13 is
, 14, 15, and 16, and is applied to each gate of each transistor 24, 23, 22, and 21 while being repeatedly inverted and re-inverted.

That is, in the present invention, the direction in which the clock signal from the clock generator and its inverted clock signal are transmitted is from right to left in FIG. from the end to the first unit shift register SI and then from the first unit shift register S1 to the 82 unit shift register S
2... (from left to right), and furthermore, the clock signal or inverted clock signal is applied to each inverter 11, 12, 13, 14.
, 15, and 16, the signal is sequentially delayed by a predetermined time.

In the embodiment shown in FIG. 1, the delay means is provided between the gates of each transistor, that is, between CbC5, c,
Inverters for inverting or re-inverting the clock signal are connected between C, C, c, C3, 03C2, and CzC+, but the additional effect of the sagging configuration is particularly noteworthy. This will be explained later.

However, the present invention is not necessarily limited to such a configuration. For example, a clock signal may be sequentially applied to each gate of the transistors 25, 23, and 21 while being delayed by an appropriate delay circuit, and an inverted clock signal may be inverted by an inharter. may be sequentially applied to the gates of transistors 26, 24, and 22 while being delayed by the same delay circuit.

FIG. 2 is a timing chart showing a situation in which a clock signal and data are sequentially transmitted in the shift register circuit according to the present invention shown in FIG.

That is, the clock signal inputted from a predetermined clock generator is first inverted by the inverter 11 and then delayed for a predetermined time, so that at the gate of the transistor 26, that is, at point 06, the waveform becomes as shown in FIG. 2, C8.

This inverted clock signal is then applied to inverter 12.
The transistor 25 is inverted again and further delayed for a predetermined time.
At the gate of , that is, at point C3, the waveform becomes as shown in FIG.
22 and 21, namely C4, C3, Ct
, and C8 point respectively in Figure 2 Ca, C:
+, C2, and c, and in short, a predetermined time lag occurs between the rising or falling portions of each clock waveform 01 to c6.

Here, during 3 clock cycles, data from the data input side is rL, H, LJ (i.e. "0°1, OJ
) shall be entered.

Then, when the clock at point 01 rises to a high level in its first cycle, the transistor 21 is turned on, and the first data rLJ passes through the transistor 21 and is further inverted by the inverter 31, causing the point D1 to become high level. .

In this case, even if the rising edge of the clock at point 01 and the falling edge of the clock at point 02 become distorted on the board, there is a predetermined distance between the rising edge of the clock at point 01 and the falling edge of the clock at point 02. There is a time lag, and the fourth example of the conventional example above
Period T as shown in the figure (i.e. transistor 21
and 22 are turned on at the same time).

Next, when the clock at point 02 rises in the latter half of the first cycle, the transistor 22 turns on, and the data rHJ at the three points passes through the transistor 22 and is transferred to the inverter 3.
2, and the data rLJ is transmitted to the output side of the first unit shift register SI, that is, to the point D2. At this time, the clock at point 01 is completely low level.
l D Data at two points will not pass through the adjacent second shift register s2.

Then, when the clock at the 01 point rises to a high level in the first half of the second cycle, the transistor 23
is turned on and the data rLJ at the D2 point is transferred to the D3 point.
When the 04-point clock rises in the latter half of the second cycle, the transistor 24 turns on and the 1-point data rHJ is transmitted to the output side of the second unit register s2, that is, D4. The data is transmitted to the point as data rLJ.

On the other hand, in the first unit register S1, when the second cycle of the clock at point 01 rises, the second data r
HJ rises and is transmitted to point D2 as data rLJ, and when the clock at point Ct rises in the second half of the second cycle, data rLJ at point D1 is transmitted to point D2 as data rHJ.

After 3 clock cycles in this way,
1st. second and third unit shift registers St,
S2, and the output side D2 of S.

Three pieces of data rL and H are placed at points D4 and D6, respectively.
, LJ (rO, 1, OJ) are transmitted.

As mentioned above, there is a predetermined time lag between the rising or falling portions of each clock waveform at points C1 to C06, and even if these rising or falling portions become dull due to this, each transistor There is no chance of data leakage due to simultaneous conduction.

Next, as shown in the embodiment of FIG.
5, 24, 23, 22, and 21, that is, Cb, Cs, C4, Ci, Cz, and C1 points, an inverter 1 for clock inversion or re-inversion is used as a means for sequentially transmitting the data with a predetermined delay.
1, 12.

The additional effects of using 13, 14, 15, and 16 will be explained.

By the way, in the above conventional example shown in FIG. On the other hand, the output side of the inverter 43 serves as a common output section for supplying an inverted clock signal to the gates of the respective transistors 52, 54, .

In such a configuration, especially when many shift registers are used, the gate capacitance of the transistor increases, and there is a risk that the rising or falling portions of the clock signal and the inverted clock signal will be blunted, causing data to pass through. To reduce the distortion of such a lock signal and its inverted clock signal, inverters 41, 42,
As mentioned above, the driving capacity of the motors 43 and 43 must be considerably increased.

On the other hand, as shown in FIG. 5 (reference example), inverters 45, 46, 47, 48, .
. . , and apply the clock signal on the output side of the buffer circuits 41 and 42 to the gate of the transistor 51, and apply the inverted clock signal obtained by inverting the clock signal by the inverter 45 to the gate of the transistor 52, and further apply the inverted clock signal to the gate of the transistor 52. If a corresponding inverter is assigned to each transistor, such as applying a clock signal obtained by re-inverting the clock signal by the inverter 46 to the gate of the transistor 53, each inverter 41, 42
, 45, 46, 47, 48, . The simultaneous conduction period of the transistors in the transistors is shortened, and data leakage can be prevented.

The embodiment shown in FIG. 1 above adopts the concept of arranging the inverters for clock inversion and re-inversion by dividing them so as to correspond to each transistor when configuring the delay means. The driving load on each of the inverters 11 to 16 for clock inversion and re-inversion is reduced, and even if the driving capacity is made considerably small, the clock signal (or its inverted clock signal) applied to the gate of each transistor is reduced. However, in combination with the time lag between the respective clock signals (or their inverted clock signals) as described above, this reliably prevents data racing during the transition as described above.

Effects of the Invention According to the present invention, the clock signal applied to the shift register and its inversion are
There is no risk of data racing (racing),
Malfunctions based on this can be reliably prevented.

[Brief explanation of the drawing]

1 is a circuit diagram showing one embodiment of a shift register circuit according to the present invention; FIG. 2 is a timing chart showing a situation in which a clock signal and data are sequentially transmitted in the circuit of FIG. 1; 3 is a diagram showing an example of a shift register circuit in the prior art, and FIG. 4 is a diagram illustrating a so-called transient situation in which the level of a clock signal and its inverted clock signal changes in the circuit of FIG. 3. , FIG. 5 is a diagram showing a shift register circuit as a reference example for deriving the circuit of FIG. 1. (Explanation of symbols) 11, 12, 13, 14, 15, 16...
Inverter, 21 , 22 , 23 , 24 , 25
, 26...transistor, 31, 32, 33,
34, 35, 36...inverter, 41, 42
, 43... Inverter, 51 , 52 , 53 ,
54...Transistor, 61, 62, 63, 6
4... Inverter, 45, 46, 47, 48.
...Inverter.

Claims (1)

[Claims] 1. A transistor controlled by a clock signal;
A plurality of unit shift registers each consisting of an inverter, a transistor controlled by an inverted clock signal obtained by inverting the clock signal, and an inverter are connected in series, and predetermined data is transmitted every cycle of the clock signal. In a shift register circuit configured to sequentially shift data to adjacent unit shift registers, the transmission direction of the clock signal and the inverted clock signal applied to the gate of each transistor in each unit shift register is opposite to the shift direction of the data. A shift register circuit characterized in that the clock signal and the inverted clock signal applied to the gates of the respective transistors are sequentially delayed. 2. A patent claim characterized in that, as means for sequentially delaying the clock signal and the inverted clock signal, an inverter having a direction opposite to that of the inverter provided in the unit shift register is connected between the gates of each of the transistors. The shift register circuit according to item 1.