JPS62181524A - Dynamic frequency division circuit - Google Patents

Abstract

PURPOSE:To obtain a 'one over an odd number' frequency division circuit while keeping the advantages of two-phase clock control by providing a bypass circuit transferring a data to the next stage by clock under a prescribed condition while a clock controlled inverter (C-INV) is turned off by the control clock. CONSTITUTION:A bypass circuit (f) is connected in parallel with a C-INV(I3) in a conventional frequency division circuit, a FET 10 selects the output level of a C-INV(I2) and a transmission gate T1 uses a clock theta and outputs an inverted output of the C-INV(I2). The C-INV(I3) is turned off at timings t4, t10, t16, no write to a node D is applied but since the level of a node C is at a high level, the FET 10 is turned on. The timing writing by C-INV (I3, I4) is quickened by a half clock respectively at the timings t4, t10, t16, the operating period of a closed loop circuit is decreased by one clock to form the 'one over an odd number' frequency division circuit (1/3 frequency division circuit).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic frequency divider circuit configured by complementary connection of insulated gate field effect transistors.

[Conventional technology]

FIG. 8 shows a clock-controlled inverter (hereinafter abbreviated as C-NV) with four stages (FH! ~ (FHT)) using a two-phase clock, which is constructed by complementary connection of insulated field effect transistors (FHT). 4) and CMOS inverter 1
1, which was constructed by continuously connecting the stage (5) and feeding back the output of this inverter α to the 0 - stage NV (4) of the first stage.
/4 minute circuit. In the figure, Vcc indicates a positive power source, and Vsa indicates a negative source. FET Ill ~ (8) is the F German T for clock input, F E T ill ~ ] 4)
The clock signals ψ and 〆 are input to the gates of FET +51 to (8), respectively, in opposite phases, and the gates of the P-channel FETs of the odd-numbered C-Engineering NV (Engineering II Eng. 8) are input. In this case, the f-th clock signal is input to the gate of the P-channel FET of the even-numbered stage NV (21-4), which is opposite to the clock signal input to the gate of the P-channel FET, and the gate of the N-channel FET is The same applies to gates.

FIG. 4 is an operating waveform diagram of the circuit in FIG. 8, p, 7p
is the clock signal, and A-B-0-D and E are the 8th clock signals, respectively.
The operating waveforms at nodes A-B-0 and DE of the circuit shown in the figure are shown.

Even-numbered timing (t, , t4++++)
Even-numbered C-engine Nv (engine 2.engine 4) is ON in VC
The adjacent C-engine NV works as an inverter, and the odd number +
7) O-INV (Il, engineering) is turned OFF.

At this time, the level is written at nodes A-0-E, and the level is maintained at node B-D. As a result, as shown in Figure 4, the level of each node (A-E) is reduced by half. This occurs sequentially in synchronization with the rising and falling edges of the clock every clock, and the frequency is divided by 174.

[Problem that the invention seeks to solve]

The above-mentioned conventional system has an even number of stages connected in series.
Since V adjusts the level every half clock,
It is possible to construct a circuit for 13 minutes for the number of pieces, but "1 for an odd number"
There was a problem that it was not possible to configure the same number of minutes.

The object of the present invention is to obtain an odd-numbered lJ frequency divider circuit in a dynamic frequency divider circuit obtained by cascading C-engine NVs.

[Means for solving problems]

The present invention is provided with a bypass circuit in which data is transferred to the next stage by the clock under certain conditions when the C-engine NV is turned off by the tllilla clock and data is not transferred to the next stage. .

[Effect]

The bypass circuit in the present invention selects and inverts the input level of one of the C-engine NVs and outputs it to the C-engine NV at the clock timing when the O-engine NV turns OFF.

〔Example〕

Fig. 1 shows an embodiment of a frequency dividing circuit constructed using the present invention, in which a bypass circuit f (within the point area) is connected in parallel to the conventional frequency dividing circuit. Connected, C-
Output level of INV (engineering 3) i F E T (101
is selected, and the transmission gate T□ clock ψ
Outputs the inversion of the output of 〇-INV (Step 2).

FIG. 2 is an operational waveform diagram of the circuit of FIG. 1, and shows timings t4. At t1°+t
LOL turns ON. Since the transmission gate TI is also ON at the timing when the clock φ is at the high level, a low level similar to the inversion of the level at the node C is written to the node. C-INV (engineering 4) is at timing 1. ．． 1□.

, t. It is ON at node WYc, and in response to the inversion of the level of the node, the level of the node WYc is inverted (
High level)Write. In this way, the timing t+*
At tlo + t16, the writing timing is advanced by half a clock at C-En NV (Step 8゜), the operating period of the closed loop circuit is shortened by one clock, and the "1/8" frequency divider circuit (l/8 min) is shortened by 1 clock. circuit).

FIG. 7 shows a clock-controlled A-type inverter based on e, and FIG. 8 shows a clock signal φ of the circuit shown in FIG.

The operating waveform A-Bi at the node A-B due to φ is shown. FIG. 5 shows the case where the present invention is included, and FIG. 6 shows the operating waveforms in a setting where the bypass circuit f operates in place of C-N only when both node A1 clock signals ψ are at high level. It is a diagram. As can be seen by comparing FIGS. 6 and 8, this method takes advantage of the fact that at timings p, , p, there is a difference of half a clock in the inversion of the level of node A.

The present invention is effective when the C-engineering NV is two or more stages,
By changing the bypass circuit f, it may be turned ON when the node C is at a low level, or it may be configured in parallel with the C-engine NV of the case, odd-numbered stages, and even-numbered stages.

By devising a circuit for selecting the output level in the preceding stage of the bypass circuit f, it is possible to construct a frequency dividing circuit that can vary the output level to either 1 divided by an odd number or 1 divided by an odd number.

〔Effect of the invention〕

The present invention makes it possible to obtain an odd-numbered lJ frequency divider circuit while retaining the advantages of two-phase clock control.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a frequency dividing circuit according to an embodiment of the present invention, FIG. 2 is an operation waveform diagram of FIG. 1, FIG. 8 is a circuit diagram showing a conventional frequency dividing circuit, and FIG. is the operating waveform diagram in Fig. 8,
FIG. 5 is a circuit diagram showing a clock-controlled inverter with a bypass circuit, FIG. 6 is an operating diagram of FIG. 5, and FIG.
The figure shows a circuit diagram of a clock-controlled inverter, and Figure 8 shows the circuit diagram of a clock-controlled inverter.
The operating waveform diagram of FIG. 7 is shown. ψ, 〆 is the control clock signal 1. Vaa and Vsa are positive power supply and negative power supply respectively, 11) to (8) are F for clock input.
ET, A-B-0-D-E are the nodes of each inverter,
4 is a clock-controlled inverter, 5 is a CMOS inverter, f is a bypass circuit, (+ol rl level selection FET, TI is a transmission gate. The same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a dynamic frequency dividing circuit formed by continuously connecting an odd number of inverters to form a closed loop, the circuit comprises at least a first bypass circuit and first, second, and third inverters, and the first inverter is connected to the first inverter. The second and eighth inverters each include a first FET and a second FET between the second and third complementary inverters and the first power source and the second power source, respectively. A control clock is inputted in opposite phase to the first and second FETs of the second and third inverters, respectively, and the first FET of the second inverter has the following configuration:
The reverse phase of the clock input to the first FET of the eighth inverter is input, and the first bypass circuit selects one of the output levels of the second inverter. The second selection circuit selected by the first selection circuit in synchronization with a clock at a clock level at which the first selection circuit and the eighth inverter do not operate.
a circuit that inverts the output level of the inverter and outputs it to the output of the third inverter;
A dynamic frequency divider circuit, characterized in that a bypass circuit is connected in parallel with the third inverter.