JPS62248312A - Serial-parallel conversion circuit - Google Patents

Abstract

PURPOSE:To reduce the number of elements, and to minimize an area occupied by the elements from the standpoint of the constitution of an integrated circuit, by using a D type latch circuit as a circuit that latches the output of a shift register in which the D tyre latch circuits are connected in multistage, and two clock signals having antiphases in each other as the clock signal for the shift register. CONSTITUTION:When data of four bits are inputted/outputted, a circuit is constituted of the shift register consisting of eight D type latch circuits(LA)2-9 in the first group 101, and four LAs 13-16 in the second group 102. The data is inputted to the input terminal D of the LA2 in the first group 101, and to the clock input terminal of the LA at the odd-th number of stage connected in multistage in the first group, the second clock CK1 having the antiphase of a signal CK2 is inputted, and to each clock signal input terminal of the LAs in the second group, a parallel outputting clock signal CK3 is inputted commonly and simultaneously. As a result, each LA receives an output from each output terminal of the LA at the even-th number of stage in the first group corresponding one to one at each input terminal, and it is possible to output the data simultaneously from each output terminal of each LA in the second group.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a serial-to-parallel conversion circuit.

[Conventional technology]

Conventionally, this type of serial-to-parallel conversion circuit has a shift register in which multiple stages of D-type flip-flops (hereinafter referred to as FFs) are connected in series, and an FF for output parallel to the output of each stage of the shift register. Ta.

FIG. 4 is a block diagram showing an example of a conventional serial-to-parallel conversion circuit in the case of 4 bits.

When a clock signal is input to the serial transmission clock signal input terminal 36 of the FFs 32, 33, 34, and 35, the serial data input from the data input terminal 31 is transmitted to the FFs 32 to 35 in series. Clock signal input terminal 41 for parallel output
When a clock signal is input to , the data of FF32 to 35 is transferred to and held in FF37.
It is output to parallel output terminals 42, 43, 44 and 45.

FIG. 5 is a circuit diagram showing an example of a detailed circuit of each FF shown in FIG. 4.

Now, if the clock signal input to the clock signal input terminal CK is low (hereinafter referred to as low), the gate circuit 52
．． 57 is conductive, gate circuits 54 and 59 are non-conductive,
Input data from the terminal Q is transmitted to the inverter circuits 53 and 58, and the previous data is transmitted to the output terminal Q from the inverter circuit 5.
5.56 and the feedback circuit of the gate circuit 57, and does not change without being affected by input data.

Next, when the clock signal input to the tarlock signal input terminal CK becomes high (hereinafter referred to as H), the gate circuit 52
．． 57 is non-conductive, gate circuits 59 and 54 are conductive, and the input data is transmitted to the output terminal Q through the inverter circuit 55 while retaining the previous data by the feedback circuit of the inverter circuits 53 and 58 and the gate circuit 59. In other words, input data is transferred at the rising edge of the clock signal.

FIG. 6 is a timing chart showing the relationship between the output signal from the terminal Q of each FF in FIG. 4, the serial transfer clock signal, and the parallel output clock signal.

[Problem that the invention seeks to solve]

The conventional serial-to-parallel conversion circuit described above has an FF for serially transmitting data and an FF for parallel output, so it occupies a large area due to the large number of elements in the integrated circuit configuration, and consumes a large amount of power. The disadvantage is that it is large.

[Means for solving problems]

The serial-to-parallel conversion circuits of the present invention include 2n pieces of the first group (n is 1
a shift register configured by multi-stage connection of LAs (an integer greater than or equal to A first clock signal is input to the clock input terminal of the LA of the even-numbered stage, a second clock signal having the opposite phase of the first clock signal is input to the clock signal input terminal of the LA of the even-numbered stage, and The n LAs of the second group are
When the third clock signal is commonly and simultaneously inputted to each clock signal input terminal of the
The outputs from the output terminals of the LAs can be received at each input terminal in a one-to-one correspondence, and data can be simultaneously output from the output terminals of the n LAs of the second group.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and is a block diagram when 4-bit data is input/output, FIG. 2 is a circuit diagram showing an example of a detailed circuit of the LA in FIG. 1, and FIG. Each LA in Figure 1
FIG. 3 is a timing diagram showing the relationship between the output signal of the first clock signal and the first and third clock signals.

In this embodiment, eight LAs (2, 3, . . .
. . 9) and four LAs 13.14, 15.16 of the second group 102.

The data input terminal 1 is connected to the input terminal of LA2 of the first group 101, and the input terminal of LA3 of the first group 101 is connected to the L
Connect to the output terminal Q of A2, and do the same in the same way as the first group 10.
The output terminal Q of LA8 is connected to the input terminal of LA9 in the final stage of 1.
The serial transmission clock signal input terminal enters 10, and the first clock signal (hereinafter referred to as CKI) that has passed through the inverter circuits 11 and 12 is connected to the odd-numbered stage from the data input terminal 1 of the first group 101. A second clock signal is input to each clock signal input terminal C of LA2, 4, and 6.8, and is in the opposite phase of CK1.
The clock signal (hereinafter referred to as CK2) of the first group 101
Even-numbered stage LA3, 5.7.9 from data input terminal 1 of
is input to each input terminal C of the second group 102, LA13,
14. Each input terminal 15 and 19 is connected in a one-to-one correspondence with each output terminal Q of even-numbered stage LA3.5.7 and 9 of the first group 101, and each output terminal Q is a parallel output. It is connected to terminals 18, 19, 20 and 21, and each clock signal input terminal C has a clock signal input terminal 17 for parallel output.
The configuration is such that a third clock signal (hereinafter referred to as CK) inputted from the two terminals is commonly inputted at the same time.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 3.

For example, the first bit of the serial data input signal (0101) inputted from the serial data input terminal 1 is “0” at the falling edge of the first CK inputted from the serial transmission clock signal input terminal 10. It is transferred to LA2 of the first group 101, and transferred to LA3 at the first rising edge of CKl (at the first falling edge of CK2), and in the same way, at the fourth falling edge of CK. Transferred to LA8, at the fourth rise of CK1 (at the fourth fall of CK2)
is transferred to LA9. Also, the last pit 1” is the 4th
It is transferred to LA2 at the falling edge of CKl for the fourth time, and transferred to LA3 at the rising edge of CK4 for the fourth time (at the falling edge of CK2 for the fourth time), and all four bits of the serial data input signal (0101) are Transfer ends.

Thereafter, at the falling edge of CK input to the parallel output clock signal input terminal 17, the bit "'0゛° held in LA9 of the first group 101 is transferred to LA16 of the second group 102, and so on. Pid 1'' held in LA 3 of the first group 101 is simultaneously transferred to LA 13 of the second group. Therefore 1. The data "'010" is connected in parallel by the output of each Q terminal of LA16, 15, 14 and 13 of the second group.
1°゛ can be taken out.

FIG. 2 is a circuit diagram showing an example of a detailed circuit of the D-type latch circuit shown in FIG. 1.

Gate circuits 22 and 25 made of a combination of one P-FET and one N-FET, and an inverter circuit 23.
24 and 26.

When data is input from the data input terminal C, when the clock signal from the clock signal input terminal C has a logic value, the gate circuit 22 becomes conductive, and the data is sent to the output terminal Q. Data with an inverted phase is sent to the output terminal Q. is output to. When the clock signal becomes a logical value H, the gate circuit 22 becomes non-conducting, the gate circuit 25 becomes conductive, and the previous data is held until the next clock signal L is input.

〔Effect of the invention〕

As explained above, the present invention uses a D-type latch circuit in a circuit that latches the output of a shift register in which D-type latch circuits are connected in multiple stages, and uses two clock signals with mutually opposite phases as clock signals for the shift register. Since the number of elements can be reduced, the area occupied by the integrated circuit structure can be reduced and power consumption can be reduced.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, and is a block diagram when 4-bit data is input/output, FIG. 2 is a circuit diagram showing an example of a detailed circuit of the D-type latch circuit shown in FIG. 1, and FIG. The figure is the first
A timing diagram showing the relationship between the output signal of each type latch circuit and the first and third clock signals, FIG. 4 is a block diagram showing an example of a conventional serial-to-parallel conversion circuit, and FIG. 6 is a circuit diagram showing an example of a detailed circuit of the D-type flip-flop circuit shown in FIG. FIG. 1...Data input terminal, 2-9.13-16...D
Type latch circuit (LA), 10... Clock signal input terminal for serial transmission, 11, 12.23.24.26... Inverter circuit, 17... Clock signal input terminal for parallel output, 18-21.・・Parallel output terminal, 22゜25・・
- Gate circuit, 101... first group, 102... second
group, CK1...first clock signal, CK2...second clock signal, CK3...third clock signal
Sweet Graduation 'J Side Kaya 4th Dormitory Yumen

Claims (1)

[Claims] consisting of a first group of 2n (n is an integer of 1 or more) D-type latch circuits (hereinafter referred to as LA) connected in multiple stages, and a second group of n LAs; The 2n LAs in the first group receive a first clock signal from the data input terminal to the clock input terminals of the odd-numbered LAs, and send a first clock signal to the clock signal input terminals of the even-numbered LAs from the data input terminal. A second clock signal having the opposite phase of the clock signal is input, and the n LAs of the second group
When the third clock signal is commonly and simultaneously inputted to each clock signal input terminal of the
The serial type is characterized in that outputs from each of the output terminals of the LAs are received in a one-to-one correspondence to each input terminal, and data can be output simultaneously from each of the output terminals of the n LAs of the second group. Parallel conversion circuit.