JPH0348693B2 - - Google Patents

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a display device in which display elements are arranged in a matrix.

(Prior Art) A display device in which liquid crystal or other display elements are arranged in a matrix requires a drive circuit that generates scanning pulses for sequentially scanning address lines and data lines. As a scanning pulse generation circuit used in such a drive circuit, as shown in FIG. 1, data input to the first stage S ₁ of a shift register row 1 is formed by cascading multiple stages of shift registers S ₁ , S ₂ . . . , Sn. By inputting a data pulse Din to the terminal and transferring this data pulse Din through the shift register train in the order of S ₁ →S ₂ ... → Sn by the clock pulse CP, the output Q ₁ , of each stage S ₁ , S ₂ ..., Sn A circuit is known that generates scanning pulses 21, 22, . . . 2n synchronized with the clock pulse CP from Q 2 , . _. . Qn as shown in FIG.

In FIG. 1, the data pulse Din is a signal that is "1" only during one cycle of the clock pulse CP, and is "0" for all other periods while the shift register column 1 is performing a transfer operation. There is. Generally, in a logic circuit such as a shift register, power consumption increases significantly when a clock pulse is input regardless of whether data is input or not. Therefore, in the scanning pulse generation circuit shown in FIG. 1, when the value of n becomes large, each stage S ₁ , S ₂ , .
A data pulse is given to output Q ₁ , Q ₂ ,...Qn
Even though the period during which each of these is set to "1" is extremely short for one transfer cycle, the power consumption of the entire circuit becomes quite large. This problem is extremely serious, especially in recent years when there is a trend toward using large-sized liquid crystal panels.

(Problems to be Solved by the Invention) As described above, in the conventional display device drive circuit,
Although the transfer period in each shift register is short, clock pulses are always inputted, so there is a problem in that the power consumption of the entire circuit increases.

Therefore, an object of the present invention is to provide a display device with low power consumption.

[Structure of the Invention] (Means for Solving the Problems of the Invention) The present invention has a shift register array formed by cascading a plurality of shift registers, and a shift register array in which one data pulse is transferred by a clock pulse. and a control circuit that sequentially generates scanning pulses synchronized with clock pulses from the outputs of each stage of the shift register array for sequentially scanning address lines and data lines of a display device in which display elements are arranged in a matrix. In this drive circuit, the shift register array is divided into at least two or more blocks, and the control circuit applies clock pulses to each block of the shift register array for only the period necessary for the transfer operation based on a control signal supplied from the outside. It is characterized by being distributed.

(Function) In this invention, the shift register train is divided into at least two or more blocks, and each block is given clock pulses only during the transfer period, that is, during the period when each output scan pulse is generated. Power is reduced to the minimum necessary.

According to the above invention, only two external connection terminals are required, one for common clock pulses and one for inputting control signals, so even if a plurality of divided driving means are connected in cascade, there is no need to increase the number of external terminals. ,
Further, there is no need to adjust the timing of supplying clock pulses to each driving means.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 3 shows the basic configuration of a scanning pulse generation circuit for explaining the present invention. As shown in the figure, the shift register array consists of multiple blocks 3.
1,32, and each of these blocks 3
The configuration is such that clock pulses CP ₁ and CP 2 are individually supplied to clock pulses CP 1 and CP ₂ for a period necessary for each of them to perform a transfer operation. In this way, power consumption can be reduced to 1/the number of divided blocks of the shift register array. In other words, the shift register array is divided into a plurality of blocks, and each block is given a clock pulse only during the period during which a scanning pulse is generated at its output, so power consumption can be effectively reduced.

In this embodiment, in addition to the data pulse Din, it is necessary to externally introduce the same number of clock pulses as the number of divided blocks. Therefore, if it is integrated into an integrated circuit, the number of lead-out pins will increase, resulting in a slight reduction in cost and reliability. It will be disadvantageous.

Next, a first embodiment of the present invention, which is effective when implemented as an integrated circuit, will be described.

FIG. 4 shows the configuration of the scanning pulse generating circuit in the second embodiment, and FIG. 5 shows waveform diagrams of various parts. In the figure, n-stage shift registers S ₁ , S ₂ ,
...Sn is divided into two blocks 41 and 42, and each block 41 and 42 receives clock pulses CP ₁ and CP ₂ and data pulses from the control circuit 43.
D ₁ and D ₂ are given separately. Also, each block 4
1 and 42 are cascaded so as to be divided on the same side surface around a display means in which liquid crystal and other display elements (not shown) are arranged in a matrix.

The control circuit 43 receives a clock pulse CP from the outside and a control signal CS whose level is inverted every time each transfer operation of blocks 41 and 42 is completed, that is, with the same period as the period T of the scanning pulse to be obtained at the output of each stage of the shift register train. , and a rectangular wave with a duty of 1/2 is introduced, and a clock pulse and a data pulse are distributed to blocks 41 and 42 each time the level of the control signal CS is inverted.

That is, the control circuit 43 receives the clock pulse CP.
is used as one input, and the control signal CS and the signal inverted by the inverter 44 are used as the other input.
AND gates 45 and 46, and a shift register (D-flip-flop) 47 that receives CP and CS as inputs.
, with CS as one input, shift register 47
AND gate 4 whose other input is the inverted output Q of
8 and a NOR gate 49. And C.S.
When “0” → “1” rises and “1” →
At the falling edge of "0", "1" level data pulses D ₁ and D ₂ are supplied to the first stage shift registers S ₁ and Sn/2+1 of blocks 41 and 42, respectively.

Further, during periods when CS="1" and CS="0", clock pulses CP ₁ and CP ₂ are supplied to the shift registers of blocks 41 and 42, respectively. As a result,
Outputs Q ₁ to Qn of each stage S ₁ to Sn of the shift register array
Then, scanning pulses synchronized with clock pulses CP (CP ₁ , CP ₂ ) are sequentially obtained.

According to this configuration, among the shift register columns,
Since the number of shift registers that are in the active state when clock pulses are applied is always 1/2 of all shift registers, the power consumption is also approximately 1/2. In this case, it is also necessary to consider the power consumption of the control circuit 43;
This can be ignored compared to the power consumption in the shift register array if the number of stages per block of the shift register array is several dozen or more.

In addition, the external connection terminal is the clock pulse CP.
Since only two circuits are required for inputting the control circuit 43 and the control signal CS, the increase in chip area when integrating the circuit is extremely small even considering the addition of the control circuit 43, which is advantageous in terms of cost and design. It is advantageous.

FIG. 6 shows another embodiment of the present invention, in which the shift register array is divided into four blocks 61, 6.
This is an example of dividing into 2, 63, and 64 parts. Also, the 6th
FIG. 7 shows a waveform diagram of each part in the figure. Control circuit 65
Inputs a clock pulse CP and a control signal CS consisting of a rectangular wave with a period T/2 (T is the period of a scanning pulse) and a duty 1/2, and each block is controlled by an inverter 66, a flip-flop 68, and AND gates 69-72. Clock pulse from 61 to 64
CP ₁ to CP ₄ are created, and the inverter 66, shift register 67, AND gates 73, 75, and
Each block 61~ by NOR gates 74 and 76
Create data pulses D ₁ to _{D 4} to 64.

According to this embodiment, only 1/4 of all the shift registers S ₁ to Sn are always in the active state when clock pulses are applied to the shift register array, so if the power consumption of the control circuit 65 is ignored, The total power consumption is reduced to about 1/4 of that when the shift register array is not divided into blocks. Furthermore, although the number of divided blocks of the shift register array has been increased to four, the number of external connection terminals is only two, as in the embodiment of FIG.

In the above embodiment, the case where the number of divided blocks of the shift register array is 2 and 4 has been described, but it goes without saying that the present invention can be similarly applied to cases where the number of divided blocks is 3 or 5 or more.

Furthermore, in the embodiment, data pulses for each block in the shift register array were created individually by the control circuit, but the final stage output terminal of the previous stage block and the first stage data pulse input terminal of the next stage block were directly connected. , the data pulse may be applied only to the data pulse input terminal of the first stage of the shift register array every period of the scanning pulse.

Since data pulses are distributed internally to each block using control signals, the connection terminal between this scanning pulse generation circuit and the outside is basically one clock pulse input, compared to the first embodiment. Only one terminal and one control signal input terminal are required, and the number of terminals does not increase even if the number of divided blocks of the shift register array increases. This reduction in the number of connection terminals to the outside means that the chip area is reduced due to the reduction in the number of external lead-out pins of the integrated circuit when integrated circuits are integrated, and this can greatly contribute to cost reduction. Also, by reducing external wiring,
Reliability will also be improved.

[Effects of the Invention] According to the present invention, by supplying clock pulses only to the shift register of a block that performs a transfer operation, it is possible to provide a drive circuit for a display device with low power consumption. In addition, in this invention, scanning pulses are not erroneously outputted due to the influence of noise from blocks that are in an inactive state and no clock pulses are supplied, so there is an advantage that there is less deterioration in the quality of displayed images due to erroneous outputting of scanning pulses. There is.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of a conventional scanning pulse generation circuit, FIG. 2 is a scanning pulse waveform diagram showing its operation, and FIG. 3 is a diagram showing the shift register array according to the first embodiment of the present invention. 4 is a basic configuration diagram of a scanning pulse generation circuit divided into two blocks, FIG. 4 is a configuration diagram of a scanning pulse generation circuit according to a second embodiment of the present invention, FIG. 5 is a waveform diagram showing its operation, and FIG. 6 7 is a configuration diagram of a scanning pulse generation circuit according to a third embodiment of the present invention, and FIG. 7 is a waveform diagram showing its operation. 1...Shift register row, 31, 32, 41, 4
2, 61, 62, 63, 64...Shift register row block, 43, 65...Control circuit, _S1 , _S2 ~,
Sn…Shift register, CP, CP ₁ , CP ₂ , CP ₃ ,
CP ₄ ...Clock pulse, CS...Control signal, _D1 , _D2 ,
_D3 , _D4 ...Data pulse, _Q1 , _Q2 ~, Qn...Scanning pulse output.

Claims (1)

[Scope of Claims] 1. At least first and second driving means configured of a multi-stage shift register connected to a display means in which display elements are arranged in a matrix and outputting scanning pulses to the display means; The first and second data pulses are transferred to the first and second driving means by first and second clock pulses, respectively, and the scanning pulses synchronized with each clock pulse are sequentially generated from the output of each stage of the shift register. In the display device, the control means is provided with a common clock pulse from the outside, and a control unit that inverts the level at each time required for each of the first and second driving means to transfer the data pulse. and the control means includes means for generating the first and second clock pulses based on the common clock pulse in accordance with the timing of level inversion of the control signal; A display device comprising means for generating first and second data pulses in accordance with the timing of level inversion of the control signal.