JPS62231291A - Liquid crystal display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a liquid crystal display device, and particularly to a liquid crystal display device in which unit pixels are arranged in a two-dimensional matrix.

(Prior Art) Liquid crystal display devices are widely used as display devices for devices using computers. FIG. 2 shows an example of a conventional liquid crystal display device in which unit pixels are arranged in a two-dimensional matrix. The display device 100 consists of a plurality of liquid crystal unit pixels 101 arranged on a secondary circular row. This display device 100 is driven by a drive device 200. The drive device 200 is connected to the arithmetic device 300, receives data to be displayed, and displays the data on the display device 100 based on this data. In a case where the number of unit pixels is large as in the display device 100, a dynamic drive method is adopted in which pixel columns are sequentially switched and driven by - rows.

For this reason, the driving device 200 includes a memory circuit 201, a latch circuit 202, a latch timing generation circuit 203, a common counter 204, and an address decoder 205.

The storage circuit 201 has the same two-dimensional matrix configuration as the display device 21100, and display data corresponding to each unit pixel 101 on a one-to-one basis is stored on the matrix.

The latch timing generation circuit 203 is a circuit that generates a clock pulse at a constant period, and the storage circuit 201 generates a clock pulse at a constant period.
One row of data is sequentially fetched into the latch circuit 202. Since the row address is sequentially updated by the address decoder 205, data of, for example, the first row, the second row, the third row, etc., is taken into the latch circuit 202 at each latch timing. On the other hand, the common counter 204
C0M1.C0M1. C0M2. ...
.

Proceed with C0Mn. SL1~ on the latch circuit 202
The data taken into SLn is segment access I!
1isea1 to 1isea1 to 3egn are used to access the display circuit 100, but at this time, only the unit pixel 101 in the row specified by the common counter 204 is accessed. For example, when the data on the third row of the memory circuit 201 is taken into the latch circuit 202, the count value of the common counter 204 becomes C0M3, and the count value of the common counter 204 becomes C0M3.
The third row, ie, the pixel row starting from S13, will be accessed based on the data in the latch circuit 202.

As described above, the first to nth rows are sequentially accessed at the clock cycle of the latch timing generation circuit 203.

(Problems to be Solved by the Invention) As described above, data to be displayed is provided from the arithmetic unit 300 to the storage circuit 201 via the data bus. Therefore, the memory circuit 201 must be accessible by the arithmetic unit 300. That is, the memory circuit 20
1 is normally accessed by the latch circuit 202, but when rewriting data, the arithmetic unit 300
It is necessary to apply a chip enable signal (in this example, a negative logic GE) to the drive device 200 and switch this access to the arithmetic device side. However, if the latch timing given by the latch timing generation circuit 203 and the access to this arithmetic unit from the sides overlap, the memory circuit 201 will be accessed from both sides simultaneously, making it impossible to perform normal access operations. I can't. Therefore, in such a case, simultaneous accesses must be avoided by delaying the latch timing or by delaying accesses from the arithmetic unit.

However, due to the characteristics of liquid crystals, if the latch timing is not repeated at regular intervals, differences in shading will appear between pixel rows. Therefore, it is necessary to delay access from the arithmetic device. In reality, as shown in FIG.
SY signal is given, and during the period when this 5usy signal is given, control is performed to avoid the arithmetic device f300 from accessing the memory circuit 201, or when the arithmetic device 300 accesses the memory circuit 201. , a method is adopted in which two accesses are performed in succession and the access that does not overlap with the latch timing is used.

Delaying the access from the arithmetic device when access operations overlap in this way poses a problem in that the arithmetic processing time becomes longer and the processing becomes more complicated.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a liquid crystal display device that can be accessed at all times without delaying the processing operations of an external arithmetic unit.

[Structure of the invention]

(Means for Solving the Problems) The present invention relates to a liquid crystal display device in which unit pixels made of liquid crystal are arranged in a two-dimensional matrix, and a display device in which unit pixels made of liquid crystal are arranged in a two-dimensional matrix. a first latch circuit and a second latch circuit that take in one row of data in the memory circuit; and a display device that displays data on a display device based on the data in the first latch circuit. a first latch circuit and the second
The latch circuit is provided with atref 411111 means for fetching the data in the first latch circuit so that it precedes the data by one row, and an external access means for accessing the memory circuit to an external device. It is designed so that it can be performed at all times.

(Function) In addition to the first latch circuit, a second latch circuit is provided to always latch two rows of data, so that when an external arithmetic unit is accessing the memory circuit, Even if the latch timings overlap, the display operation can be performed without any problem if the data from the second latch circuit is supplied to the first latch circuit.

(Example) The present invention will be described below based on an illustrated example. 1st
The figure is a configuration diagram of a liquid crystal display device according to an embodiment of the present invention. Here, the same components as those of the conventional device shown in FIG. 2 are denoted by the same reference numerals, and the description thereof will be omitted. A feature of this embodiment is that in addition to the first latch circuit 202, a second latch circuit 206 is provided. Both latch circuits 202.206
A latch timing clock from a latch timing generation circuit 203 is applied to both. However, the data in the first latch circuit 202 always precedes the data in the second latch circuit 206 by one row. That is, the data of the addressed row in the memory circuit 201 is first taken into the second latch circuit 206, and the first latch circuit 202 receives the data from the second latch circuit 206 at the next latch timing. I will take it in. Therefore, for example, when the first latch circuit 202 is latching the data on the first row, the second latch circuit 206 is latching the data on the second row.

Chip enable signal G given from arithmetic device 300
E passes through the inverter 207 and becomes a positive logic, one directly and the other through the delay circuit 208 to the NOR circuit 20.
9 input. The output of this NOR circuit 209 is given to the second latch circuit 206, and the latch operation is performed at 1I.
IIIl.

Next, the operation of this apparatus will be explained with reference to the time chart shown in FIG. First, during normal display operation, that is, during period (3), the chip enable signal GE is disabled (negative logic, so "1").

As a result, the input of the NOR circuit 209 becomes "O", and its output becomes "1", that is, the second latch circuit 206
(SPL) latch clock is enabled. Therefore, as described above, the data in the storage circuit 201 is
The signal is taken into the first latch circuit 202 through the latch circuit 206, and a display operation is performed. That is, the address of the memory circuit 201 is specified on the display device side.

Now, suppose that the arithmetic device 300 needs to access the memory circuit 201. This access is made during period (3) in FIG. First, chip enable signal G
E is enabled (0”). This makes NOR
At least one input of the circuit 209 becomes "1" and its output becomes "0", that is, the SPL latch clock is disabled. Therefore, the address of the memory circuit 201 is designated to the 8# arithmetic device side, and no data is taken into the second latch circuit 206 within this period (3).

Now, let us consider a case where the latch timings happen to coincide within this period ■. In this case, the first latch circuit 20
Only the operation in which data in the second latch circuit 206 is taken in is performed.

Since the latch clock of the second latch circuit 206 (SPL) is in a disabled state, the second latch circuit 206 (SPL)
6 is not latched, and the memory circuit 201 is never accessed.

When the access by the arithmetic unit E300 is completed, the chip enable signal CE becomes disabled (“1”) again. At the same time, the address of the memory circuit 201 is designated to the display device @ side. However, the latch clock of the second latch circuit 206 is delayed during the delay time d of the delay circuit 208, that is,
Since “1” is still output during period ■,
The NOR circuit 209 continues to output "0" and is in a disabled state. After delay time 61i, that is, 0 for 111
The state returns to the same state as in period ■ for the first time. This period■
In this case, the data that should have been latched from the storage circuit 201 in the period (3) may be latched into the second latch circuit 206.

The reason for providing the period (2) is that when the address of the memory circuit is switched from the arithmetic device 300 side to the display device 100 side, it takes a predetermined time for the data in the memory circuit to become stable. Furthermore, compared to the latch timing cycle which is on the order of 1 m5 ec, the access time of the arithmetic device 300 is on the order of several μsec, so there is no case that there are two or more latch timings within the interval II in FIG.
This does not affect display operation in any way.

(Effects of the Invention) As described above, according to the present invention, in the liquid crystal display device,
Since two latch circuits are provided, access from an external arithmetic device can always be performed.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a liquid crystal display device according to an embodiment of the present invention, FIG. 2 is a configuration diagram of a conventional liquid crystal display device, and FIG. 3 is a configuration diagram of a conventional liquid crystal display device.
3 is a time chart for explaining the operation of the device shown in the figure. 100...Display device, 101...Unit pixel, 200
...Drive device, 201...Storage device, 202...
First latch circuit, 203... Latch timing generation circuit, 204... Common counter, 205... Address decoder, 206... Second latch circuit, 207
...Inverter, 208...Delay circuit, 209...
・NOR circuit, 300... Arithmetic device.

Claims (1)

[Scope of Claims] 1. A display device in which unit pixels made of liquid crystal are arranged in a two-dimensional matrix; a memory circuit arranged in the two-dimensional matrix and storing data to be displayed for each unit pixel; a first latch circuit and a second latch circuit that take in one row of data in a memory circuit; a display control means that causes the display device to display based on the data in the first latch circuit; address control means for loading data in the memory circuit row by row in a predetermined order into the first latch circuit and the second latch circuit such that the data in the first latch circuit precedes the data by one row; and external access means for allowing an external device to access the storage circuit. 2. The second latch circuit takes in one row of data from the storage circuit, and the first latch circuit takes in one row of data from the second latch circuit. The liquid crystal display device according to item 1. 3. The liquid crystal display device according to claim 2, wherein data is taken into the second latch circuit after a predetermined delay time after the external access means completes the access operation from the external device.