JPH0673068B2 - Liquid crystal display - Google Patents

Description

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device in which unit pixels are arranged in a two-dimensional matrix.

(Prior Art) A liquid crystal display device is widely used as a display device for equipment using a computer. FIG. 2 shows an example of a conventional liquid crystal display device in which unit pixels are arranged in a two-dimensional matrix. The display device 100 includes a plurality of liquid crystal unit pixels 101 arranged in a two-dimensional matrix. This display device 100 is a drive device 200.
Driven by. The drive unit 200 is connected to the arithmetic unit 300, receives data to be displayed, and displays on the display unit 100 based on this data. When the number of unit pixels is large as in the display device 100, a dynamic drive method is adopted in which pixel rows are sequentially switched and driven one by one. Therefore, the drive device 200 includes the memory circuit 201, the latch circuit 202, the latch timing generation circuit 203, and the common counter.
204 and an address decoder 205.

The storage circuit 201 has the same two-dimensional matrix configuration as the display device 100, and display data corresponding to each unit pixel 101 on a one-to-one basis is stored on the matrix. Latch timing generator 203
Is a circuit for generating a clock pulse at a constant cycle, and the data for one row in the memory circuit 201 is sequentially taken into the latch circuit 202 at this cycle. Since the address decoder 205 sequentially updates the row address, the data of, for example, the first row, the second row, the third row, ... Is taken into the latch circuit 202 at each latch timing. On the other hand, the common counter 204
Advances the count to COM1, COM2, ..., COMn each time a clock pulse is obtained from the latch timing generation circuit 203. The data captured in SL1 to SLn on the latch circuit 202 is displayed on the display circuit via the segment access lines Seg1 to Segn.
It is used to access 100, but at this time, only the unit pixel 101 in the row designated by the common counter 204 is accessed. For example, when the data in the third row of the memory circuit 201 is fetched by the latch circuit 202, the common counter 2
Count of 04 COM3, and the third line in the display circuit 100, that is, the pixel row starting with S ₁₃ is accessed based on the data in the latch circuit 202.

As described above, in the clock cycle of the latch timing generation circuit 203, the first row to the nth row are sequentially accessed.

(Problems to be Solved by the Invention) As described above, the data to be displayed is given from the arithmetic unit 300 to the memory circuit 201 via the data bus. Therefore,
The memory circuit 201 must be accessible by the arithmetic device 300. That is, the memory circuit 201 is normally accessed by the latch circuit 202, but when rewriting data, a chip enable signal (negative logic ▲ ▼ in this example) from the arithmetic unit 300 to the drive unit 200 is used.
It becomes necessary to switch this access to the arithmetic unit side. However, when the latch timing given by the latch timing generation circuit 203 and the access from the arithmetic unit side overlap, the memory circuit 201 is simultaneously accessed from both sides, and normal access operation can be performed. Can not. Therefore, in such a case, simultaneous access must be avoided by delaying the latch timing or delaying the access from the arithmetic unit.

However, due to the characteristics of the liquid crystal, if the latch timing is not repeated in a constant cycle, a difference in shade appears between pixel rows. Therefore, there is no choice but to delay the access from the arithmetic unit. Actually, as shown in FIG. 2, a BUSY signal is applied from the latch timing generation circuit 203 to the arithmetic unit 300, and the arithmetic unit is operated while the BUSY signal is applied.
When the control is performed so as to prevent the memory 300 from accessing the memory circuit 201, or when the arithmetic unit 300 accesses the memory circuit 201, the access is performed twice in succession, and the access that does not overlap with the latch timing is performed. The method of using is adopted.

In this way, delaying the access from the arithmetic unit when the access operation for controlling the liquid crystal display and the access operation of the arithmetic unit, that is, the access operations of the first and second access means overlap, causes a long arithmetic processing time. There is a problem that the process becomes complicated.

Therefore, the present invention is a liquid crystal display in which the second access means can always access the storage device without causing any trouble in the display control and without delaying the processing operation of the second access means. The purpose is to provide a device.

[Structure of Invention]

(Means for Solving Problems) In a liquid crystal display device according to the present invention, a display device in which unit pixels made of liquid crystal are arranged in a two-dimensional matrix form, and the display device is driven by sequentially switching pixel rows one by one. Drive unit,
A storage device in which storage areas respectively corresponding to the unit pixels are arranged in the two-dimensional matrix, and a storage capacity for one row of the two-dimensional matrix, and input data in response to a first latch timing control signal. A first latch circuit for taking in the taken data and giving the taken data to the display device; and a capacity for one row of the two-dimensional matrix, and responding to a second latch timing control signal from the memory device. Capture the input data of
A second latch circuit that gives the fetched data to the first latch circuit and outputs the first latch timing control signal at each row switching timing of the display device,
After that, the latch control means for outputting the second latch timing control signal when the enable signal having the first state and the second state which is the logical negation thereof is the first state, and the enable signal First access means for accessing the storage device in the first state so that the storage area of the storage device is sequentially switched by one row at a designated address at each row switching timing of the display device; The memory device is accessed by setting the enable signal to the second state, and the second access means sets the enable signal to the first state except during the access period.

(Operation) According to the present invention, the display device is driven based on the data in the first latch circuit, and the data from the storage device is taken into the first latch circuit via the second latch circuit. Even if the data fetching of the second latch circuit is delayed, the driving of the display device is not hindered and the storage device is always opened to the second access means. When the storage device is accessed by the second access means at the same timing as the latch timing at the time of row switching, after the end of the access, the data is fetched from the storage device to the second latch circuit so that the next display line is displayed. Since the data to be taken into the first latch circuit can be prepared in the second latch circuit by the time of switching to, the storage device is accessed at an arbitrary timing by the second access means. In addition to the above, the display operation can be performed without any trouble.

(Example) Hereinafter, the present invention will be described based on illustrated examples. First
FIG. 1 is a configuration diagram of a liquid crystal display device according to an embodiment of the present invention. Here, the same components as those of the conventional device shown in FIG. One of the characteristics of this embodiment is that a second latch circuit 206 is provided in addition to the first latch circuit 202. The latch timing clock from the latch timing generation circuit 203 is applied to both the latch circuits 202 and 206. The latch circuit 202
To the latch circuit 206 constitutes the first latch timing control signal, and the latch timing clock to the latch circuit 206 constitutes part of the second latch timing control signal. The data in the first latch circuit 202 is always one row ahead of the data in the second latch circuit 206. That is, the data of the row addressed in the memory circuit 201 is first taken in by the second latch circuit 206, and then the data of the first latch circuit 20 is latched at the next latch timing.
2 will take in the data from this second latch circuit 206. Therefore, for example, when the first latch circuit 202 is latching the data of the first row, the second latch circuit 20
6 is latching the data of the second row.

Chip enable signal given from arithmetic unit 300
▼ becomes a positive logic through the inverter 207, and one is given directly to the other and the other is given to the input of the NOR circuit 209 via the delay circuit 208. The second latch timing control signal of the NOR circuit 209 is applied to the second latch circuit 206 together with the latch timing clock to control the latch operation.

Next, the operation of this device will be described with reference to the time chart of FIG. First, during a normal display operation, that is, during a period, the chip enable signal ▲ ▼ is disabled (“1” because it is a negative logic). This allows the NOR circuit 2
Both inputs of 09 become "0" and its output is "1", that is, the second
The latch clock of the latch circuit 206 (SPL) is enabled. Therefore, as described above, the data in the memory circuit 201 is taken into the first latch circuit 202 through the second latch circuit 206 and the display operation is performed. That is, the address of the memory circuit 201 is designated by the address from the common counter 204 on the display device 100 side being decoded by the address decoder 205. That is, these common counter 204 and address decoder 205 constitute the first access means.

Now, it is assumed that the arithmetic device 300 needs to access the memory circuit 201. This access is made during the period shown in FIG. First, the chip enable signal ▲ ▼
Is an enable (“0”). This allows the NOR circuit 2
At least one input of 09 becomes "1" and its output becomes "0", that is, the SPL latch clock is disabled. Therefore, the address of the memory circuit 201 is specified by the arithmetic unit 300 and the address being decoded by the address decoder 205, and during this period, the data is not taken into the second latch circuit 206. As is apparent from this, the arithmetic unit 300 and the address decoder 205 constitute the second access means. Now, consider the case where the latch timings happen to overlap within this period. In this case, the first latch circuit 202 only takes in the data in the second latch circuit 206. Since the latch clock of the second latch circuit 206 (SPL) is in a disabled state, the second latch circuit 206 is not latched and the access to the memory circuit 201 does not overlap.

When the access by the arithmetic unit 300 is completed, the chip enable signal ▲ ▼ becomes disabled (“1”) again. At the same time, the address of the memory circuit 201 is designated on the display device side. However, since the latch clock of the second latch circuit 206 still outputs “1” during the delay time d of the delay circuit 208, that is, during the period, the NOR circuit 2
09 continues to output “0” and is in a disabled state.
After the delay time d elapses, that is, for the first time in the period, the state returns to the same state as the period. During this period, the memory circuit 201
The data that should have been latched in the period from 1 to 4 may be latched in the second latch circuit 206.

The reason for providing the period is that when the address of the memory circuit is switched from the arithmetic device 300 side to the display circuit 100 side, a predetermined time is required until the data in the memory circuit becomes stable. Further, since the access time of the arithmetic unit 300 is on the order of several μsec as compared with the latch timing cycle on the order of 1 msec, there is no latch timing more than once within the period shown in FIG. Does not hinder anything.

〔The invention's effect〕

As described above, according to the present invention, the storage device can be accessed at an arbitrary timing by the second access means, and the display operation can be performed without any trouble.

[Brief description of drawings]

FIG. 1 is a block diagram of a liquid crystal display device according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional liquid crystal display device, and FIG. 3 is a time chart for explaining the operation of the device shown in FIG. It is a chart. 100 ... Display device, 101 ... Unit pixel, 200 ... Driving device, 201 ...
Storage device, 202 ... First latch circuit, 203 ... Latch timing generation circuit, 204 ... Common counter, 205 ... Address decoder, 206 ... Second latch circuit, 207 ... Inverter, 20
8 ... Delay circuit, 209 ... NOR circuit, 300 ... Arithmetic device.

Claims (2)

[Claims] 1. A display device in which unit pixels made of liquid crystal are arranged in a two-dimensional matrix, a drive unit for sequentially switching and driving the pixel columns of each row of the display device, and a drive unit corresponding to each of the unit pixels. A storage device in which storage areas are arranged in the two-dimensional matrix form, and a capacity for one row of the two-dimensional matrix, which takes in input data in response to a first latch timing control signal, and takes in the taken-in data. A first latch circuit for applying to the display device, and a capacity for one row of the two-dimensional matrix, which takes in input data from the storage device in response to a second latch timing control signal, and acquires the data. A second latch circuit for supplying the latched data to the first latch circuit; outputting the first latch timing control signal for each row switching timing of the display device; and thereafter, outputting the first state and its logic. no And a latch control means for outputting the second latch timing control signal when the enable signal having the second state is the first state, and the storage when the enable signal is the first state. First access means for accessing the storage device by sequentially switching the designated address one row at a time for each row switching timing of the display device, and the enable signal as the second state. A liquid crystal display device, comprising: second access means for accessing the storage device and setting the enable signal to the first state except during the access period. 2. The latch control means sets a second delay time with a predetermined delay time after the access operation by the second access means is completed.
The liquid crystal display device according to claim 1, wherein data is taken into the latch circuit.