JP2003347919A - Cascade connection circuit and electronic apparatus provided with same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely transfer a start signal STH between data side drivers in cascade connection. <P>SOLUTION: In the cascade-connection of the data side drivers 40, the first stage data side driver uses its changeover switch 41 to select a basic clock signal CLKA as a clock signal supplied to a start signal read circuit 10 and the data side drivers of the second and succeeding stages select a delayed clock signal CLKB resulting from delaying the basic clock signal CLKA by each delay circuit 9. Thus, the first stage data side driver at a leading edge of a substantial read pulse of the basic clock signal CLKA and the second and succeeding stage data side drivers at a leading edge of a substantial read pulse of the delayed clock signal CLKB can normally read the start signal STH, respectively. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a cascade connection circuit and an electronic device having the cascade connection circuit, and more particularly to a cascade connection circuit for sequentially transferring a start signal between a plurality of semiconductor integrated circuit devices and a cascade connection circuit. Electronic device.

[0002]

2. Description of the Related Art As a dot matrix type display device,
Liquid crystal display devices are thin, lightweight, and low power,
Active matrix color liquid crystal display devices, which are used in various devices such as personal computers and are particularly advantageous for controlling image quality with high definition, dominate.

As shown in FIG. 4, a liquid crystal display module of this type of liquid crystal display device has a liquid crystal panel (LCD panel).
1, a control circuit (hereinafter, referred to as a controller) 2 comprising a semiconductor integrated circuit device (hereinafter, referred to as an IC), a plurality of scanning-side driving circuits (hereinafter, referred to as a scanning-side driver) 3 including an IC, and a data-side driving circuit (Hereinafter, referred to as a data-side driver) 4. The liquid crystal panel 1
Although not shown in detail, a semiconductor substrate on which a transparent pixel electrode and a thin film transistor (TFT) are arranged,
It consists of an opposing substrate on which two transparent electrodes are formed, and a structure in which liquid crystal is sealed between the two substrates so that a predetermined voltage is applied to each pixel electrode by controlling a TFT having a switching function. In addition, an image is displayed by changing the transmittance of the liquid crystal according to the potential difference between each pixel electrode and the counter substrate electrode. On the semiconductor substrate, a data line for transmitting a gradation voltage to be applied to each pixel electrode and a scanning line for transmitting a switching control signal (scanning signal) for the TFT are wired.

The controller 2 has an input side connected to a PC (personal computer) 5 and an output side connected to a scanning driver 3 and a data driver 4. Scanning driver 3
The output side of the data side driver 4 is connected to a scanning line and a data line of the liquid crystal panel 1, respectively. The chip size of the scanning driver 3 and the data driver 4 is limited due to manufacturing restrictions. Therefore, the number of outputs corresponding to the scanning lines and data lines that can be output by one IC is also limited, and the size of the liquid crystal panel 1 is large. In such a case, it is necessary to arrange a plurality of them on the outer periphery of the liquid crystal panel 1. For example, in the case of mounting each of the drivers 3 and 4 on a module in the case of a liquid crystal panel of XGA (1024 × 768 pixels) color display, the scanning driver 3 needs to drive 768 gate lines. In the case where the liquid crystal panel 1 has a driving capability of four, four are required, and one side is arranged in a cascade connection on the left outer periphery of the liquid crystal panel 1. The data side driver 4
Data lines are R (red) and G to display one pixel in color.
(Green), three for B (blue) required, 1024 × 3
= 3072 data lines. For example, when the driving capability for 384 lines is required, the liquid crystal panel 1
8 cascade connections (A, B, ..., H)
On one side.

Image data is sent from the PC 5 to the controller 2 of the liquid crystal display module, and a clock signal and the like are sent from the controller 2 to the scanning driver 3 in parallel with each scanning driver 3, and a vertical synchronization start signal STV Are sent to the first-stage scanning driver 3 and are sequentially transferred to the cascaded next- and subsequent scanning drivers 3.
In addition, a timing signal such as a clock signal and a data signal are sent from the controller 2 to the data driver 4 in parallel to each data driver 4, and a start signal STH for horizontal synchronization is sent to the data driver A at the first stage. , Cascade-connected data drivers B, C,
.., H sequentially. Then, a pulse-like scanning signal is sent from the scanning driver 3 to each scanning line, and when the scanning signal applied to the scanning line is at a high level, all the TFTs connected to that scanning line are turned on, The gradation voltage sent from the driver 4 to the data line is applied to the pixel electrode via the turned-on TFT. When the scanning signal goes low and the TFT changes to the off state, the potential difference between the pixel electrode and the counter substrate electrode is maintained until the next gradation voltage is applied to the pixel electrode. Then, by sequentially transmitting a scanning signal to each scanning line, a predetermined gradation voltage is applied to all the pixel electrodes, and an image can be displayed by rewriting the gradation voltage in a frame cycle.

The data side driver 4 is a circuit for sequentially transferring the start signal STH by cascade connection, as shown in FIG. 5, an input terminal 6 for a basic clock signal CLKA, an input terminal 7 for a start signal STH, and a start signal. An output terminal 8 of STH, a delay circuit 9 for delaying the basic clock signal CLKA supplied to the input terminal 6 by a predetermined time td1 and outputting it as a delayed clock signal CLKB, and delaying the start signal STH supplied to the input terminal 7 Start signal read circuit 10 including a flip-flop that reads at the rising edge of clock signal CLKB
And a plurality of stages that sequentially shift the start signal from the start signal reading circuit 10 in synchronization with the basic clock signal CLKA and output from the output terminal 8 as the start signal STH of the next-stage data-side driver 4 cascaded, for example, It has a shift register 11 in which 64-stage flip-flops are cascaded. The predetermined time td1
Is a start signal S between the data side drivers 4 described later.
It is set smaller than the TH delay time td2.

Next, the operation of the data side driver 4 in cascade connection will be described with reference to FIG. The basic clock signal CLKA is supplied from the controller 2 to the input terminal 6 of each data side driver 4 in parallel. The basic clock signal CLKA supplied to the input terminal 6 is supplied to a delay circuit 9 and a shift register 11, and the basic clock signal CLKA supplied to the delay circuit 9 is delayed by a predetermined time td1 and becomes a start signal as a delayed clock signal CLKB. It is supplied to the reading circuit 10.

The start signal STH is supplied from the controller 2 to the input terminal 7 of the first driver A on the data side at time t1.
Is supplied at the rise to the “H” level. The start signal STH supplied to the input terminal 7 is supplied to the start signal reading circuit 10 of the data side driver A, and this “H” level becomes the delayed clock signal CLKB at time t3.
At the rising edge of the pulse b '. The read start signal STH is supplied to the shift register 11 of the data side driver A, and is supplied to the basic clock signal CL.
The cascade-connected flip-flops are sequentially shifted at the rising edge of KA, and as the start signal of the data-side driver B at the next stage, the basic clock signal CLK at time t4.
It becomes “H” level at the rising edge of the pulse c of A and is output from the output terminal 8 of the driver A on the data side.

The start signal STH output from the output terminal 8 of the data side driver A is delayed by the time td2 due to the influence of the cascade connection wiring capacitance and the like, and at time t5 becomes the "H" level. It is supplied to the input terminal 7 of the side driver B. The start signal STH supplied to the input terminal 7 is supplied to the start signal reading circuit 10 of the data driver B, and this "H" level is read at the rising edge of the pulse d 'of the delayed clock signal CLKB at time t6. It is. The read start signal STH is supplied to the shift register 11 and is output from the output terminal 8 of the data driver B, similarly to the data driver A. Hereinafter, similarly, the start signal STH
, H are sequentially supplied to the input terminals 7 of the data-side drivers C, D,. When the transfer to the data driver H is completed, the start signal STH
Is sent to the data side driver A, and the same operation is started. Although not shown, each data side driver 4
Shift register 11 reads data from the data register disposed in the subsequent stage of the shift register 11 during a period from when the start signal STH is supplied to the input terminal 7 to when it is output from the output terminal 8. Are sequentially output from the cascade-connected flip-flops.

[0010]

By the way, the above-mentioned data side driver 4 clocks the start signal STH by the start signal reading circuit 10 of the data side drivers B, C,... When reading at the rising edge of the signal, if the basic clock signal CLKA supplied to the input terminal 6 is used directly as it is, it is necessary to read at the rising edge of the pulse d. STH delay time td
Depending on the magnitude of the pulse No. 2, reading cannot be performed at the rising edge of the original reading pulse d, and reading may be performed at the rising edge of the next pulse e. In consideration of the above, the basic clock signal CLKA is read at the rising edge of the delayed clock signal CLKB delayed by the time td1. On the other hand, the start signal ST from the controller 2
The timing of H is the same as the basic clock signal C transferred from the controller 2 to each data driver 4 in parallel.
It is determined by the controller 2 based on the LKA. The transfer of the start signal STH from the controller 2 to the first-stage data driver A is performed by the basic clock signal CL.
Since the KA is performed under substantially the same conditions as those in which the KA is transferred from the controller 2 to each data driver 4 in parallel, the timing relationship between the basic clock signal CLK and the start signal STH determined in the controller 2 is determined on the data side. Since the driver A does not collapse much, the start signal ST is read by the start signal reading circuit 10 of the driver A on the data side.
If H is read at the rising edge of the delayed clock signal CLKB, it may be read not at the original reading pulse b ′ of the clock CLKB but at the immediately preceding pulse a ′, and the data side driver 4 of the start signal STH may be read. There is a problem that transfer between them becomes uncertain. Therefore, an object of the present invention is to provide a cascade connection circuit in which the transfer of the start signal STH is reliably performed between a plurality of cascade-connected semiconductor integrated circuit devices, and an electronic device including the circuit.

[0011]

According to the cascade connection circuit of the present invention, a start signal sequentially transferred between a plurality of cascade-connected semiconductor integrated circuit devices is transferred to a preceding semiconductor integrated circuit device in the cascade connection. In the cascade connection circuit in which data is read into the preceding-stage semiconductor integrated circuit device during a period from the time when the data is transferred to the subsequent-stage semiconductor integrated circuit device after the cascade connection, the semiconductor integrated circuit device delays the basic clock signal. A delay circuit for generating a delayed clock signal, a changeover switch for selecting one of the basic clock signal and the delay clock signal, and a start signal reading circuit for reading a start signal at an edge of the clock signal selected by the changeover switch. ,
A shift register for sequentially shifting the start signal from the start signal reading circuit at the edge of the basic clock signal and outputting a start signal to the next-stage semiconductor integrated circuit device. According to the electronic device of the present invention, a start signal sequentially transferred between a plurality of semiconductor integrated circuit devices connected in cascade is transferred to a semiconductor integrated circuit device in a preceding stage of the cascade connection, and then a semiconductor integrated circuit device in a subsequent stage of the cascade connection is connected. In the period before being transferred to the circuit device,
In an electronic device in which data is read into a preceding-stage semiconductor integrated circuit device, the semiconductor integrated circuit device generates a delayed clock signal obtained by delaying a basic clock signal, and one of a basic clock signal and a delayed clock signal Switch, a start signal reading circuit that reads a start signal at the edge of the clock signal selected by the changeover switch, and a start signal from the start signal reading circuit that is sequentially shifted at the edge of the basic clock signal to the next stage. A shift register that outputs a start signal to the semiconductor integrated circuit device, wherein a changeover switch is controlled so as to output a basic clock signal in a first-stage semiconductor integrated circuit device among the semiconductor integrated circuit devices; In the subsequent semiconductor integrated circuit device, a delayed clock signal is output. Characterized in that it is controlled such. The electronic device is used as a display device, and the semiconductor integrated circuit device is a data-side drive circuit. The display device is used as a liquid crystal display device.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. Note that the same components as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted. The liquid crystal display module of the liquid crystal display device includes a liquid crystal panel 1, a controller 2, a plurality of scanning drivers 3, and a data driver 40.

The data side driver 40 is a circuit for sequentially transferring the start signal STH by cascade connection, as shown in FIG. 2, as shown in FIG.
7, an output terminal 8, a delay circuit 9, a start signal reading circuit 10, and a shift register 11;
1 and a mode selection signal terminal 42. The changeover switch 41 receives the delayed clock signal CL from the delay circuit 9 as a clock signal supplied to the shift register 10.
KB or basic clock signal CLKA from input terminal 6
Select and output either one. Changeover switch 41
Is controlled by the logic level of the mode selection signal terminal 42. When one of the logic levels is, for example, "L" level,
The basic clock signal CLKA is selected, and when the other logical level, in this example, the “H” level, the delayed clock signal CLKB is selected.

Next, the operation of the data side driver 40 in the cascade connection will be described with reference to FIG. The basic clock signal CLKA is supplied from the controller 2 to the input terminal 6 of each data side driver 40 in parallel. The basic clock signal CLKA supplied to the input terminal 6 is supplied to the delay circuit 9 and the shift register 11,
The basic clock signal CLKA supplied to one of the inputs and supplied to the delay circuit 9 is delayed by a predetermined time td1 to produce a delayed clock signal CLKB.
It is supplied to the other of the two inputs 1. The data side driver A has a mode selection signal terminal 42 having one logic level,
For example, the switch 41 is set to “L” level and
Selects the basic clock signal CLKA and supplies it to the start signal reading circuit 10. The data side drivers B, C,..., H have the mode selection signal terminal 42 set to the other logic level, in this example, “H” level, and the changeover switch 41
Is supplied to the start signal reading circuit 10.

A start signal STH is supplied from the controller 2 to the input terminal 7 of the first driver A on the data side at time t1.
Is supplied at the rise to the “H” level. The start signal STH supplied to the input terminal 7 is supplied to the start signal reading circuit 10 of the data side driver A, and the “H” level becomes the basic clock signal CLKA at time t2.
At the rising edge of the pulse b. The read start signal STH is supplied to the shift register 11 of the data-side driver A, and the basic clock signal CLK
A is sequentially shifted at the rising edge of A, and as a start signal of the data driver B of the next stage, at time t3, at the rising edge of the pulse c of the basic clock signal CLKA
It becomes “H” level and is output from the output terminal 8 of the data side driver A.

The start signal STH output from the output terminal 8 of the data-side driver A is delayed by the influence of the cascade connection wiring capacitance, etc., and becomes "H" level at time t4. Is supplied to the input terminal 7. The start signal STH supplied to this input terminal 7
Is the start signal reading circuit 10 of the data side driver B.
At the rising edge of the pulse d 'of the delayed clock signal CLKB at time t5. The read start signal STH is supplied to the shift register 11 and is output from the output terminal 8 of the data driver B, similarly to the data driver A.
Similarly, the start signal STH is successively supplied to the input terminals 7 of the data-side drivers C, D,... When the transfer to the data side driver H is completed, the same operation is started by sending the start signal STH to the data side driver A again.

As described above, when the data side driver 40 is cascaded, the changeover switch 41 included in the data side driver 40 serves as a start signal reading clock signal supplied to the start signal reading circuit 10. The first-stage data-side driver A selects the basic clock signal CLKA, and the second- and subsequent-stage data-side drivers B, C,..., H select the delayed clock signal CLKB. ., H at the rising edge of the original read pulse b of the CLKA, and the data side drivers B, C,..., H at the rising edge of the original read pulse d ′ of the delayed clock signal CLKB. Can be read.

In the above embodiment, the start signal is read and shifted at the rising edge of the clock signal. However, the reading and shifting may be performed at the falling edge. In addition, although the liquid crystal display device has been described as an example, the present invention is not limited to this, and the present invention can also be used for transferring a start signal by cascading data-side drivers of other display devices. Further, the present invention is not limited to a display device, and can be used in a case where a start signal is transferred by cascading semiconductor integrated circuit devices in another electronic device to which data is transferred.

[0019]

As described above, according to the present invention, when a plurality of semiconductor integrated circuit devices are used and a start signal is transferred by cascade connection between the semiconductor integrated circuit devices, the changeover switch included in the semiconductor integrated circuit device is used. Accordingly, the first-stage semiconductor integrated circuit device selects the basic clock signal, and the subsequent-stage semiconductor integrated circuit devices select the delayed clock signal obtained by delaying the basic clock signal. At the edge of the original read pulse of the basic clock signal, the semiconductor integrated circuit devices of the next and subsequent stages can normally read the start signal STH at the edge of the original read pulse of the delayed clock signal, respectively. The start signal can be reliably transferred, and a stable operation is guaranteed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit of a liquid crystal display device according to one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a cascade connection circuit of the data-side driver shown in FIG. 1;

3 is a waveform diagram of input / output of a start signal in the cascade connection of the data side driver shown in FIG.

FIG. 4 is a circuit diagram showing a circuit of a conventional liquid crystal display device.

FIG. 5 is a circuit diagram showing a configuration of a cascade connection circuit of the data-side driver shown in FIG. 4;

FIG. 6 is a waveform diagram of input / output of a start signal in the cascade connection of the data side driver shown in FIG. 4;

[Explanation of symbols]

1 LCD panel 9 Delay circuit 10 Start signal reading circuit 11 shift register 40 Data side driver 41 Changeover switch

Claims (4)

[Claims] A start signal sequentially transferred between a plurality of cascade-connected semiconductor integrated circuit devices is transferred to a preceding cascade-connected semiconductor integrated circuit device and then a cascade-connected subsequent semiconductor integrated circuit device. In a cascade connection circuit in which data is read into the preceding-stage semiconductor integrated circuit device until the data is transferred to the cascade connection circuit, the semiconductor integrated circuit device generates a delayed clock signal obtained by delaying a basic clock signal; and A changeover switch for selecting one of the basic clock signal and the delayed clock signal, a start signal reading circuit for reading a start signal at an edge of the clock signal selected by the changeover switch, and a start signal from the start signal reading circuit as a basic clock. The signal is sequentially shifted at the edge of the signal and transferred to the next-stage semiconductor integrated circuit device. A cascade connection circuit comprising: a shift register that outputs a start signal. 2. A cascade-connected semiconductor integrated circuit device, wherein a start signal sequentially transferred between a plurality of cascade-connected semiconductor integrated circuit devices is transferred to a preceding cascade-connected semiconductor integrated circuit device and then a cascade-connected subsequent semiconductor integrated circuit device. In the electronic device in which data is read into the preceding-stage semiconductor integrated circuit device during a period until the transfer is performed, the semiconductor integrated circuit device generates a delayed clock signal obtained by delaying a basic clock signal; A changeover switch that selects one of the basic clock signal and the delayed clock signal, a start signal reading circuit that reads a start signal at an edge of the clock signal selected by the changeover switch, and a start signal from the start signal reading circuit. The clock signal is sequentially shifted at the edge of the clock signal to switch to the next-stage semiconductor integrated circuit device. A shift register for outputting a start signal, wherein the changeover switch is controlled to output the basic clock signal in a first stage semiconductor integrated circuit device of the semiconductor integrated circuit devices; An electronic device, wherein the circuit device is controlled to output the delayed clock signal. 3. The electronic device according to claim 2, wherein the device is used as a display device, and the semiconductor integrated circuit device is a data-side drive circuit. 4. The electronic device according to claim 3, wherein the electronic device is used as a liquid crystal display device.