JP2001092422A - Driving method for liquid crystal display device and liquid crystal display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the driving method for a liquid crystal display device capable of writing a multilevel signal on a display electrode sufficiently even when bluntness is generated in a gate signal and to provide a liquid crystal display device using the same method. SOLUTION: In the state shown in the figure 1 (a), a gate delay is not generated in a gate signal Gn and the gate signal Gn has a pure rectangle shape. In the state shown in the 1 (b), the gate delay is generated in the signal and a gate signal Bf on a gate bus line 2 is blunted. However, a data signal Df is not outputted at the same timing as that of a data signal Dn and the changeover timing of the data signal Df is delayed by Δt than that of the data signal Dn. As a result, even though a gate-off time is delayed by an amount equivalent to the bluntness of the gate signal Gf, since the changeover time of the data signal of the data signal Df is also delayed by Δt, the original level of the data signal Df can be correctly written on a pixel electrode 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a driving method of an active matrix type liquid crystal display device in which switching elements such as thin film transistors and pixel electrodes are arranged in a matrix, and a liquid crystal display device using the same.

[0002]

2. Description of the Related Art Liquid crystal display devices are used in various fields including portable devices as thin and low power display devices. In recent years, high quality display has been demanded as a display device replacing a CRT due to colorization and high definition.

As an active matrix type liquid crystal display device, a thin film transistor (TFT: Thin Film) is used.
The structure of a liquid crystal display device using m Transistor as a switching element will be briefly described with reference to FIG.
FIG. 9 shows a state in which the liquid crystal display device is viewed from the upper surface of the panel. Liquid crystal is sealed between two glass substrates of the array substrate 1 and the counter substrate 14. On the array substrate 1, for example, a plurality of gate / bus lines 2 extending in the horizontal direction of the drawing are formed in parallel in the vertical direction. A plurality of data bus lines 4 extending in the vertical direction in the drawing are formed in parallel with the horizontal direction via an insulating film (not shown). Pixel regions in which the pixel electrodes 8 are formed in a plurality of regions divided by the gate bus lines 2 and the data bus lines 4 formed in the vertical and horizontal directions are formed in a matrix.

A TFT 6 is formed in each pixel near the intersection of the gate bus line 2 and the data bus line 4, and the gate electrode of the TFT 6 is connected to the gate bus line 2.
The drain electrodes are connected to the data bus lines 4, respectively. Further, the source electrode is connected to the pixel electrode 8. Gate bus line 2 is gate driver 1
The data bus line 4 is driven by a data driver 16. When a gray scale voltage is output from the data driver 16 to each data bus line 4 and a gate signal is output to any one of the gate bus lines 2, a gate electrode is connected to the gate bus line 2. A series of TFTs 6 are turned on, and their T
A gradation voltage is applied to the pixel electrode 8 connected to the source electrode of the FT 6.

[0005]

In the active matrix type liquid crystal display device having the above-mentioned structure, the display screen has been improved in definition and the number of display pixels has been increased. Is also happening. For example, the resistance of the gate bus line 2 and the load capacity are increased due to the high definition of the display screen, the miniaturization of the gate bus line 2 accompanying the increase in the number of display pixels, the increase in the number of wirings, and the extension of the wiring length. To cause a gate delay. If the gate delay becomes remarkable, luminance unevenness occurs in the left and right direction of the display screen.

The gate delay will be described with reference to FIG. FIG. 10A shows the TFT 6 located at a position closer to the gate driver 18 side of the gate bus line 2 shown in FIG.
Signal Gn and data signal (gray scale signal) D
n. The horizontal axis represents time, and the vertical axis represents signal level. In the state shown in FIG. 10A, since no gate delay occurs, the gate signal Gn on the gate bus line 2 has a clean rectangular shape. Therefore, the gate of the TFT 6 is turned off during the time when the data signal Dn is being output to the data bus line 4 in accordance with the predetermined data output timing, so that data can be accurately written to the pixel electrode 8.

On the other hand, FIG. 10B shows a gate signal Gf and a data signal Df input to the TFT 6 at a position away from the gate driver 18 of the gate bus line 2 shown in FIG. In the state shown in FIG. 10B, a gate delay has occurred, and the gate signal Gf on the gate bus line 2 is dull. Therefore, even when the data signal Df is output to the data bus line 4 at the same data output timing as the data signal Dn shown in FIG. 10A, the time when the gate of the TFT 6 is turned off by the dullness of the gate signal Gf. , And incorrect data different from the original level of the data signal Df is written to the pixel electrode 8.
The timing of turning off the gate of the TFT 6 due to the dulling of the gate signal Gf becomes longer than a predetermined one horizontal scanning period (1H), and becomes remarkable as the distance from the gate driver 18 increases. For this reason, in the case of the liquid crystal display device shown in FIG. 9, luminance unevenness occurs in the horizontal direction of the drawing, and the display quality cannot be improved.

The gate delay is a problem that cannot be avoided in view of the high definition and high aperture ratio expected of a liquid crystal display device. For example, to reduce the gate delay, it is conceivable to increase the thickness of the gate / bus line. However, increasing the thickness of the gate / bus line decreases the aperture ratio of the display pixel.

Therefore, as a countermeasure against the gate delay, normally, as shown in FIG. 11, the gate signal is controlled so that the gate-off voltage becomes earlier than the switching of the data signal, and the gate signal is outputted to the gate / bus line 2, and the gate signal is outputted. -Ensure that the data signal exists at the time of the off-voltage. FIG.
The output timing of the data signal Dn shown in FIG.
This is the same as that shown in FIG. The gate signal Gn ′ shown in FIG. 11A is the same as the gate signal Gn shown in FIG.
The gate pulse width is shorter than the gate signal Gn. FIG. 10 (b)
The gate signal Gf shown in FIG. 11B has a gate-off voltage near the time of switching of the data signal Df, whereas the gate signal Gf ′ shown in FIG.
The gate-off voltage is at a point immediately before the switching of f. Note that the gate signal G shown in FIG.
f ′ is a waveform in which the waveform becomes dull as the gate signal Gn ′ shown in FIG. Therefore, the gate pulse width of the gate signal Gf ′ is shorter than the gate signal Gf shown in FIG.
As described above, if the gate signal is output to the gate bus line 2 earlier in anticipation of the gate-off time of the TFT 6 being delayed due to the dulling of the gate signal Gf, the data signal can be accurately output even if a gate delay occurs. Can be written to the pixel electrode 8.

However, in this method, since the gate pulse width of the gate signal Gn '(Gf') is shortened as described above, the time for which the TFT 6 is kept on is short. For this reason, the time for writing the grayscale voltage to the pixel electrode 8 is shortened. In particular, when the display area of the liquid crystal display device is enlarged, insufficient writing of data may occur. Alternatively, in order to secure a write margin, T
If the on-resistance is reduced by increasing the size of the FT, there arises a problem that the aperture ratio of each pixel region is reduced and the luminance is reduced.

An object of the present invention is to provide a driving method of a liquid crystal display device capable of sufficiently writing a data signal to a pixel electrode even if a gate signal becomes dull, and a liquid crystal display device using the same.

[0012]

SUMMARY OF THE INVENTION It is an object of the present invention to output a gate signal from a gate driver to a gate bus line connected to a gate electrode of a plurality of thin film transistors and to connect the gate signal to a drain electrode of the plurality of thin film transistors. In a method for driving a liquid crystal display device for outputting an image from at least one data driver to a plurality of data bus lines and displaying an image, the method according to a distance on the gate bus line from the gate driver. This is achieved by a driving method of a liquid crystal display device, characterized by changing data output timing between a plurality of data bus lines.

Further, the above object is to provide a gate driver for outputting a gate signal to a gate bus line connected to a gate electrode of a plurality of thin film transistors, and a plurality of data drivers respectively connected to drain electrodes of the plurality of thin film transistors. At least one that outputs data to the bus line
In the liquid crystal display device having one data driver, the data driver changes data output timing between the plurality of data bus lines according to a distance on the gate bus line from the gate driver. This is achieved by a liquid crystal display device.

In the liquid crystal display device according to the present invention, the liquid crystal display device further includes a control circuit unit for controlling the data driver, wherein the control circuit unit transmits a plurality of data output timing signals for changing the data output timing to the data driver. Is supplied. Alternatively, in the liquid crystal display device according to the present invention, the data driver includes an additional circuit that changes the data output timing.

According to the configuration of the present invention, when outputting a data signal to a plurality of data bus lines, switching of the data signal on the data bus line is performed using at least two types of output timing signals (latch pulses). Can be changed. Therefore, even if the gate signal becomes dull, the data signal can be sufficiently written to the pixel electrode.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A driving method of a liquid crystal display device according to a first embodiment of the present invention and a liquid crystal display device using the same will be described with reference to FIGS. First, an outline of a method for driving the liquid crystal display device according to the present embodiment will be described with reference to FIG. FIG. 1A shows the gate signal Gn and the data signal Dn input to the TFT 6 located at a position near the gate driver 18 side of the gate bus line 2 shown in FIG. ) Is the same as the signal waveform shown in FIG. The horizontal axis represents time, and the vertical axis represents signal level. In the state shown in FIG. 1A, since no gate delay occurs, the gate signal Gn on the gate bus line 2 has a clean rectangular shape. Therefore, the data signal Dn is applied to the data bus line 4 based on the predetermined data output timing.
Since the gate of the TFT 6 is turned off during the time when the pixel electrode 8 is output, the grayscale voltage is applied at the correct data signal level.
Can be written to. On the other hand, FIG. 1B shows a gate signal Gf input to the TFT 6 at a position away from the gate driver 18 of the gate bus line 2 shown in FIG.
And the data signal Df. In the state shown in FIG. 1B, a gate delay has occurred, and the gate signal Gf on the gate bus line 2 is dull.

However, in the present embodiment, FIG.
The data signal Df shown in (b) is not output at the same data output timing as the data signal Dn shown in FIG. 1A, and the signal switching timing of the data signal Df is delayed by the time Δt. Therefore, even if the gate-off voltage is delayed by the slack of the gate signal Gf, the switching time of the data signal Df is also Δt.
Therefore, the level of the original data signal Df can be accurately written to the pixel electrode 8. The gate-off timing due to the dulling of the gate signal Gf becomes longer than a predetermined one horizontal scanning period (1H), and becomes longer as the distance from the gate driver increases, and in response to this, the switching time of the data signal Df changes. What is necessary is just to control so that delay (DELTA) t may be changed sequentially (long).

In this manner, by delaying the switching time of the data signal Df by the dullness of the gate signal Gf, it is possible to avoid a situation in which the time when the gate of the TFT 6 is turned off is delayed. Can be accurately written to the pixel electrode 8. Further, the gate signal Gn (G
Since the gate pulse width of f) is not shortened, the time for maintaining the ON state of the TFT 6 is not shortened, and the time for writing the gradation voltage to the pixel electrode 8 can be sufficiently secured.

Next, a schematic configuration of a liquid crystal display device using the above-described driving method according to the present embodiment will be described with reference to FIG. FIG. 2 shows the liquid crystal display device as viewed from the top of the panel. The configuration of the pixels on the array substrate 1 is the same as that shown in FIG.

As shown in FIG. 2, a plurality of data buses each outputting a data signal to a plurality of data bus lines 4 are provided.
Drivers 16-1 to 16-n are arranged in order from left to right on the panel, for example, TAB (Tape Automated Bo).
The substrate is connected to the array substrate 1 by mounting. For example, in the case of the SVGA display method, 300
The 2400 data bus lines 4 are controlled by using eight (n = 8) data drivers 16 for controlling the data bus lines 4. Similarly, a plurality of gate drivers 18-1 to 18- are arranged from the upper left to the lower panel.
n is provided.

Such a gate driver 18-1 to 18-1
8-n and the data drivers 16-1 to 16-n, the plurality of data bus lines 4 connected to the data drivers 16-1 to 16-n are connected to the data drivers 16-1 to 16-n. Gate driver 18-1 in the order of −n
１８18-n. Gate driver 18
-1 to 18-n are connected via a signal line 26 to a control circuit section 20 for outputting a gate driver control signal.
The control circuit unit 20 includes a dot clock, a horizontal synchronization signal (Hsync), or a vertical synchronization signal (Vs) output from a system such as a PC (personal computer).
nc), and further, gradation data and the like are input. The control circuit unit 20 receives the input Hsync and Vs
gate drivers 18-1 to 18-n
Control. The gradation data is supplied to the data drivers 16-1 to 16-1 through the data and data driver control signal lines 28.
16-n.

The control circuit section 20 has a counter 22 and a decoder 24. The dot clock input to the control circuit section 20 is input to the counter 22 and counted. FIG. 3 shows the counter 22 and the decoder 24.
Is enlarged. As the counter 22, a general binary counter is used. RESE of counter 22
Hsync (or a data enable signal (DE) may be used) is input to the T input. Alternatively, when the control circuit 20 is configured by an ASIC, Hsync
Alternatively, a signal generated inside the ASIC so as to synchronize with the DE may be used. The dot clock from the system is input to the CLK terminal of the counter 22.

The output of the counter 22 is input to a decoder 24. From the C1 output terminal of the counter 22, a rectangular signal having a period twice as long as the dot clock is output, and from the C2 output terminal, 2 of the output signal of the C1 output terminal
A rectangular signal having a double cycle is output. Further, a rectangular signal having a cycle twice as long as the output signal of the C2 output terminal is output from the C4 output terminal, and a rectangular signal having a cycle twice as long as the output signal of the C4 output terminal is output from the C8 output terminal. Is C
A rectangular signal that is twice as large as the output signal of the eight fishing terminals is output.
The decoder 24 outputs two types of latch pulses LP1 and LP2 based on the output values of the C1 to C16 output terminals of the counter 22. Latch pulse LP
1 is output to the data drivers 16-1 to 16- (n-1) excluding the data driver 16-n via the control line 28, and the latch pulse LP2 is output via the control line 30 to the data driver 16-n. n.
The specific configuration of the decoder 24 will be described later.

Next, the driving operation of the liquid crystal display device having such a configuration will be described with reference to FIG. FIG.
(A) shows the waveform of the Hsync signal. FIG.
(B) shows the data drivers 16-1 to 16- (n-
The output timing of the latch pulse LP1 output in 1) is shown. For example, as shown in FIG.
P1 is output in synchronization with the rising edge of the Hsync signal. As shown in FIG. 4C, each of the data drivers 16-1 to 16- (n-1) receives the latch pulse LP1, and writes the data signal on each data bus line 4 to the next pixel area. Switch to the desired gradation voltage.

On the other hand, the data driver 16-n located farthest from the gate drivers 18-1 to 18-n along the gate bus line 2 has a latch pulse LP.
The latch pulse LP2 is supplied from the decoder 24 instead of 1. FIG. 4D shows the output timing of the latch pulse LP2. As shown in the figure, the latch pulse LP2 is input to the data driver 16-n with a delay of Δt from the latch pulse LP1. Therefore, the data driver 16
4n, the data signal is delayed by .DELTA.t from the data signal output from each data driver 16-1 to 16- (n-1) on each data bus line 4 as shown in FIG. Switches.

The above operation is repeated every horizontal scanning period. Each data driver 16-1 to 16- (n-1)
Is output to each data bus line 4 during substantially one horizontal scanning period, and the data signal from the data driver 16-n is substantially equal to the time Δ from the beginning of one horizontal scanning period.
Each data is delayed for the same time as one horizontal scanning period with a delay of t.
Output to the bus line 4.

Therefore, even if the time at which the gate signal falls to the gate-off voltage is delayed by a time Δt due to the gate dulling caused by the delay of the gate signal, the data driver 16-n
The data signal is switched after a delay of time .DELTA.t, and the data is maintained on the data bus line 4 for substantially one horizontal scanning period, so that a sufficient data voltage can be obtained when the TFT 6 is turned off. . As described above, according to the present embodiment, it is possible to take a sufficient time to accurately write the gradation voltage to the pixel electrode 8 even if the gate delay occurs, so that even if the display area of the liquid crystal display device becomes large, There is no shortage of writing. Further, since it is not necessary to increase the size of the TFT 6 in order to secure the write margin by lowering the on-resistance of the TFT 6, a high-quality image without luminance unevenness over the entire display area without reducing the aperture ratio of each pixel area. Display will be possible.

Next, the decoder 24 will be described with reference to FIGS.
An example of the circuit configuration will be described. The latch pulse in the conventional liquid crystal display device is generated at a predetermined timing by counting a dot clock input from the system side to the control circuit unit with reference to the Hsync signal (or another signal corresponding to the Hsync signal). . The decoder 24 according to the present embodiment can generate a plurality of latch pulses by using the same method.

First, the circuit configuration of the decoder 24 according to the present embodiment will be described with reference to FIG. In the present embodiment, the decoder 24 outputs the RESET signal (= Hsync).
A description will be given of an example in which the latch pulse LP1 is output at the third clock from the signal) and the latch pulse LP2 is output 25 clocks after the latch pulse LP1, that is, at the 28th clock from the RESET signal.
The decoder 24 is configured such that the C2 output terminal of the counter 22 has the CLK
D-FF (flip-flop) 40 connected to the terminal
have. The same Hsync signal or data enable signal as the input of the RESET input terminal of the counter 22 is input to the RESET input terminal of the D-FF 40. A reference voltage VCC is applied to a D input terminal of the D-FF 40. The Q output terminal of the D-FF 40 is connected to one input terminal of an EXOR (exclusive OR) circuit 44.

Similarly, the decoder 24 has a D-FF 42 with the C4 output terminal of the counter 22 connected to the CLK terminal. The RESET input terminal of the D-FF 42
The same signal as the input of the RESET input terminal of the counter 22 is input. A reference voltage VCC is applied to a D input terminal of the D-FF 42. The Q output terminal of the D-FF 42 is connected to another input terminal of the EXOR (exclusive OR) circuit 44.

The output terminal of the EXOR circuit 44 is a D-FF
48 D input terminals. C of D-FF48
A dot clock is input to the LK terminal. In addition, the RESET terminal of the D-FF 48
The same signal as the RESET terminal of the FFs 40 and 42 is input. The output signal from the Q output terminal of the D-FF 48 is used as the latch pulse LP1.

The C2, C8, and C16 output terminals of the counter 22 are connected to the three input terminals of the AND circuit 46, respectively. The output terminal of the AND circuit 46 is connected to the D input terminal of the D-FF 52. RESE of D-FF52
The same Hsync signal or data enable signal as the input of the RESET input terminal of the counter 22 is input to the T input terminal. C of D-FF52
A dot clock is input to the LK terminal. The Q output terminal of the D-FF 52 is connected to the D-FF 54 of the next stage.
CLK terminal. RES of D-FF54
The signal input to the ET input terminal is the RESE of the D-FF 52.
The signal is the same as the signal input to the T input terminal, and the reference voltage VCC is applied to the D input terminal. Q of D-FF54
The output terminal is connected to one input terminal of the EXOR circuit 56.

The counters C4, C8, and C4
The 16 output terminals are connected to the 3 input terminals of the AND circuit 50, respectively. The output terminal of the AND circuit 50 is a D-FF
60 D input terminals. R of D-FF60
The same Hsync signal or data enable signal as the input of the RESET input terminal of the counter 22 is input to the ESET input terminal. A dot clock is input to the CLK terminal of the D-FF 60. DF
The Q output terminal of F60 is connected to the CLK terminal of the D-FF 62 of the next stage. The signal input to the RESET input terminal of the D-FF 62 is the same as the signal input to the RESET input terminal of the D-FF 60, and the reference voltage VCC is applied to the D input terminal. The Q output terminal of the D-FF 62 is connected to another input terminal of the EXOR circuit 56.

The output terminal of the EXOR circuit 56 is a D-FF
58 are connected to the D input terminal. C of D-FF58
A dot clock is input to the LK terminal. Also, D
The same signal as the RESET terminal of the D-FFs 60 and 62 is input to the RESET terminal of the -FF 58. An output signal from the Q output terminal of the D-FF 58 is used as a latch pulse LP2.

Next, the operation of the decoder 24 shown in FIG. 5 will be described with reference to the timing chart shown in FIG. FIG.
The timing chart shown in FIG.
sync) signal and the output timing of the CLK (dot clock) signal, and then the output signals from the C1 to C16 output terminals of the counter 22 are sequentially shown. Then, FIG.
3 shows the signal states and the output timings of the latch pulses LP1 and LP2 at the positions (1) to (9) shown in FIG.

First, when the dot clock is input to the CLK terminal of the counter 22 shown in FIG.
The Hsync signal input to the RESET input terminal of “H” is “H”.
(High) ", the count signal is output from the C1 to C16 output terminals in synchronization with the rising edge of the dot clock input to the CLK terminal. When the CLK terminal of the FF 40 becomes “H”, the Q output terminal of the D-FF 40 changes from “L (low)” to “H” (see (1) in FIGS. 5 and 6). Since it is fixed at “H”, the Q output terminal of the D-FF 40
The “H” state is maintained until the signal becomes “L”.

When the count signal from the C4 output terminal is input two clocks later than the count signal from the C2 output terminal and the CLK terminal of the D-FF 42 becomes "H", the DF
D is delayed by two clocks from the state change of the Q output terminal of F40.
-The Q output terminal of the FF 42 changes from "L (low)" to "H" (see (2) in FIGS. 5 and 6). Since the D input terminal is always fixed at “H”, the Q output terminal of the D-FF 42 maintains the “H” state until the RESET signal becomes “L”.

Therefore, the EXO to which these signals are input
At the output terminal of the R circuit 44 (see (3) in FIGS. 5 and 6), only while the levels of the Q output terminals of the D-FF 40 and D-FF 42 are different, that is, the second clock (C
LK = 2) to the “H” state for a second clock width of the fourth clock (CLK = 4). The output from the EXOR circuit 44 is input to the D input terminal of the D-FF 48,
From the Q output terminal 48, a latch pulse LP1 having a width of 2 clocks is output from the third clock (CLK = 3) in synchronization with the dot clock input to the CLK terminal.

On the other hand, the output of the AND circuit 46 changes from the 26th clock (CLK = 26) at which the count signals from the C2, C8 and C16 output terminals of the counter 22 all become "H" to "H" with a width of 2 clocks. After that, the signal becomes “L” for two clocks and then becomes “H” for two clocks again (FIG. 5).
And (4) in FIG. 6). This signal is the D-FF 52 D
Input to the input terminal. Therefore, DF is performed in the same manner as described above.
The Q output terminal of F52 is the 27th clock (CLK = 27)
From this, it becomes “H” for two clock widths, then becomes “L” for two clocks, and then becomes “H” for two clocks again (FIG. 5).
And (5) of FIG. 6). The Q output of the D-FF 52 is D-
The signal is input to the CLK terminal of the FF 54,
Since the input terminal is fixed at “H”, the Q output terminal of the D-FF 54 changes to 27 at the first “H” state change of the Q output.
It changes to “H” at the clock (CLK = 27). This “H” state is maintained until the D-FF 54 is reset (see (6) in FIGS. 5 and 6).

Next, the output of the AND circuit 50 is "H" with a width of two clocks from the 28th clock (CLK = 28) when the count signals from the C4, C8 and C16 output terminals of the counter 22 all become "H". After that, it goes low for two clocks and then goes high again for two clocks (FIG. 5).
And (7) of FIG. 6). This signal is the D-FF60 D
Input to the input terminal. Therefore, DF is performed in the same manner as described above.
The Q output terminal of F60 is the 29th clock (CLK = 29)
From this, it becomes “H” for two clock widths, then becomes “L” for two clocks, and then becomes “H” for two clocks again (FIG. 5).
And (8) of FIG. 6). The Q output of the D-FF 60 is D-
The signal is input to the CLK terminal of the FF 62,
Since the input terminal is fixed at “H”, the Q output terminal of the D-FF 62 changes to 29 at the first “H” state change of the Q output.
It changes to “H” at the clock (CLK = 29). This “H” state is maintained until the D-FF 62 is reset (see (9) in FIGS. 5 and 6).

Accordingly, (6) and (9) of FIGS.
At the output terminal of the EXOR circuit 56 (see (10) in FIGS. 5 and 6) to which the signal shown in FIG. 5 is input, only while the levels of the Q output terminals of the D-FF 54 and the D-FF 62 are different, that is, 27. The state becomes “H” for two clock widths from the clock (CLK = 27) to the 29th clock (CLK = 29). The output from the EXOR circuit 56 is input to the D input terminal of the D-FF 58,
A latch pulse LP2 having a width of 2 clocks is output from the output terminal from the 28th clock (CLK = 28) in synchronization with the dot clock input to the CLK terminal.

The decoder 24 of the present embodiment described above
The third clock (CL) from the Hsync signal
K = 3), the latch pulse LP1 is output, and the latch pulse LP2 can be output with a delay of 25 clocks from the latch pulse LP1, that is, at the 28th clock (CLK = 28) from the Hsync signal. This latch pulse LP
1 is supplied to the data drivers 16-1 to 16- (n-1), and the latch pulse LP2 is supplied to the data drivers 16-n.
, The grayscale signal can be sufficiently written to the pixel electrode even if the gate signal becomes dull due to the gate delay.

Next, a liquid crystal display according to a second embodiment of the present invention will be described with reference to FIGS. FIG.
It shows a state where the liquid crystal display device is viewed from the top of the panel,
Components having the same functions and functions as those shown in FIG. 2 in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted. The liquid crystal display device shown in FIG. 7 is different from the first embodiment shown in FIG. 2 in that the signal line 32 for supplying the latch pulse LP2 from the control circuit unit 20 to the data driver 16-n is not provided. The points are different. Instead, the latch pulse LP2 is supplied from the adjacent data driver 16- (n-1) via the signal line 80. Therefore, a decoder (not shown) in the control circuit unit 20 does not have a function of generating the latch pulse LP2, and is configured to generate only the conventional latch pulse LP1.

FIG. 8 shows a data driver 16- (n) that supplies a latch pulse LP2 to the data driver 16-n.
1 shows a schematic configuration. FIG. 8A shows an additional circuit 82 having an N-stage shift register 84 incorporated in the data driver unit 100. FIG. 8B shows a data driver unit 100 having a circuit configuration similar to that of the related art.

The data driver section 100 has a data register 104 and a shift register 102 for supplying a sampling pulse to the data register 104. The shift register 102 has, for example, 100 stages, and outputs a sampling pulse to the data register 104 in order from 01 to 100 stages. The shift register 102 starts operating when a shift register start pulse is input from the control circuit unit 20, and supplies a sampling pulse to the data register 104 every time a dot clock is input as a CLK signal. The data register 104 has 300 display data storage units (not shown), and R, G, and B display data storage units are sequentially assigned to each stage of the shift register 102. By sequentially transmitting the sampling pulses of each stage, each display data output to the display data line 114 is stored in three corresponding display data storage sections in the data register 104 in sequence. ing. Therefore, the sampling pulses are sequentially 1
When 00 pieces of data are output, display data for 300 subpixels is stored in the data register 104.

The latch 106 is connected to the next stage of the data register 104. When the display data is stored in all the display data storage units of the data register 104, the display data is latched by the latch 106 in response to the latch pulse LP1. A level shifter 108, a D / A converter 110,
A voltage follower output section is provided. In these output circuits, a gray scale voltage corresponding to each display data output from the latch 106 is output to a predetermined data bus line 4. As the gray scale reference voltage, for example, a voltage for 64 gray scales is output, and the output circuit selects a desired voltage value according to the display data and outputs the selected voltage value to the data bus line. 6-bit display data is required to display 64 gradations, and 8-bit display data is required to display 256 gradations.

Now, the data having the above configuration
The additional circuit 82 shown in FIG. 8A is incorporated in the driver 16- (n-1). The addition circuit 82 has an N-stage shift register 84. This data register 84
Is supplied with a latch pulse LP1 supplied to the latch 106 of the data driver unit 100 and a dot clock as a CLK signal. Shift register 8
No. 4 starts operation when the latch pulse PL1 is input, and shifts data every time a dot clock is input. The number of stages of the shift register 84 is determined by how many clocks the latch pulse LP2 is delayed from the latch pulse LP1.
If it is desired to output 2 at 25 clocks after the latch pulse LP1, N = 25 stages may be used.

According to the configuration of the present embodiment, an accurate gradation voltage can be written to the pixel electrode 8 even if there is a gate delay, and data of data can be written without shortening the ON time of the gate of the TFT. A sufficient writing time can be taken. Therefore, even if the display area of the liquid crystal display device becomes large, insufficient writing of data does not occur. Also, since it is not necessary to increase the size of the TFT in order to secure a write margin by lowering the on-resistance of the TFT, a high-quality image without luminance unevenness over the entire display area without reducing the aperture ratio of each pixel area. Display will be possible.

The present invention is not limited to the above embodiment, but can be variously modified. For example, in the above embodiment, the latch pulse LP2 is supplied only to the data driver 16-n farthest from the gate drivers 18-1 to 18-n among the data drivers 16-1 to 16-n. ing. This is particularly effective when the delay due to the dulling of the gate signal is not so large, but the present invention is not limited to this. For example, when the delay due to the dull gate signal is relatively large, the gate drivers 18-1 to 18-1
The latch pulse LP2 may be supplied to a plurality of data drivers in the order from −n. In addition, it is of course possible to generate not only the two types of latch pulses LP1 and LP2, but also various types of latch pulses so as to correspond to the gate delay finely.

In the above embodiment, n data drivers 16-1 to 16-n are used.
In other words, the present invention can be applied to the case where the number of data drivers is one. In this case, the output timing of the data signal may be shifted among a plurality of data bus lines in the data driver.

In the second embodiment, in order to supply the latch pulse LP2 to the data driver 16-n, the data driver 16- (n-
1), an additional circuit 82 is provided, and data
Although the driver 16-n is connected, the present invention is not limited to this. For example, an additional circuit 82 is provided in the data driver 16-n itself, and the other data drivers 16-1 to 16-1
16- (n-1), the control circuit unit 20 sends the control line 3
0, the latch pulse LP1 is input. The latch pulse LP1 is supplied to the data driver 1
6-n to the additional circuit 82 and latch pulse LP2
May be generated and input to the latch 106.

The present invention is not limited to the above embodiment,
Circuits such as gate driver and data driver are TFT
Similarly, the present invention can be applied to a so-called peripheral circuit integrated panel formed on a substrate, and can accurately write a gradation voltage to a pixel electrode even if there is a gate delay, and has high quality without luminance unevenness over the entire display area. Can be displayed.

[0053]

As described above, according to the present invention, the gate
The size of the TFT can be reduced in accordance with the delay of the gate signal on the bus line without impairing the data write margin, so that the aperture ratio of the pixel can be improved and a bright and high-quality image can be displayed. Become like

[Brief description of the drawings]

FIG. 1 is a diagram schematically illustrating a driving method of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a liquid crystal display device using a driving method of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 3 is an enlarged view showing a counter 22 and a decoder 24 of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a driving operation in the liquid crystal display device according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a schematic configuration of a decoder 24 in the liquid crystal display device according to the first embodiment of the present invention.

FIG. 6 is a diagram showing a timing chart of signals in the counter 22 and the decoder 24 in the liquid crystal display device according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a schematic configuration of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 8 is a diagram showing a schematic configuration of a data driver of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 9 is a diagram showing a structure of a conventional liquid crystal display device using a thin film transistor as a switching element.

FIG. 10 is a diagram illustrating a gate delay.

FIG. 11 is a diagram showing a conventional response to a gate delay.

[Explanation of symbols]

 Reference Signs List 1 array substrate 2 gate bus line 4 data bus line 6 TFT 8 pixel electrode 10 liquid crystal 14 counter substrate 16 data driver 18 gate driver 20 control circuit section 22 counter 24 decoder 28 control line 40, 42, 48, 52, 54, 60, 62 D-FF 44, 56 EXOR circuit 46, 50 AND circuit 80 Signal line 82 Additional circuit 84 N-stage shift register 100 Data driver unit 102 Shift register 104 Data register 106 Latch 108 Level shifter 110 D / A converter 112 Voltage follower output unit

Continued on the front page F term (reference) 2H093 NA16 NB07 NB12 NC09 NC16 NC21 NC22 NC26 NC34 NC35 ND22 ND36 ND48 5C006 AA01 AA22 AC02 AC21 AF43 AF51 AF72 BB16 BC06 BC12 BF22 BF26 BF50 EC13 FA25 5C080 AA05 BB05 JJ05 BB05 JJ KK02 KK07 KK43

Claims (4)

[Claims] A gate signal is output from a gate driver to a gate bus line connected to a gate electrode of a plurality of thin film transistors, and at least a plurality of data bus lines connected to drain electrodes of the plurality of thin film transistors are connected to at least a plurality of data bus lines. A driving method of a liquid crystal display device for outputting data from one data driver and displaying an image, wherein the plurality of data bus lines are connected to each other in accordance with a distance on the gate bus line from the gate driver. A method for driving a liquid crystal display device, characterized by changing data output timing. 2. A gate driver for outputting a gate signal to a gate bus line connected to a gate electrode of a plurality of thin film transistors, and a data driver connected to a plurality of data bus lines respectively connected to drain electrodes of the plurality of thin film transistors. And at least one data driver for outputting data between the plurality of data bus lines according to a distance on the gate bus line from the gate driver. A liquid crystal display device characterized by changing output timing. 3. The liquid crystal display device according to claim 2, further comprising a control circuit for controlling the data driver, wherein the control circuit transmits a plurality of output timing signals for changing the data output timing to the data driver. A liquid crystal display device supplied to a driver. 4. The liquid crystal display device according to claim 2, wherein said data driver has an additional circuit for changing said data output timing.