JPH06230743A - Integrated circuit for display data drive - Google Patents

Abstract

PURPOSE:To remarkably reduce the number of elements of a circuit to control the inversion/non-inversion of display data and to perform the inversion/non- inversion control at every bit of the display data in a display data driving IC which drives a matrix type display device by a dynamic system. CONSTITUTION:This circuit is provided with a polarity switching circuit 16 which receives a display data signal serially inputted from an input terminal 11 and outputs the signal by controlling the inversion/non-inversion of the display data signal according to a polarity switching signal inputted from a polarity switching terminal 14, and data processing circuits 18, 191-19n which convert the display data signal serially inputted from the polarity switching circuit and latch it, and output a parallel data signal directly or by converting a voltage level to the outside via plural output terminals 151-15n.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display data driving integrated circuit (IC) for driving a matrix type display device to display by a dynamic method, and more particularly to a circuit for switching the polarity of a display data input signal.

[0002]

2. Description of the Related Art A display data driving IC for dynamically driving a matrix type display device such as a liquid crystal display device, an EL (electroluminescence) display device, a fluorescent display device and a DC plasma display device is basically In addition, a data processing circuit for serially / parallel converting a serially input display data signal and converting the parallel data signal directly or by converting the voltage level to the outside through a plurality of output terminals is provided. ing. Figure 7
Shows an example of a display data driving IC for driving the display of a conventional monochrome EL display device by a dynamic method. FIG. 8 is a timing waveform chart showing an operation example of the IC of FIG.

When the ICs of FIG. 7 are used, a plurality of ICs are arrayed along the horizontal display direction of the EL display device, and a display data signal is input from either one end side or the other end side in the array direction. It has a dual port configuration so that

That is, the pair of first display data input terminals 7
11 and 712 correspond to the display data DO of the first series.
(L) and DO (R) selectively input serially,
This first series of display data input is serially input to the first bidirectional data register 721 for 16 bits.

This first bidirectional data register 721
Is a clock signal C input from the clock input terminal 73.
When K is given through the buffer circuit 74, the first series of display data input DO (L) or DO
(R) is shifted to convert serial data into parallel data. In this case, the first bidirectional data register 72
1 is the direction switching signal R / input from the direction switching terminal 75.
By applying L via buffer circuits 76 and 77, switching control is performed so that the data shift direction is right shift or left shift.

Similarly to the above, the pair of second data input terminals 781 and 782 correspondingly receive the second series of display data DE (L) and DE (R) selectively serially, and the second data The display data input of the series is serially input to the second bidirectional data register 722 for 16 bits.

This second bidirectional data register 722
When the clock signal CK is input through the buffer circuit 74, shifts the display data input DE (L) or DE (R) of the second series to convert serial data into parallel data. In this case, the second bidirectional data register 722 receives the direction switching signal R / L through the buffer circuits 76 and 77, so that the data shift direction is the first bidirectional data register 72.
Switching control is performed in the same data shift direction as 1. The two series of data registers 721 and 722 constitute a 32-bit data register.

The 32-bit latch circuit 79 receives the latch signal / Latch input from the latch input terminal 80 via the buffer circuit 81, and latches the data D1 to D32 input from the 32-bit data register.

32-bit gate circuits 8201 to 82
32, the gate control signal / CL input from the gate control terminal 83 is given through the buffer circuit 84,
It controls passage of the outputs Q1 to Q32 of the bit latch circuit 79.

32-bit exclusive OR circuits 8501-
8532 is supplied with the polarity switching signal P / C input from the polarity switching terminal 86 via the buffer circuit 87, and outputs the outputs of the gate circuits 8201 to 8232 for 32 bits according to the logic level of the polarity switching signal P / C. The logic level is output as it is or after being inverted.

32-bit voltage conversion circuits 8801-8
832 is an exclusive OR circuit 8501 for the above 32 bits.
To 8532 output is converted to a required voltage level, and output signals OUT1 / OUT32 are output terminals 89 for 32 bits.
It outputs to 01-8932. This output signal OUT1 / O
The UT 32 is supplied as a dynamic drive signal to a matrix type EL display device (not shown).

According to the IC of FIG. 7, as can be seen from the timing waveform diagram shown in FIG. 8, 32-bit exclusive OR circuits 8501 to 8532 are generated based on the polarity switching signal P / C input from the polarity switching terminal 86. Common control makes it possible to control the inversion / non-inversion of the display data necessary for driving the matrix-type display device by the dynamic method. However, in the above-mentioned IC, 32-bit exclusive OR circuits 8501 to 85
Each 32 requires the number of elements of 2.5 in terms of NAND gate conversion. Therefore, the pattern occupying area of the exclusive OR circuits 8501 to 8532 for 32 bits on the IC chip becomes large and the chip size becomes large.

Further, since the polarity switching signal P / C input from the polarity switching terminal 86 is commonly input to the 32-bit exclusive OR circuits 8501 to 8532 via the buffer circuit 87, each bit of the display data is displayed. It was impossible to control each.

[0014]

As described above, the conventional display data driving IC is a circuit for controlling the inversion / non-inversion of the display data necessary for driving the matrix type display device by the dynamic type. There is a problem that the number of elements is large and the chip size becomes large.

The present invention has been made to solve the above problems, and the number of elements of a circuit for controlling inversion / non-inversion of display data necessary for driving a matrix type display device by a dynamic method. It is an object of the present invention to provide a display data driving IC which can significantly reduce the number of bits and can perform inversion / non-inversion control for each bit of display data.

[0016]

According to the present invention, in a display data driving integrated circuit for driving a matrix type display device in a dynamic system, a display data signal serially input from a display data input terminal is received and polarity switching is performed. A polarity switching circuit that controls the inversion / non-inversion of the display data signal based on the polarity switching signal input from the terminal and outputs it, and a display data signal serially input from this polarity switching circuit is serial / parallel converted and latched. And a data processing circuit for directly outputting the parallel data signal or converting the voltage level and outputting it to the outside through a plurality of output terminals.

[0017]

By controlling the polarity switching circuit based on the polarity switching signal input from the polarity switching terminal, it is possible to control the inversion / non-inversion of the display data necessary for driving the matrix type display device by the dynamic type. Will be possible.

As described above, by providing the polarity switching circuit for controlling the inversion / non-inversion of the display data signal serially input from the display data input terminal, in the conventional example, the display necessary for driving the display device by the dynamic method is displayed. The large number of exclusive OR circuits required to control the inversion / non-inversion of data are eliminated.

Since the number of elements used in the polarity switching circuit is small, the pattern occupying area of the polarity switching circuit on the IC chip is remarkably reduced, and the chip size can be reduced.

Further, there is an advantage that the pattern of the display data can be controlled by controlling the inversion / non-inversion of each bit of the display data by the polarity switching signal inputted from the polarity switching terminal.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a display data driving IC according to the first embodiment of the present invention. FIG. 2 is a timing waveform chart showing an operation example of the IC of FIG.

In FIG. 1, 11 is a serial data input terminal, 12 is a clock input terminal, 13 is a strobe input terminal, 14 is a polarity switching terminal, and 151 to 15n are a plurality of output terminals (32 in this example). .

The polarity switching circuit 16 includes an inverter G3,
The serial data Sin (display pattern data in this example, hereinafter referred to as “display pattern data” in this example) having clocked inverters G1 and G2 whose operations are controlled based on complementary polarity switching signals DR and / DR is input from the serial data input terminal 11. Inversion / non-inversion of (display data) is output.

The above-mentioned complementary polarity switching signals DR, / DR
Is generated by the polarity switching signal generation circuit 17 including, for example, two inverters based on the polarity switching signal DR input from the polarity switching terminal 14.

The serial / parallel conversion circuit 18 comprises a shift register (32-bit register in this example) to which the clock signal CK input from the clock input terminal 12 is supplied as a shift clock, and the polarity switching circuit 16 is provided.
The display data signal serially input from is fetched in synchronism with the leading edge of the shift clock CK and converted into serial / parallel.

A plurality of (32 in this example) transparent type latch circuits 191 to 19n are connected to the parallel data signals Q1 to Q1 output from the shift register 18.
Qn is input, and in the normal state, the input data is output at the logic level as it is, and the strobe signal STB input from the strobe input terminal 13 is at the active level (for example, “L”).
Input data is latched at the time of output signal OUT1 / OU
T32 is output to the plurality of output terminals 151 to 15n. The output signals OUT1 / OUT32 are supplied as a dynamic drive signal to a matrix type plasma display device (not shown), for example.

According to the IC of FIG. 1, the complementary polarity switching signal DR, which operates as shown in the timing waveform diagram of FIG. 2 and is generated based on the polarity switching signal DR input from the polarity switching terminal 14, By controlling the polarity switching circuit 16 by / DR, it is possible to control the inversion / non-inversion of the display data necessary for driving the matrix-type display device by the dynamic method, and control the pattern of the display data. Become.

As mentioned above, in the IC of FIG.
By having the polarity switching circuit 16 that controls the inversion / non-inversion of the display data signal serially input from the serial input terminal 11 and inputs it to the first stage of the shift register 18,
In the conventional example, a large number of exclusive OR circuits required for controlling the inversion / non-inversion of the display data necessary for driving the display device by the dynamic method are unnecessary.

The polarity switching circuit 16 can be realized by using a relatively small number of elements such as the inverter G3 and the clocked inverters G1 and G2. In the conventional example, a large number of exclusive OR circuits are required. Compared to
The number of elements used is drastically reduced. Therefore, the pattern occupying area of the polarity switching circuit 16 on the IC chip is significantly reduced, and the chip size can be reduced.

Further, there is an advantage that the polarity switching signal DR inputted from the polarity switching terminal 14 can control the inversion / non-inversion of each bit of the display data. FIG. 3 shows a display data driving IC according to the second embodiment of the present invention. FIG. 4 is a timing waveform chart showing an operation example of the IC of FIG. The IC shown in FIG. 3 is different from the IC shown in FIG. 1 in the following points and is the same in other respects. Therefore, the same parts as those in FIG.

(1) The display data Din input from the display data input terminal 31 is commonly input to a plurality of (32 in this example) transparent type latch circuits 191 to 19n via the polarity switching circuit 16, and the plurality of the display data Din are input. Latch signals LH1, LH2,
... LHn is sequentially supplied, and the display data signal is latched when the latch signal is at the active level (for example, "H"). Then, the display data serial / parallel converted by the plurality of latch circuits 191 to 19n is output via a plurality (32 in this example) of output terminals 151 to 15n.

(2) The serial data Sin input from the serial input terminal 11 is input to the first stage of the shift register 18, the shift clock CK is supplied to the shift register 18, the serial data is shifted, and each stage of the shift data is output. QM ... And the shift clock CK are input to a plurality of (two in this example) two-input AND gates 321 to 32n, so that the output of each stage of the shift register 18 is synchronized with the shift clock CK. LH
1, LH2, ... LHn are sequentially taken out. Figure 3
1 operates according to the IC of FIG. 1 described above, for example, as shown in the timing waveform diagram of FIG.
The effect that is almost the same as that of C is obtained. FIG. 5 shows the third aspect of the present invention.
3 illustrates a display data driving IC according to an example. Figure 6
FIG. 6 is a timing waveform chart showing an operation example of the IC of FIG. 5. The IC of FIG. 5 is an application of the configuration of the IC of FIG. 1 and FIG.
A color display device of a matrix system is driven for display by a dynamic system.

16 display data input terminals 61 are provided for each 4
R (red) and G with bit configuration (16 gradations from 0 to F)
The 16 bits of the display data forming a set of (green), B (blue), and luminance data are input correspondingly, and the display data are input serially.

The polarity switching circuit 62 has 16 exclusive OR gates and 16 buffer gates corresponding to the 16-bit display data input from the display data input terminal 61, and the polarity input from the polarity switching terminal 63. When the switching signal DATA REVERSE is given through the buffer circuit 64, the display data signal is inverted or controlled not to be inverted and output.

A transparent type latch circuit 65 for 64 bits is provided corresponding to each of the four series of R, G, B of the display data and the luminance data (only four bits are representatively shown for each series). The latch circuits 65 of the respective series have AND gates 321, 322 ...
The serial data of each corresponding series is sequentially latched in units of 4 bits by the latch signal sequentially supplied from, and the display data input is converted into parallel data in units of 16 sets (64 bits).

Latch circuit 6 for four series of 64 bits
In order to take in 16 sets of display data latched in 5 at the same time, 256 transparent type latch circuits 66 (typically only 16 bits are shown) are provided, and each of these latch circuits 66 is provided with a strobe. The signal / STB input from the input terminal 13 is commonly input as a latch signal.

In the 4-bit counter 67, the gate control signal / CL input from the gate control terminal 68 is given as a reset input R via the buffer circuit 69, and is input from the second clock input terminal 70 via the buffer circuit 71. The second clock signal CK2 is provided as a count input.

The output of the 4-bit counter 67 (4 bits) and the outputs of the 256 latch circuits are digitally compared with 16 sets of display data R, G, B and luminance data (each 4 bits). In order to do so, 64 4-bit digital comparison circuits 72 (typically only 4 are shown) are provided. Each of the comparison circuits 72 receives the second clock signal CK2 as an enable control input, compares the two inputs bit by bit, and outputs respective values for R, G, B, and luminance data of display data. Pulse width modulation (PWM) according to the above.

The output of the 64 comparison circuits 72 ... Is 64.
To each gate circuit 73 (typically, only four gate circuits are shown), and each gate circuit 73 receives a gate control signal / CL input from the gate control terminal 68 via the buffer circuit 69, The 64 comparison circuits 72
Control the passage of the output of.

The output of the 64 gate circuits 73 is 64.
The exclusive OR circuits 74 (typically only four are shown) are input to each of the exclusive OR circuits 74. In each of the exclusive OR circuits 74, the polarity switching signal P / C input from the polarity switching terminal 75 passes through the buffer circuit 76. The logic levels of the outputs of the 64 gate circuits 73 are output as they are or after being inverted according to the logic level of the polarity switching signal P / C.

The outputs of the 64 exclusive OR circuits 74 are input to 64 voltage conversion circuits 77 (representatively only four are shown), and each of the voltage conversion circuits 77 outputs the 64 exclusive OR circuits. The output of the logical OR circuit 74 is converted to a required high voltage level and is output by the push-pull drive circuit,
The output signals OUT1 to OUT64 for bits are supplied as dynamic drive signals to, for example, an EL display device of a matrix system via the output terminals 78 for 64 bits.

The IC of FIG. 5 operates, for example, as shown in the timing waveform diagram of FIG. 6, and the effect substantially the same as that of the IC of FIG. 3 described above can be obtained, and it is desirable to drive at the required voltage level. A matrix type color display device (for example, a color EL display device) can be driven to display by a dynamic system.

[0043]

As described above, according to the display data driving IC of the present invention, a circuit for controlling the inversion / non-inversion of the display data necessary for driving the matrix type display device by the dynamic type is provided. The number of elements can be greatly reduced, and inversion / non-inversion control can be performed for each bit of display data, and the pattern of display data can be controlled.

[Brief description of drawings]

FIG. 1 is a display data driving I according to a first embodiment of the present invention.
The logic circuit diagram which shows C.

FIG. 2 is a timing waveform chart showing an operation example of the IC of FIG.

FIG. 3 is a display data driving I according to a second embodiment of the present invention.
The logic circuit diagram which shows C.

FIG. 4 is a timing waveform chart showing an operation example of the IC of FIG.

FIG. 5 is a display data driving I according to a third embodiment of the present invention.
The logic circuit diagram which shows C.

FIG. 6 is a timing waveform chart showing an operation example of the IC of FIG.

FIG. 7 is a logic circuit diagram showing a conventional display data driving IC.

8 is a timing waveform chart showing an operation example of the IC of FIG.

[Explanation of symbols]

11 ... Serial data input terminal, 12 ... Clock input terminal, 13 ... Strobe input terminal, 14 ... Polarity switching terminal,
151 to 15n ... Output terminal, 16 ... Polarity switching circuit, 17
... polarity switching signal generation circuit, 18 ... shift register, 19
1 to 19n ... Transparent type latch circuit,
21 ... Display data input terminal, 221 to 22n ... Two-input AND gate.

Claims (3)

[Claims] 1. A display data driving integrated circuit for driving a matrix type display device by a dynamic method, wherein a display data signal serially input from a display data input terminal and a polarity switching signal input from a polarity switching terminal are received. A polarity switching circuit for controlling and outputting the inversion / non-inversion of the display data signal based on this, and a display data signal serially input from this polarity switching circuit are serial / parallel converted, and this parallel data signal is directly or An integrated circuit for driving display data, comprising: a data processing circuit which converts a voltage level and outputs it to the outside through a plurality of output terminals. 2. The display data driving integrated circuit according to claim 1, wherein the display data signal serially input from the polarity switching circuit is input to the first stage in the data processing circuit, and the display data signal input is a shift clock. With a shift register that shifts the display data signal input to serial / parallel by shifting with the shift clock input from the terminal, and a signal that is commonly input from the control signal terminal to each stage output of this shift register. An integrated circuit for driving display data, comprising: a plurality of transparent latch circuits for latching inputs. 3. The display data driving integrated circuit according to claim 1, wherein the data processing circuit inputs shift data input from a shift data input terminal to a first stage and inputs the shift data input from a shift clock terminal. A shift register that shifts with a shift clock, a logic circuit that sequentially extracts the output of each stage of this shift register in synchronization with the shift clock, and a display data signal that is serially input from the polarity switching circuit is commonly input to each stage. And a plurality of transparent type latch circuits for latching inputs by signals sequentially fetched from the logic circuit, the display data driving integrated circuit.