KR100326766B1 - Apparatus and method for processing and driving video signals - Google Patents

Abstract

The present invention relates to an image signal processing and driving apparatus for displaying data on a liquid crystal panel, and an image signal processing and driving method. When the digital video data to be transmitted is compared with the pixel data at the same position one line before, By transmitting invalid data and transmitting current data only when there is a change, it minimizes digital video data transition between video signal processing device and video signal driving device to reduce EMI generation and minimizes the number of driving of data bus lines to consume power. It relates to a video signal processing and driving apparatus and a video signal processing and driving method that can minimize the.

Description

Apparatus and method for processing and driving video signals

The present invention relates to an image signal processing and driving apparatus and an image signal processing and driving method of a display device, and in particular, an image signal processing and driving apparatus and an image signal processing capable of reducing the amount of data transition between the image signal processing apparatus and the driving apparatus. And a driving method.

In general, the liquid crystal display is divided into a liquid crystal panel, a light source, and a driving circuit unit.

The liquid crystal panel is largely composed of a liquid crystal layer injected between the upper and lower transparent substrates and the upper and lower transparent substrates. A common electrode, a black matrix, and a color filter layer are formed on the upper transparent substrate, and a plurality of gate lines are arranged in one direction at regular intervals on the lower transparent substrate, and in a direction perpendicular to the gate lines at regular intervals. A plurality of data lines are arranged, and a spatial region between each gate line and the data line is a pixel region, and a pixel electrode and a thin film transistor are arranged in each pixel region. That is, the thin film transistor is selectively turned on according to a signal applied to the gate line by a gate electrode connected to the gate line, a source electrode connected to the data line, and a pixel electrode connected to the drain electrode. Is applied to the pixel electrode.

The driving circuit unit includes a plurality of data drivers for supplying a video signal to each data line of the liquid crystal panel for a given time, a plurality of gate drivers for sequentially driving each gate line, and digital data to each of the data driver and the gate driver. And a timing controller for providing video data and control signals.

The driving circuit of the conventional liquid crystal display will be described with reference to the accompanying drawings.

1 is a block diagram of a general LCD module, and FIG. 2 is a block diagram illustrating an internal configuration of a timing controller for processing an image signal of a conventional LCD.

A general LCD module may include digital video data (digital video data, R [0: 5], G [0: 5], B supplied externally, such as a video graphic array chip of a PC, as shown in FIG. 1). [0: 5]) and a timing controller 10 for adjusting and outputting timings to control the control signals to configure a screen, and digital video data provided from the timing controller 10 as an analog signal. A plurality of source drivers (source drivers) 20 which are converted and supplied to the liquid crystal panel 40 for a given time according to the control signal, and the liquid crystal panel 40 according to a control signal provided from the timing controller 10. And a plurality of gate drivers 30 for driving the respective gate lines.

Here, the number of data lines (data lines) for transmitting video data signals between the timing controller 10 and each source driver 20 transmits a 6-bit color video data signal to a single port. In this case, 18 data lines (6 bits each for R, G, and B and 1 line per 1 bit) are required.

When transmitting video data having an XGA (resolution 1024 * 768) resolution, high frequency data of about 65 MHz is transmitted in parallel on 18 data lines.

In the LCD module, an internal configuration of the timing controller, which is the conventional image signal processing apparatus, is illustrated in FIG. 2.

That is, the conventional timing controller 10 converts serial data into parallel data so that the timing processor can process digital video data and control signals (D_en signal and load signal) input from the PC side (Serial data to Parallel data). Alternatively, the interface circuit 11 converts and outputs LVDS data into CMOS data, and inputs the digital video data and the control signals D_en and Load transmitted from the interface circuit 11 to each of the source drivers. 20) and a timing processor 12 for formatting and outputting video data R, G, and B and a control signal at a timing suitable for reproducing the screen by the gate driver 30, and the timing. Video data and control signals D_en and Load transmitted from the processor 12 are transmitted to the source driver 20 and the gate driver 30 without error. It is composed of the output circuit (Output Circuit) (13) to to.

On the other hand, the configuration of each source driver 20 that is a video signal driving device in the conventional LCD module is as follows.

3 is a configuration diagram of conventional source driver ICs, FIG. 4 is a block diagram of each source driver 20 of the conventional LCD module, and FIG. 5 is an output timing diagram of each unit in FIG. 4.

First, in the configuration of the plurality of source driver ICs of the conventional LCD module, when the 384 output driver / single port method is adopted in the XGA class LCD module, eight source drivers are arranged as shown in FIG. 3. If one source driver drives 128 pixels, one pixel is composed of R, G, and B so that 384 data lines can be driven. Therefore, the control signal D_en output from the timing controller 10 is input to the D_eni terminal of the first source driver 20-1, and the previous source is input from the D-eni terminal of the next source driver 20a. The D_en signal output from the D_eno terminal of the driver is input. The control signal Load and the clock signal clk of the timing controller 10 are input to respective terminals of each source driver.

Here, the detailed configuration of the source driver 20 is as shown in FIG.

The conventional source driver is configured to receive a control signal D_en from the timing controller 10 and a clock signal clk and an enable signal for latching each data. A shift enable unit 51 for generating and sequentially outputting pulse signals (En_01 to En_128) synchronized with the clock signal for every clock signal from the D_en signal, and a plurality of (128) 18 port latch elements 52a. A first latch unit configured to receive each enable signal of the shift enable unit 51 to the Ltc_en terminal of each latch element 52a and sequentially latch data on the data bus according to the enable signal. 52 and a plurality of 128 port 18 latch elements 53a. The first latch receives the control signal Load from the timing controller 10 as the Ltc_en terminal of each latch element 53a. Part (52) Data on the data bus is inputted to the first latch unit 52 by a second latch unit 53 for simultaneously inputting and simultaneously outputting data to be outputted from the shift enable unit 51 and an enable signal output from the shift enable unit 51. And a delay and bus driver 54 to adjust the timing so that it can be latched correctly and to sufficiently drive the bus line.

Here, when the 128th enable signal is generated, the shift enable unit 51 outputs the D_eno signal to the D_eni terminal of the next source driver IC so that the next source driver IC generates the enable signal as described above. .

In the LCD module according to the related art, the operation of the timing controller as an image signal processing apparatus is as follows.

As described above, when transmitting 64 Gray (6bit) video data from the timing controller 10 to each source driver 20 in a single port method, each data line is used for every clock (clk) period using 18 data lines. Valid digital video data is transmitted at a total bit rate of 18 bits / clk, 1 bit each.

Each of the 18 data lines consists of six R-data lines (R0 to R5), G-data lines (G0 to G5), and B-data lines (B0 to B5). The digital video data of one pixel (6 bits each of R, G, and B) is transmitted by 6 bits each. For reference, the dual port method is a method of transmitting data of 2 pixels during every clock period by using 36 data lines.

The 6-bit data thus transferred is converted into an analog signal for a predetermined time in each source driver 20 and used to drive one cell in the liquid crystal panel.

The LCD module of the LCD module with XGA resolution (1024 X 768) has 1024 × 3 data lines (Column) and 768 gate lines (Row), and the thin film transistor cell at the intersection of the data line and the gate line {TFT Cell (Sub-Pixel)} is formed.

Accordingly, 1024 × 3 sub-pixels, that is, 1024 pixels are connected in parallel to one gate line, and a total of 768 gate lines are connected to one liquid crystal panel. As a result, a total of 1024 x 3 x 768 sub-pixels are formed in one pixel.

One thin film transistor cell serves as a sub-pixel representing one of red, blue, and green colors, and is used for red (R), blue (B), and green (G). Three sub-pixels constitute one pixel.

In the LCD module, all the digital video data (1024 x 3 x 6 bits) corresponding to one row are sequentially transmitted from the timing controller 10 to the source driver 20, and then one All the thin film transistor cells Sub-Pixel corresponding to the rows are simultaneously driven individually by the output of each source driver 20.

Which row is selected is made by driving one gate line in the gate driver 30 using the control signal transmitted from the timing controller 10.

In general, a row is selected and driven one by one from the top row of the liquid crystal panel, and one row is connected to one output of the gate driver 30. One vertical period is called until one line is sequentially driven from the top row to the last row one by one, and then again to drive the top row. In this way, driving one by one sequentially is called a progressive driving method. (Depending on the application, odd-numbered lines are sequentially driven from the top first, and then even-numbered lines are driven first. It also uses an interlacing driving method which drives one complete frame by sequentially driving it from the top.)

Source drivers 20 used in the recent XGA-class LCD modules are mainly designed to drive 384 outputs at the same time, and each output is connected to one data line of the liquid crystal panel. Therefore, since there are 1024 x 3 data lines in the XGA class LCD module, eight source drivers 20 having 384 outputs are used. In addition, since there are 768 gate lines (Row), it is designed to sequentially drive 192 gate lines per one gate driver 30, in this case four gate drivers 30 are used.

In case of XGA LCD module having 60 frames per second, each gate line is sequentially driven at about 21.7㎲ intervals (actually shorter because there is a vertical synchronizing section), and this is one horizontal period. This is called.

In order to transmit one row of digital video data from the timing controller 10 to the source driver 20 in a single port method, 1024 clocks are required, and a clock of 65 MHz is used.

Therefore, since the number of clocks during 1H is more than 1024, the timing controller 10 transmits one row of digital video data for 1024 clocks, waits for a predetermined time, and then waits for the source drivers 20. It transmits the control signal (LOAD) to convert the transmitted data into the corresponding analog signal and outputs it to the respective outputs. (When transmitting the data by the dual port method, the clock of 32.5MHz is used. I need a clock.)

The source drivers 20 sequentially receive digital video data required to drive the next row while driving one row selected by the gate driver 30 from the timing controller 10. 20) Stored in the first latch portion of the memory. (The digital video data of the n + 1th row is received while driving the nth row.)

In the conventional transmission method, R, G, and B digital video data sets (R0 to R5 & G0 to G5 & B0 to B5) are always transmitted / received with a valid data set every clock for 1024 clocks.

That is, in order to configure a 1H or 1 row screen, valid data of 1024 (pixels) × 3 (sub-pixels / pillars) × 6 (bits / sub-pixels) bits is transmitted / received during 1024 clocks. Must be received. Therefore, in the worst case, 1024 data transitions occur in 1H per line in 18 data lines. When using the two-port method, up to 512 data transitions occur per line in 36 lines. This increase in the number of data changes causes power consumption and increased EMI.

In addition, the operation of the conventional source driver 20 IC which receives the control signals D_en and Load, the clock signal clk, and the data output from the timing controller 10 and drives each pixel is as follows.

In the timing controller 10, when the D_en signal and the clock signal clk are output as shown in FIG. 5, the shift enable unit 51 may input the data to the first latch unit 51. The enable signals En_01, En_02, ..., En_0127, En_0128 are output in synchronization with the rising edge of the clock signal clk.

Each latch element 52a of the first latch unit 52 has a data input terminal Ri [5: 0], Gi [5: 0], Bi [5: 0] when the enable signal is applied to the Ltc_en terminal. Each data on the data bus is inputted and latched, and the latched data is outputted through the data output terminals Ro [5: 0], Go [5: 0] and Bo [5: 0]. That is, the first latch unit 52 sequentially receives the enable signal from the output terminals of the shift enable unit 51 and sequentially latches data on the data bus in synchronization with the enable signal.

The Ltc_en terminals of the latch elements 53a of the second latch unit 53 are commonly connected to the control signal Load of the timing controller 10 and the data input terminals Ri [5: 0] and Gi [5. : [0], Bi [5: 0]) are the data output terminals Ro [5: 0], Go [5: 0], Bo [5: of the latch elements 52a of the first latch portion 52. 0]) and one to one, respectively. Therefore, the data output from all the latch elements 52a of the first latch portion 52 by the load signal are input to the second latch portion 53 at one time and latched. In addition, the data latched in the second latch unit 53 are output through the data output terminals Ro [5: 0], Go [5: 0], and Bo [5: 0], and the output data are decoded by respective decoders. The signal is then converted into an analog signal, which drives the LCD pixels through the output buffer.

The delay and bus driving circuit section 54 is formed on the data bus by an enable signal sequentially generated by the shift enable section 51 by the D_en signal and the clock signal clk output from the timing controller 10. The time is adjusted so that the data can be latched correctly by the first latch unit 51 and the bus line can be sufficiently driven.

The conventional video signal processing and driving apparatus and the video signal processing and driving method described above have the following problems.

First, as described above, the number of data lines for transferring video data signals between a timing controller as an image signal processing device and a source driver as a driving device is equal to 18 data lines when a 6 bit (64 gray) color video data signal is transmitted to a single port. 6 bits each for R, G, and B, and 1 line per 1 bit) .When transmitting video data with XGA (resolution 1024 * 768) resolution, high frequency of about 65 MHz is parallel on 18 data lines. Since a valid data must be transmitted / received every clock at a transmission rate of, a large amount of electro magnetic interference (EMI) is generated on this line, and power consumption required for data transmission also increases.

That is, since a transition of data transmitted between the timing controller and the source driver occurs every time the zeta is transmitted, EMI is generated and power consumption is increased.

Second, as the resolution is improved or the image quality is improved with 8bit color, the amount of data to be transmitted per unit time increases, so the EMI and power consumption become more serious as the image quality is improved. That is, an 8-bit (256Gray) color video data signal must be transmitted in a single port manner at a data rate of 65 MHz to 24 data lines.

Third, in order to alleviate this problem, a method of connecting a separate component to each data line and control line in the PCB and doubling the number of data lines to reduce the data transfer rate to half (32.5 MHz) is performed. However, as the number of data lines is doubled, it is difficult to design a PCB. Also, a satisfactory EMI reduction effect cannot be expected at resolutions higher than XGA, and additional measures are required.

Fourth, as a new EMI reduction method, the data transmission method is LVDS or current-driven serial transmission method. In this case, the timing controller and the source are not compatible with the existing data transmission method (TTL or CMOS driving method). Drivers need to be replaced entirely to accommodate the changed data drive, which can be costly and time consuming.

1 is a typical LCD module block diagram

2 is a block diagram of a conventional image signal processing device of the LCD

3 is a connection diagram of source driver ICs of a conventional LCD module.

4 is a detailed block diagram of a source driver of a conventional LCD.

5 is a timing diagram of operations of each part of a source driver of a conventional timing controller and LCD;

6 is a block diagram of a video signal processing device having an MDT function according to the present invention;

7 is a block diagram illustrating an MDT processor according to the present invention.

8 is a circuit diagram of the MDT processor according to the first embodiment of the present invention.

9 is a circuit diagram of the MDT processor of the second embodiment of the present invention.

10 is a connection diagram of source driver ICs of an LCD module according to the present invention.

11 is a detailed configuration diagram of a source driver according to the present invention.

12 is an output timing diagram of each part of a timing controller and a source driver according to the present invention.

13 is a flow chart showing a video signal processing method according to the present invention

14 is a flow chart showing a video signal driving method according to the present invention

Explanation of symbols for the main parts of the drawings

11 interface circuit portion 12 timing processing unit

13 output circuit 14 MDT processor

21: delay part 21a, 22c, 24a: flip-flop

22: memory section 22a: FIFO memory section

22b: clock generator 23: bit comparison unit

23a, 23b, 23c: Exclusive Oa Gate

23d: ora gate 24: output control unit

61: shift enable portion 62: first latch portion

62a, 63a: latch element 63: second latch portion

64: delay and bus drive

The present invention has been made to solve such a problem, and compares the current digital video data to be transmitted to the source driver as a driving device with the pixel data at the same position one line before, and treats it as invalid data. Digital video data is transmitted only when there is a change, minimizing the transition of transmitted data to reduce EMI and minimizing power consumption by minimizing the number of driving of data bus lines. Its purpose is to provide a signal processing and driving method.

The video signal processing apparatus of the present invention for achieving the above object is an interface circuit unit for converting and outputting the external video data, the control signal and the MDT control signal (MDT_off) to be processed by the timing processing unit, and the interface circuit unit A timing processor configured to input video data and a control signal and format and output the video data and the control signal at a timing suitable for each source driver and gate driver to reproduce a screen; and a video transmitted from the timing processor according to the MDT control signal. Compare the data with the video data of the previous line, if it is the same, do not output the digital video data and keep the previous video data as it is, and if it is not the same, output the video data delivered from the timing processor. An MDT processor for outputting a latch signal (D_latch) indicating whether the data to be output is valid, and an output for transmitting the digital video signal and the control signal output from the MDT processor to each source driver and gate driver without error (Error) It is characterized by including a circuit portion.

Here, the MDT processor may include a delay unit for delaying and outputting the control signals inputted from the timing processor for a predetermined time, a memory unit for sequentially storing and outputting video data transmitted from the timing processor for a predetermined time, and the timing A bit comparison unit for comparing the video data transmitted from the timing processing unit with the video data of the previous line of the memory unit according to the MDT control signal outputted from the processing unit and determining whether they are identical and generating a latch signal according to the result; It is characterized by having an output control unit for outputting the video data transmitted from the processing unit in accordance with the latch signal of the bit comparison unit.

In addition, the image signal driving apparatus for achieving the above object, the time when the D_en_d signal is started by receiving the D_en_d signal, the clock signal (clk) and the latch signal (D_latch) indicating the start of data transmission from the image signal processing unit When the latch signal (D_latch) signal is in the second state, the enable signal for latching each data is output to the output terminal sequentially determined in synchronization with the pulse signal (clk) and the latch signal (D_latch) is in the first state A shift enable unit that does not output a back enable signal, a first latch unit which sequentially latches data on a data bus according to each enable signal of the shift enable unit, and a load signal according to a load signal of the image signal processor And a second latch unit for simultaneously latching data output from the first latch unit and simultaneously outputting the data to each pixel line. Has its features.

In addition, the video signal processing and driving method of the present invention for achieving the above object, the data is input, compare the data of the current line and the previous line by the pixel unit if the same, and outputs invalid data, the same Otherwise, sequentially outputting and transmitting pixel data of the current line, receiving the transmitted data, replacing invalid data with corresponding pixel data of the previous line, and providing each pixel data to the corresponding data line. Its features are included.

In addition, the video signal processing method of the present invention for achieving the above object, the first step of storing the data in line units by inputting video data, control signals (D_en, Load) and MDT control signals from the outside; When the video data of the current line and the video data of the stored previous line are the same in pixel units according to the MDT control signal, the latch signal is output to the first state and the invalid data are output at the same time. Otherwise, the method includes a second step of outputting the latch signal to the second state and outputting pixel data of the current line.

In addition, the video signal driving method of the present invention for achieving the above object comprises a first step of receiving a latch signal, a control signal (D_en, Load), a clock signal,

A second step of outputting a latch enable signal in synchronization with a clock signal in a second state without outputting a latch enable signal when the latch signal is in a first state for each pixel;

A third step of sequentially primary latching data of one line from the data bus according to the latch enable signal;

And a fourth step of simultaneously latching data of the first latched first line according to the control signal Load and outputting the data to the data line of each pixel.

The video signal processing and driving apparatus and the video signal processing and driving method of the present invention will be described in detail with reference to the accompanying drawings.

6 is a block diagram of an image signal processing apparatus having an MDT function according to the present invention.

In the video signal processing apparatus according to the present invention, as shown in FIG. 6, the serial data is converted into parallel data so that the timing processor can process digital video data, control signals, and MDT control signals MDT_off input from the outside (PC side, etc.). An interface circuit 11 for converting serial data to parallel data or converting LVDS data into CMOS data, and inputting digital video data and a control signal transmitted from the interface circuit 11 to the respective circuits; The source driver 20 and the gate driver 30 format and output the video data R, G, and B and the control signal at a timing suitable for reproducing the screen, and output the MDT output from the interface circuit 11. The timing processor 12 bypasses the control signal MDT-off, and is transferred from the timing processor 12 according to the MDT control signal MDT-off. When the digital video data is compared with the digital video data of the previous line, the previous video data is kept as it is without outputting the digital video data, and the video data transferred from the timing processor 12 is stored only when it is not the same. Minimized Data Transmission (MDT) processor 14 for outputting and outputting a latch signal D_latch indicating whether data to be output is valid, and a digital video signal and a control signal output from the MDT processor 14. Is composed of an output circuit 13 for transmitting to the source driver 20 and the gate driver 30 without an error.

In the video signal processing apparatus of the present invention configured as described above, specific configurations and operations of the MDT processor will be described below.

FIG. 7 is a block diagram illustrating an MDT processor according to the present invention, FIG. 8 is a circuit diagram illustrating the MDT processor according to the first embodiment of the present invention, and FIG. 9 is a circuit diagram illustrating the MDT processor according to the second embodiment of the present invention. .

The MDT processor 14 according to the present invention synchronizes with the digital video data R [0: 5], G [0: 5], and B [0: 5] in the timing processor 12 as shown in FIG. Delay unit that outputs the control signal (Control Signals_d) by adjusting the timing so as to synchronize the transmitted control signals with the output digital video data (Rd [0: 5], Gd [0: 5], Bd [0: 5]) (Delay Block) 21 and the digital video data transmitted from the timing processor 12 to sequentially store for a predetermined time in order to provide digital video data of all lines to output a part or all of the digital video data The digital video data transmitted from the timing processor 12 and the memory 22 are transferred according to a memory element block 22 and an MDT control signal MDT_off output from the timing processor 12. Digital of the pixel at the same position of the previous line A bit comparator block 23 for comparing the video data to determine whether it is the same and generating a latch signal according to the result, and the digital video data R [delivered from the timing processor 12]. 0: 5], G [0: 5], and B [0: 5] are output terminals Rd [0: 5] and Gd [0 according to the latch signal D_latch transmitted from the bit comparison unit 23. : 5] and an output control block 24 for determining whether to output to Bd [0: 5]).

Here, the detailed structure of each part is as follows.

First, the detailed configuration of the MDT processor of the first embodiment of the present invention is as shown in FIG.

That is, the delay unit 21 is composed of n-port flip-flops (F / F) 21a to delay the control signal output from the timing processing unit 12 for a predetermined time in synchronization with the clock signal clk. Output a control signal (control signal_d).

The memory unit 22 is synchronized with a FIFO memory 22a for sequentially storing and outputting digital video data transmitted from the timing processor 12 and a clock signal clk output from the timing processor 12. The clock signal generator 22b is configured to generate a separate clock signal cclk, and the FIFO memory 22a is composed of 1024 18 port flip-flops (F / F) 22c. The video data output from is sequentially stored and output.

The bit comparator 23 is configured to perform logical operations on the R, G, and B video data output from the memory unit 22 and the R, G, and B video data output from the timing processor, respectively. (exclusive OR gate) 23a, 23b, 23c, the output of each of the extruder ora gates 23a, 23b, 23c and the MDT-off signal output from the timing processor 12 are logically operated to latch signals. And an OR gate 23d for outputting (D_latch) to compare the video data output from the timing processor 12 with previous data output from the memory unit 22 to output a latch signal D_latch. .

The output control unit 24 performs an AND operation on the latch signal D_latch output from the bit comparison unit 23 and the clock signal cclk output from the memory unit, and outputs the result of AND gate 24b. And an 18 pod flip-flop (F / F) 24a for outputting digital video data output from the timing processor 12 according to the output signal of the AND gate 24b. The video data output from the timing processor 12 is output according to the latch signal D_latch.

In addition, the detailed configuration of the MDT processor of the second embodiment of the present invention is as shown in FIG.

That is, in the first embodiment of the present invention, video data output from the timing processor 12 according to the latch signal D_latch of the bit comparison unit 23 without using the AND gate and the flip-flop. The output control unit 24 is composed of a plurality of switching elements for switching. When the output control unit 24 is composed of a plurality of switching elements, the video data output from the timing processing unit 12 is generated by the clock signal clk. Since it is output from the output controller 24 without delay, the delay unit 21 also has to output the control signal output from the timing processor 12 without delay, so that there is no n-port flip-flop as in the first embodiment of the present invention. The bypass delay unit 21 is configured.

The video signal processing method of the video signal processing apparatus of the present invention configured as described above is as follows.

In the case of the single port method, 18 bits of digital video data of R [0: 5], G [0: 5], and B [0: 5] are clocked by the timing processor 12 every clock. Are transmitted to the memory unit 22, the bit comparison unit 23 and the output control unit 24 of the MDT processor 14, respectively. The transmission of the digital video data starts when the data enable signal D_en, which is one of the control signals, is generated. In the XGA-class LCD module, the data enable signal is generated during one horizontal period. Digital video data valid for 1024 clocks from. For reference, in the dual port method, 36 bits of digital video data are transmitted every clock for 512 clocks.

The clock signal generator 22b of the memory unit 22 uses the clock signal clk transmitted from the timing processor 12 and a control signal control signal that is a data enable signal D_en. From the occurrence of D_en, only 1024 clock signals cclk are generated and supplied to the AND gate 24b of the FIFO memory 22a and the output controller 24.

The bit comparator 23 is a digital signal of the current line transmitted from the timing processor 12 according to an external MDT control signal MDT_off input through the interface circuit 11 and the timing processor 12. The video data is compared with the digital video data of the previous line transferred from the memory unit 22, and as a result, the latch signal D_latch is supplied to the AND gate 24b of the output control unit 24. The AND gate 24b performs a logical multiplication on the clock signal cclk and the latch signal D_latch, and supplies the AND signal to the clock terminal of the flip-flop 24a of the output controller 24.

That is, the bit comparator 23 may include 16 digital video data transmitted from the timing processor 12 and the memory unit 22 when the MDT_off signal transmitted from the timing processor 12 is low. Compare 16 bits of digital video data delivered from the output of the last 1024th flip-flop (F / F) (1024th) of the FIFO memory 22a. When all bits coincide with each other, the latch signal D_latch is low (State 1). ), And if one bit is different from each other, the latch signal D_latch is generated high (state 2) (assuming that the latch signal D_latch is high enabled).

However, when the MDT_off signal is high, the latch signal D_latch is always fixed high regardless of the result of the bit comparison unit 23.

Therefore, the FIFO memory 22a of the memory unit 22 sequentially stores digital video data transmitted from the timing processor 12 only 1024 valid data sections, and flip-flops F / F of the output controller 24. 24a operates only when the latch signal D_latch is enabled (State 2) among the 1024 valid data sections. (However, the clock supplied to the output control unit 24 is driven by the latch signal D_latch. Since the mask is masked at the AND gate 24b, the clock clk may be supplied from the timing processor 12 to the AND gate 24b.

Therefore, if the control signal D_en is not transmitted even when power is supplied to the LCD module, even if the invalid data and the clock clk are supplied from the timing processor 12, the FIFO memory 22a of the memory unit 22 and Since the clock cclk is not supplied to the output control unit 24, the output control unit 24 maintains the initial state (Reset state) without performing an operation, and the output circuit unit 13 provides a flip-flop (F / F) of the output control unit 24. The Reset value of 24a is transferred and output to the digital video data terminals Rd [0: 5], Gd [0: 5], and Bd [0: 5].

When the data enable signal D_en is generated in the timing processor 12 and digital video data is transmitted to the FIFO memory 22a, the output controller 24, and the bit comparator 23 every clock, the FIFO memory. 22a stores the transferred digital video data sequentially. Since 1024 cclk clocks are supplied, only 1024 clocks cclk are operated from the generation of the data enable signal D_en, so only 1024 sets of valid digital video data are stored in the FIFO memory 22a. The data set transferred to the first flip-flop (F / F) is output as the 1024th flip-flop (F / F) 1024th only at 1024 clocks. Therefore, when the digital video data of the m-th clock of the n-th line is transferred from the timing processor 12 to the FIFO memory 22a, in the 1024th flip-flop of the FIFO memory 22a, the m-th digital video of the n-1th line The data will be output. That is, the relationship between the digital video data transmitted from the timing processor 12 and the output data of the 1024th flip-flop (F / F) of the FIFO memory 22a is the pixel data at the same position of one line difference in the LCD screen.

Therefore, the digital video data input from the timing processor 12 and the digital video data of pixels at the same position before one horizontal section output from the 1024th flip-flop (F / F) of the FIFO memory 22a are converted into bit comparison units ( 23) are compared in bit unit.

The bit comparison unit 23 compares data transmitted from the 1024th flip-flop (F / F) of the timing processor 12 and the FIFO memory 22a by bit to determine whether they are the same, and determines whether they are identical. D_latch). That is, when the MDT control signal MDT_off is low, the bit comparison unit 23 compares the digital video data of the current line with the digital video data of the same position one line before and is low (State 1). The signal, if different, generates a high (State 2) signal and delivers it to the output controller 24. However, when the MDT control signal MDT_off is high, a high state 2 signal is always generated and transmitted to the output controller 24 regardless of the comparison result.

The output controller 24 outputs the current digital video data transmitted from the timing processor 12 or continues the data of the previous clock according to the state of the latch signal D_latch received from the bit comparator 23. Output (the output of the output control unit 24 does not change). That is, when the latch signal D_latch is low, the output of the AND gate 24b of the output control unit 24 is always low regardless of the clock cclk of the clock signal generator 22b of the memory unit 22. Since the state is maintained, the 18-port flip-flop (F / F) of the output control unit 24 does not operate to continuously output data of the previous clock. When the latch signal D_latch signal is high, the output of the AND gate 24b becomes the same as the clock signal cclk, so that the flip-flop (F / F) 24a of the output control unit 24 is the timing. The data input from the processor 12 is output one clock later.

In the second embodiment of the present invention, the output control unit 24 is implemented as an electronic switch (SW_R [5: 0], SW_G [5: 0], SW_B [5: 0]). In this case, since the clocked delay of the digital video data does not occur in the output controller 24, R [5: 0] = Rd [5: 0], G [5. : 0] = Gd [5: 0], B [5: 0] = Bd [5: 0] Also, since there is no clock delay of the digital video data, the control signals are also delayed without delay. Bypass.

As described above, the digital video data output from the MDT processor 14 is output by one clock delay than the digital video data transmitted from the timing processor 12, and the digital video of the pixel at the same position one line ahead. If the data is the same as the data, the output is not changed and the output of the previous clock is maintained.

As described above, the digital video data transmitted from the timing processor 12 to the MDT processor 14 and the digital video data output through the MDT processor 14 generate a time delay of one clock. Delay unit 21 is required because control signals transmitted to output circuit unit 13 and to source drivers must also be delayed by one clock.

The state of the latch signal D_latch is input by the source driver, which is an image signal driving device, as valid data (D_latch = State 2) or by processing as invalid data. Determine whether or not (D_latch = State 1).

The configuration and driving method of an image signal driving device (source driver IC of an LCD module) driving each data line by inputting data and control signals processed by the image signal processing device will be described below.

FIG. 10 is a connection diagram of source driver ICs as the image signal driving apparatus according to the present invention, FIG. 11 is a detailed configuration diagram of the source driver as the image signal driving apparatus according to the present invention, and FIG. 12 is a video signal processing according to the present invention. Fig. 1 is a timing diagram of output of each part of the device and the video signal driving device.

First, although the image signal driving apparatus according to the present invention is composed of a plurality of source driver ICs as in the related art, the D_Ltc terminal for determining whether to output an enable signal for latching in each source driver is as shown in FIG. 10. The latch signal D_latch signal is applied to the D_Ltc terminal.

The detailed configuration of the source driver 20 according to the present invention is as shown in FIG.

That is, in the configuration of the source driver which is the video signal driving apparatus of the present invention, the D_en_d signal (a pulse signal indicating the start of data transmission), a clock signal clk, and a latch signal D_latch are transmitted from the video signal processing unit 10. When the latch signal D_latch signal is 'high' state (second state) from the time when the D_en_d signal is received by the D_eni terminal, the clk terminal, and the D_Ltc terminal, the enable signal D_en signal is latched. And outputs a pulse signal synchronized with the clock signal to every output signal sequentially to an output terminal sequentially synchronized with the clock signal clk, and when the latch signal D_latch is in a low state (first state). The shift enable part 61 includes a shift enable part 61 for preventing an output signal from being output to the clock signal clk during the low 'state, and a plurality of 128 port 18 latch elements 62a. A first latch unit 62 which receives each enable signal of the unit 61 as the Ltc_en terminal of each latch element 62a and sequentially latches data on the data bus only when the enable signal is present; 128 pieces of 18 port latch elements 63a are configured to receive a load signal from the image signal processing unit 10 as the Ltc_en terminal of each latch element 63a, and output data from the first latch unit 62. The data on the data bus can be correctly latched to the first latch portion 62 by the second latch portion 63 for simultaneously inputting and simultaneously outputting them, and the enable signal output from the shift enable portion 61. And a delay and bus driver 64 so as to adjust timing so as to sufficiently drive the bus line.

Here, when the 128th enable signal is generated, the shift enable unit 61 outputs the D_eno signal to the D_eni terminal of the next source driver IC so that the next source driver IC generates the enable signal as described above. .

The operation of the source driver 20 IC which is the video signal driving device of the present invention configured as described above is as follows.

As illustrated in FIG. 12, the shift enable unit 61 receives the D_en_d signal, the clock signal clk, and the latch signal D_latch output from the image signal processor 10. When the received latch signal is 'high', the shift enable unit 61 is synchronized with the rising edge of the clock signal clk so that each data can be input to the first latch unit 62. Enable signals En_01, En_02, ..., En_0127, En_0128 are output. On the contrary, when the latch signal D_latch is 'low', the shift enable unit 61 does not output the enable signal regardless of the clock signal. In FIG. 12, since the latch signal D_latch is 'low' at the moments En_01 (1), En_128 (1), and En_03 (2), the enable signal is not output at that moment. That is, the section in which the latch signal D_latch is 'low' is when the data signal of the previous line and the currently input data signal are the same.

Accordingly, the latch element 62a to which the enable signal is applied to the Ltc_en terminal among the latch elements 62a of the first latch portion 62 is the data input terminal Ri [5: 0] and Gi [5: 0. ], Bi [5: 0]) inputs and latches data on the data bus, respectively, and the latch element 62a to which the enable signal is not applied is connected to the data input terminals Ri [5: 0] and Gi [5. : 0] and Bi [5: 0]) do not input data on the data bus, but continue to latch the data on the previous line.

The latched data is then output through the data output terminals Ro [5: 0], Go [5: 0], and Bo [5: 0] of each latch element 62a. That is, each latch element 62a of the first latch unit 62 receives the enable signal sequentially from the output terminals of the shift enable unit 61 to synchronize data with the enable signal to receive data on the data bus. The latch element 62a, which is sequentially latched and output and does not receive the enable signal, outputs data of the previous line.

In addition, the load signal output from the video signal processor 10 is commonly input to the Ltc_en terminals of the latch elements 63a of the second latch unit 63, and the data input terminal Ri [5: 0]. , Gi [5: 0], Bi [5: 0]) are the data output terminals Ro [5: 0], Go [5: 0], of the latch elements 62a of the first latch portion 62. Bo [5: 0]) is connected one to one, respectively. Accordingly, data output from all the latch elements 62a of the first latch part 62 by the load signal are input latched to the second latch part 63 at a time, and the latched data are the data output terminals Ro. [5: 0], Go [5: 0], Bo [5: 0]). The output data is converted into an analog signal at each decoder to drive the LCD pixel through the output buffer.

As described above, an image signal processing and driving method for driving the image signal by receiving the data processed by the image signal processing apparatus and transmitted by the image signal driving apparatus will be described as follows.

13 is a flowchart showing a video signal processing method of the present invention.

First, the video signal processing apparatus receives the video data, the control signals D_en and Load, and the MDT control signal from the outside, and checks the MDT control signal while storing the input data (S1, S2, and S3).

The image data currently input according to the MDT control signal is compared with the image data of the stored previous line in pixel units (S4).

As compared with the above, if the pixel data of the current line is the same as the corresponding pixel data of the previous line (S4), the latch signal D_latch is outputted as 'low' and the invalid data is maintained. The output of (24) is maintained (S5, S6, S9). If the pixel data of the current line is not the same as the pixel data of the previous line (S4), the latch signal is output 'high' and the pixel data of the current line is transmitted (S7, S8). , S9) Repeat the process.

After all, the previous line and the current line data are compared in units of pixels based on the data of one line, and if the same is the case, the latch signal is set to 'low' state and the invalid data is outputted; otherwise, the latch signal is set to the 'high' state. To transmit the current pixel data.

As such, when the image signal processing apparatus outputs the latch signal, the data, the control signals D_en, Load, and the clock signal, the signals are received and the driving apparatus supplies data to each data line.

A driving method of such an image signal driving apparatus will be described below.

14 is a flowchart illustrating a video signal driving method according to the present invention.

A latch signal, a control signal (D_en, Load), a clock signal (clk), and data transmitted from the image signal processing apparatus are received (S0). In this case, the control signal D_en is a signal for data transmission.

When the control signal D_en is input (S1), the latch signal state is determined (S2). If the received latch signal is 'high', a latch enable signal is generated (S4), and the latch signal is 'low'. In this case, the latch enable signal is not generated (S3). As such, the latch enable signal corresponding to each pixel is generated or not generated according to the latch signal.

When the latch enable signal is generated in this manner, the data of the pixel is latched from the data bus according to the enable signal of each pixel (S5). At this time, the pixel without the latch enable signal is latched with the pixel data of the previous line as it is without latching the data from the data bus.

In this manner, when each pixel data is sequentially latched so that one line of data is primarily latched (S6), the second latched data of the first latched line is simultaneously latched according to the control signal (Load). Are sequentially supplied to the data lines (S7, S8).

This process is repeated to display the video signal.

As described above, the video signal processing apparatus and the video signal processing method of the present invention have the following effects.

First, by comparing digital video data transmitted to source drivers with data of pixels at the same position one line before, the digital video data is transmitted only when there is a change, and the video signal is transmitted only when there is a change. Minimize the transmission of digital video data between the processing unit and each source driver. Therefore, the occurrence of EMI can be reduced by minimizing the data change in the data bus line.

Second, power consumption can be minimized by minimizing the number of driving times of the data bus lines.

Third, the MDT method of the present invention is applicable not only to CMOS I / F but also to LVDS, RSDS or Current Mode I / F.

Fourth, the unit cost can be reduced by the above results.

Claims (19)

An interface circuit unit which converts and outputs video data, control signals, and MDT control signals from the outside so as to be processed; A timing processor which inputs the video data and the control signal transferred from the interface circuit unit, formats and outputs the video data and the control signal at a timing suitable for each source driver and the gate driver to reproduce the screen, and bypasses the MDT control signal; , The video data transmitted from the timing processor according to the MDT control signal is compared with the video data of the previous line. When the video data is the same, the previous video data is maintained as it is without outputting the digital video data. An MDT processor which outputs video data of a processing unit and outputs a latch signal indicating whether the output data is valid; And an output circuit unit for transmitting the digital video signal and the latch signal output from the MDT processor to each source driver and the gate driver without an error. The method of claim 1, When the MDT control signal is in the first state, the MDT processor compares the video data transmitted from the timing processor with the video data of the previous line so that the previous video data is maintained as it is without outputting the digital video data. And outputting the video data of the timing processor only when it is not the same, and outputting the video data of the timing processor unconditionally when the MDT control signal is in the second state. A delay unit for outputting a delayed control signal by a predetermined time; A memory unit for sequentially storing and outputting input video data for a predetermined time; A bit comparison unit which compares current video data with video data of a previous line of the memory unit according to an input MDT control signal and determines whether the same is identical, and generates a latch signal according to the result; And an output control unit for outputting input video data according to a latch signal of the bit comparison unit. The method of claim 3, wherein And the delay unit comprises a flip-flop of n ports. The method of claim 3, wherein The delay unit bypasses the input control signals, characterized in that the image signal processing device. The method of claim 3, wherein The memory unit sequentially stores and outputs video data transferred from the timing processor; And a clock signal generator configured to generate a separate clock signal in synchronization with the clock signal output from the timing processor. The method of claim 6, And the FIFO memory comprises 1024 18 port flip-flops. The method of claim 3, wherein The bit comparison unit may include a plurality of exclusive unit ora gates configured to logically perform R, G, and B video data output from the memory unit and R, G, and B video data output from the timing processor; And an OR gate for outputting a latch signal by performing a logic operation on an output of each of the Exploration unit OR gates and an MDT control signal output from the timing processing unit. The method of claim 3, wherein The output controller may include an AND gate configured to perform a logic operation on a latch signal output from the bit comparison unit and a clock signal output from the memory unit; And a flip-flop for outputting video data transferred from the timing processor in accordance with the output signal of the AND gate. The method of claim 3, wherein And the output control unit comprises a plurality of switching elements for switching the output of the video data output from the timing processing unit (12) according to the latch signal of the bit comparison unit. When the latch signal D_latch signal is in the first state from the time when the D_en_d signal is received, the data signal is inputted from the image signal processor to receive the D_en_d signal and the clock signal clk and the latch signal D_latch. A shift enable unit which outputs an enable signal for latching to the output terminal sequentially determined in synchronization with the pulse signal clk, and does not output the enable signal when the latch signal D_latch is in the second state; A first latch unit which sequentially latches data on a data bus according to each enable signal of the shift enable unit; And a second latch unit configured to simultaneously latch data output from the first latch unit according to the load signal of the image signal processor and output the same to each pixel line. The method of claim 11, And a delay and bus driver for adjusting timing and driving a bus line so that data on a data bus can be latched by the enable signal output from the shift enable part. A video signal drive device. A first step of inputting video data, control signals (D_en, Load) and MDT control signals from an external source and storing the data in units of lines; According to the MDT control signal, video data of the current line and video data of the stored previous line are compared in clock units, and when the same is the same, the latch signal is output to the first state and the invalid data is output. And if not, outputting a latch signal to a second state and outputting pixel data of a current line. The method of claim 13, In the second step, if the MDT control signal is a signal of the first state, the video data of the current line and the stored video data of the previous line are compared in clock units, and if the same, the latch signal is output in the first state. And outputs invalid data, and if it is not the same, outputs a latch signal to a second state and outputs pixel data of a current line, and if the MDT control signal is a second state opposite to the first state, And sequentially outputs video data of the current line without comparing the data of the current line and the previous line. The method of claim 13, The invalid data is recently output data. The method of claim 13, And the control signal (D_en, Load) is delayed and output as long as the data is processed and output. A first step of receiving a latch signal, a control signal (D_en, Load), a clock signal, A second step of outputting a latch enable signal in synchronization with a clock signal in a second state without outputting a latch enable signal when the latch signal is in a first state for each pixel; A third step of sequentially primary latching data of one line from the data bus according to the latch enable signal; And a fourth step of simultaneously latching data of the first latched first line according to the control signal (Load) and outputting the data to the data line of each pixel. The method of claim 17, And latching the pixel in which the latch enable signal has not been generated in the second step by holding corresponding pixel data of the previous line. Inputting data to compare data of the current line with the previous line in pixel units and outputting invalid data if they are identical, and sequentially outputting and transmitting pixel data of the current line if they are not identical; Receiving the transmitted data and replacing invalid data with corresponding pixel data of a previous line and providing each pixel data to a corresponding data line.