JPS6232632U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is an explanatory block diagram of one embodiment of the present invention, Fig. 2 is an explanatory diagram of operation, Fig. 3 is an explanatory diagram of an embodiment of the up counter, multiple storage circuit, and arithmetic circuit, and Fig. 4 is a flow rate diagram. FIG. 1 is a differentiation circuit, 2 is an oscillator, 3 is an up counter, 4 is a multiple storage circuit, and 5 is an arithmetic circuit.

Claims (1)

[Claims for Utility Model Registration] A differentiating circuit 1 that outputs an initial pulse waveform signal, an oscillator 2 that outputs a frequency signal of a desired magnitude according to an input pulse, and a counter that is reset by the initial signal from the differentiating circuit. an up counter 3 that integrates the number of pulses P based on the oscillation pulses from the oscillator, a multiple memory circuit 4 that stores and stores the required multiple value N, and a multiple memory circuit that stores the integrated pulse number P from the up counter. An operation that performs a comparison with the multiple value N from , and continuously outputs an activation signal to the oscillator if P is different from N, and outputs an activation signal to the oscillator when P reaches the same value as N. A circuit for multiplying the number of input pulses by an integer, characterized by comprising a circuit 5.