JP2535635B2 - Phase synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A phase-locked loop circuit that receives a high-speed clock and a low-speed clock with a defined phase and generates a stable timing signal to be used inside the device, even if a disturbance occurs in the received clock. The aim is to provide a phase-locked loop circuit in which the output timing signal is not disturbed, and to receive a high-speed clock and a low-speed clock with a specified phase, use the high-speed clock as the frequency reference and the low-speed clock as the phase reference to provide the timing signal. In the phase-locked loop circuit to generate, a voltage-controlled oscillator circuit that generates a signal clock for the timing signal and whose output frequency changes according to a control voltage, and the signal clock is input, frequency-divided, and supplied to an output circuit. And a first frequency divider that outputs a high-speed phase comparison signal clock divided to the same frequency as the high-speed clock. Second frequency dividing means for inputting the high-speed phase comparison signal clock and outputting a low-speed phase comparison signal clock divided to the same frequency as the low-speed clock, and the high-speed clock and high-speed phase comparison signal clock To compare the phases and output a first control pulse having a pulse length proportional to the phase difference, and high-speed clock phase comparison means and the low-speed clock and the low-speed phase comparison signal clock to input the phase comparison. , A low-speed clock phase comparison means for outputting a second control pulse having a pulse length proportional to the phase difference, and the second control pulse inputted from the low-speed clock phase comparison means, and the pulse length of the second control pulse When the pulse length is shorter than a preset pulse length, a phase difference monitoring means for outputting a lock signal, and an unlock signal for a longer pulse length; Receives the second control pulse from slow clock phase comparing means, said first control pulse upon receiving the lock signal from the phase difference monitoring means,
Selecting means for outputting a second control pulse when an unlock signal is received; and the first means for outputting by the selecting means.
The control pulse or the second control pulse is received, integrated, and output to the voltage controlled oscillator circuit.

[Industrial applications]

The present invention relates to a phase locked loop circuit that receives a high-speed clock and a low-speed clock with defined phases and generates a stable timing signal for use inside the device.

In a transmission device used for communication service, a stable high-speed (for example, 64 kHz) clock and a low-speed (for example, 8 kH) are supplied from a clock supply device provided in a station in which the transmission device is installed.
It is common to receive the clock of z). The two clocks are used to define the phase, the high-speed clock is used to specify the frequency, and the low-speed clock is used to specify the absolute phase.

In accordance with the roles of the two clocks, the conventional phase locked loop circuit generates a signal clock for creating a timing signal necessary for output, adjusts the phase of the signal clock using a high-speed clock, A circuit in which a counter that counts a signal clock and supplies a count value to an output circuit is periodically initialized with a low-speed clock is common.

However, the above method has a problem that the counter is disturbed by the influence of the disturbance of the low-speed clock when the disturbance of the low-speed clock occurs. Therefore, the phase synchronization circuit which is not affected by the disturbance of the supplied clock. Is needed.

[Conventional technology]

FIG. 5 is a block diagram of a conventional technique, FIG. 1 (1) is an example of a PLL (Phase Lock Loop) circuit that does not have a protection circuit, and FIG. 5 (2) is an example of a PLL circuit that has a protection circuit. .

The PLL circuit of FIG. 5 (1) generates a signal clock for the clock signal or timing signal (hereinafter, referred to as a timing signal) required for output by the voltage controlled oscillator circuit 23, and generates the signal clock. It is a circuit that outputs the clocks in synchronization with the frequency and the phase by the two clocks supplied to the PLL circuit, that is, the 64kHz clock 21 and the 8kHz clock 22.

In FIG. 5 (1), the signal clock generated in the voltage controlled oscillator circuit 23 is input to the loop counter 24 and the counter 27. The loop counter 24 counts when it receives the signal clock, and the output frequency is 64 kHz.
So that the output is sent every time a fixed number N is counted. That is, the loop counter 24 is a circuit that divides the input frequency into 1 / N so that the output frequency becomes 64 kHz. For example, if the signal clock is 12.352 MHz, N = 193.
Output 64kHz.

The output of the loop counter 24 is input to the phase comparator 25,
The phase is compared with the 64 kHz clock 21, and an output having a pulse length proportional to the phase difference is output as a control pulse. The control pulse is integrated in the integrating circuit 26, and the integrated voltage is applied as a control voltage to the voltage controlled oscillator circuit 23, and the frequency of the signal clock output from the voltage controlled oscillator circuit 23 is changed to generate the signal. 64kHz clock phase
Match the clock phase.

The signal clock output as described above is a counter
It is input to 27 and counted, and the count value is input to the decoder 28. The decoder 28 reads the count value and generates and outputs timing signals of various frequencies required by the output destination.

On the other hand, the 8kHz clock is input to the edge detection circuit 29,
The rising point (edge) of the pulse is detected and input to the reset terminal of the counter 27 to reset the counter 27. That is, the count value input to the decoder 28 is 8 kHz.
Since the clock is periodically initialized by the clock, various timing signals output from the decoder 28 are synchronized by the 8 kHz clock.

However, according to the configuration of FIG. 5 (1), when a disturbance occurs in the 8 kHz clock, the initialization timing of the counter 27 becomes irregular, and the frequency of the output timing signal is also disturbed. .

FIG. 5 (2) shows the configuration of the PLL circuit having a configuration not affected by the disturbance of the 8 kHz clock as described above. In the figure, the same parts as those in FIG. 5 (1) are indicated by the same symbols. Fig. 5 (2)
Is a P-stage protection circuit between the edge detection circuit 29 and the counter 27.
Only the insertion of 30 is different from FIG. 5 (1). Therefore, in FIG. 5 (2), the counter 27 is not immediately reset at the rising edge of the 8 kHz clock, but the pulse output from the edge detection circuit 29 at the rising edge of the clock is output by the P-stage protection circuit 30 P times. The counter 27 is reset only when continuously detected. Therefore, if the 8 kHz clock pulse is missing or if a pulse with an irregular cycle is input, the counter 27 is not reset and the counter 27 continues counting by free running, so the output timing signal is Not disturbed. However, the configuration of FIG. 5 (2) has the drawback that the P-stage protection circuit 30 is increased as hardware and, of course, it is not effective against disturbance exceeding the number of protection stages.

[Problems to be Solved by the Invention]

As described above, in the phase locked loop circuit of the prior art, the high-speed clock and the low-speed clock whose phase is specified are received,
When a timing signal is generated using the high-speed clock as the frequency reference and the low-speed clock as the phase reference, if the low-speed clock is disturbed, the output timing signal will also be disturbed, and a method to avoid the influence of the disturbance is adopted. However, there is a problem that the hardware is increased and it cannot be completely prevented.

It is an object of the present invention to provide a phase locked loop circuit in which the output timing signal is not disturbed even if the received clock is disturbed.

[Means for solving the problem]

 FIG. 1 is an explanatory view of the principle of the present invention.

In the figure, 1 and 2 are a high-speed clock and a low-speed clock whose phases are defined and are supplied to a phase-locked loop circuit, 3 is a signal clock for generating a timing signal to be output, and an output frequency is controlled by a control voltage. The variable voltage controlled oscillator circuit 4 receives the signal clock and divides the frequency,
The first frequency dividing means 5 supplies the high speed clock 1 with the same frequency as that of the high speed clock 1 and outputs the high speed phase comparison signal clock. Second frequency dividing means for outputting a low-speed phase comparison signal clock divided to the same frequency as 2, 6 is inputted with the high-speed clock 1 and the high-speed phase comparison signal clock, compares the phases, and is proportional to the phase difference A high-speed clock phase comparison means for outputting a first control pulse having a pulse length of 7 pulse, a low-speed clock 2 and a low-speed phase comparison signal clock are input to compare phases, and a second pulse length is proportional to the phase difference. Low-speed clock phase comparison means 8 for outputting the control pulse, and 8 receives the second control pulse from the low-speed clock phase comparison means 7, and the second control pulse has a preset pulse length. Lock signal is shorter than the pulse length,
Phase difference monitoring means that outputs an unlock signal when the length is long,
9 receives the first control pulse from the high-speed clock phase comparing means 6 and the second control pulse from the low-speed clock phase comparing means 7, and receives the lock signal from the phase difference monitoring means 8 to receive the first control pulse. Selecting means for outputting a second control pulse when the control pulse and the unlock signal are received;
An integrating circuit 10 receives the first control pulse or the second control pulse output from the selecting means 9, integrates it, and outputs it to the voltage controlled oscillation circuit 3.

[Work]

The phase-locked loop circuit of FIG. 1 is a circuit that receives a high-speed clock 1 and a low-speed clock 2 with defined phases, and generates a timing signal using the high-speed clock 1 as a frequency reference and the low-speed clock 2 as a phase reference. .

In FIG. 1, the voltage controlled oscillator circuit 3 generates a signal clock for generating the timing signal,
The signal clock is input to the first frequency dividing means 4, the frequency of which is appropriately divided, the signal clock is sent to an output circuit (not shown), and is output as a necessary timing signal. At the same time, the first frequency dividing means 4 outputs a high-speed phase comparison signal clock whose frequency is the same as that of the high-speed clock 1.

The high-speed phase comparison signal clock is input to the high-speed clock phase comparison means 6, the phase is compared with that of the high-speed clock 1, and a pulse having a pulse length proportional to the phase difference is output as a first control pulse. The high-speed phase comparison signal clock is also input to the second frequency dividing means 5, further divided into pulses having the same frequency as the low-speed clock 2, and output as a low-speed phase comparison signal clock. The low-speed phase comparison signal clock is input to the low-speed clock phase comparison means 7 to be compared in phase with the low-speed clock 2 and a pulse having a pulse length proportional to the phase difference is output as a second control pulse.

The above first and second control pulses are output to the selection means 9, but the second control pulses are simultaneously output to the phase difference monitoring means 8
And the pulse length of the second control pulse is compared with a preset pulse length. As a result of the comparison, the phase difference monitoring means 8 outputs a lock signal to the selecting means 9 when the pulse length of the second control pulse is shorter than a preset pulse length, and an unlock signal when the pulse length is longer than the preset pulse length. .

As described above, the first and second control pulses are input to the selecting means 9, but when the lock signal is received from the phase difference monitoring means 8, the first control pulse and the unlock signal are input. When it is received, switching is performed so as to output the second control pulse. The first or second control pulse output from the selecting means 9 is input to the integrating circuit 9 and changes the output voltage of the integrating circuit 9 according to the pulse length of the control pulse. The frequency of the output signal clock is changed by the output voltage, and a timing signal is generated with the high-speed clock 1 as the frequency reference and the low-speed clock 2 as the phase reference.

If a disturbance occurs in the low-speed clock 2 during control by the first control pulse, the phase difference monitoring means 8 detects this and the low-speed clock phase comparison means 7 is applied to the filter 10 via the selection means 9. The connection is made and thereafter the phase is adjusted by the low speed clock 2 until the phase matches the low speed clock 2.

In the present invention, the signal clock whose phase is adjusted by the two phase comparing means as described above is supplied to the first frequency dividing means 4 connected to the output circuit, and the first frequency dividing means 4 is supplied.
Is not reset by the low-speed clock 2. Therefore, even if the low-speed clock 2 is disturbed, the first frequency dividing means 4 is not immediately reset, but the phase comparing means is switched to the low-speed clock phase comparing means 7 as described above, and the integrating circuit 10 and the voltage controlled oscillator circuit are changed. Since the phase is gradually adjusted via 3, the signal clock sent to the output circuit does not change abruptly due to the disturbed low-speed clock 2, and the timing signal supply destination is not greatly affected. .

〔Example〕

2 is a circuit block diagram of one embodiment of the present invention, FIG. 3 is a time chart of one embodiment of the phase comparison operation of the present invention,
FIG. 4 is a time chart of an embodiment of the phase difference monitoring operation of the present invention.

In the figure, 11 is a 64 kHz clock, 12 is an 8 kHz clock, 13 is a voltage controlled oscillator circuit, 14 is a loop counter, 15 is a 1/8 frequency divider circuit, 16 is a phase comparator for 64 kHz, 17 is a phase comparator for 8 kHz, 18 is a phase difference monitoring circuit, 19 is a phase comparator selector, 20
Is an integrator circuit, FF _1A , FF _2A , FF _1B , FF _2B is a flip-flop, INV _1A , INV _2A , INV _1B , INV _2B , INV ₃ is an inverter, AN
D ₁ to AND ₄ are AND circuits, NAND ₁ to NAND ₂ are NAND circuits, 3SB _{1 to} 3
SB ₂ is a 3-state buffer, R _{1 to} R ₂ are resistors, and C is a capacitor. Also, in FIG.
This is the point where the waveform is illustrated in the time chart of the figure.

Hereinafter, FIG. 2 will be described in combination with FIG. 3 and FIG.

FIG. 2 shows that the voltage-controlled oscillator circuit 3 generates a signal clock for generating a timing signal necessary for output, and the signal clock is supplied with two clocks, that is, a 64 kHz clock. This is a circuit that synchronizes the frequency and phase with the 1 and 8 kHz clock 2 and outputs.

In FIG. 2, the signal clock generated in the voltage controlled oscillator 3 is input to the loop counter 14 and counting is performed. The count value is output to a decoder (not shown), and a timing signal having a required frequency is generated and output in the decoder. Further, the loop counter 14 also serves as a 1 / N frequency dividing circuit, and a fixed number N
The output is sent to the 64 kHz phase comparator 16 and the 1/8 frequency dividing circuit 15 each time the frequency is counted.
It is set to be kHz.

The 64 kHz pulse output from the loop counter 14 is a 64 kHz phase comparison pulse, and a 64 kHz phase comparator.
The pulse is input to 16 and the phase is compared with the 64 kHz clock 11, and a pulse having a pulse length proportional to the phase difference is output as the first control pulse, which will be described below with reference to FIG.

Now, assuming that the phase of the 64 kHz clock 11 (hereinafter referred to as the clock) is ahead of the 64 kHz pulse (hereinafter referred to as the pulse) output from the loop counter 14,
First, the clock turns on (rises) and flips.
It is input to the CK of the flop FF _1A and Q is turned on. Then, when the pulse is turned on, the R of the flip-flop FF _1A is turned on.
Is input to the flip-flop FF _1A to be reset. Therefore, during this period, a pulse is sent from -1 to Q, but the length (width) of the pulse is the same as the difference between the rising timing of the clock and the pulse, as shown in FIG. At this time, the flip-flop FF _2A does not output the output because the reset is input first.

On the contrary, when the clock lags behind the pulse, a pulse is sent to -2 from Q of the flip-flop FF _2A by the same operation as shown in FIG. 3 (2).
No output is output from flip-flop FF _1A . When the pulse and clock phases are exactly the same,
As shown in FIG. 3 (3), no output is sent from either of the flip-flops FF _1A and FF _2A .

As described above, the control pulse is output from the -1 or -2 of the 64 kHz phase comparator 16 to the phase comparator selector 19, but at this stage it is not used for the phase control.

On the other hand, the output pulse from the loop counter 14 is input to the 1/8 divider circuit 15 and divided by 1/8, and the 8 pulse for 8 kHz phase comparison is output.
The pulse of kHz is input to the 8 kHz phase comparator 17, and the phase is compared with the 8 kHz clock 12 (hereinafter referred to as clock). The comparison method and output are the same as those of the 64 kHz phase comparison shown in FIG.
A pulse having a pulse length proportional to the phase difference is output to the phase comparator selector 19 as the second control pulse.

At this time, the output from -1 or -2 of the 8 kHz phase comparator is sent to the phase difference monitoring circuit 18 at the same time and the coincidence status of the phases is monitored. Although details of the phase difference monitoring circuit 18 are omitted, the operation thereof will be described with reference to FIG.

In the phase difference monitoring circuit 18, as shown in FIG. 4, if the clock rising point T ₀ is within a certain time range before and after the pulse rising point T ₁ (the range shown by the mesh in FIG. 4). Judging that the phase of the pulse and the clock match, assuming that the phase of 8kHz is in the locked state, the subsequent phase control is performed by the phase comparator for 64kHz, but if it is out of the mesh range, the unlocked state is 8kHz. Phase control by. FIG. 4 (1) shows the 8 kHz phase unlocked state described above, and FIG. 4 (2) shows the 8 kHz phase locked state.

In the example of FIG. 4 (1), the rising point of the 8 kHz clock 12 (clock) is higher than the rising point T _{1 of the} 8 kHz phase comparison pulse (pulse) output from the 1/8 frequency divider circuit 15 of FIG.
T ₀ is much advanced, and as described above, the 8 kHz phase comparator 17 outputs a control pulse having a time length of | T ₀ −T ₁ | to −1. In this unlocked state, "1" (H level signal) is output as an unlock signal to the phase difference monitoring circuit 18 of FIG. (Note that if the clock lags behind the pulse by a large amount, -2
, Except that a control pulse with a time length of | T ₀ −T ₁ |
The same as above. ) "1" of the unlock signal is input to the phase comparator selector 19 and the gates of AND ₁ and AND ₂ are opened, so that the control pulse from the 8 kHz phase comparator 17 receives the integration circuit via NAND ₁ or NAND _2. Sent to 20. In the example of FIG. 3 (1), since the clock is ahead of the pulse, the control pulse (H level signal) output to -2 is converted to L level in the NAND ₁ and 3SB _{1 of the} integrating circuit 20. Entered in.
The voltage connected to the 3SB ₁ while this input continues
V _B is sent to the loop filter circuit and charges the capacitor C via the resistor R ₁ .

The oscillation frequency of the voltage controlled oscillator circuit 13 is controlled by the terminal voltage of the capacitor C. In this case, the capacitor C
Voltage controlled oscillator circuit
The oscillation frequency of 13 becomes high. As a result, the phase of the pulse that was delayed from the 8 kHz clock advances forward,
The length of the control pulse sent from -1 gradually becomes shorter, and eventually the clock enters the mesh of FIG. 4 centering on the rising point T _{1 of the} pulse. When both the rising edges of the clock and the pulse enter the mesh, the unlock signal ("1") changes to the lock signal ("0").

When the lock signal “0” is output from the phase difference monitoring circuit 18, the gates of AND ₃ and AND ₄ are opened via INV ₃ in the phase comparator selector 19, so that the control pulse from the 16 kHz phase comparator 16 Via NAND ₁ or NAND ₂
Sent to

FIG. 4 (2) shows a time chart in the locked state. In this case, the control pulse (not shown in FIG. 3 (2)) having a time length of | T ₀ −T ₁ | of the difference between the rising edge of the 8 kHz clock and the pulse is output from -1, but the phase comparator selector There are 64 control pulses that are blocked at 19 and have a time length equivalent to the phase difference between the 16 kHz clock and the pulse.
The signal is sent from the -1 or -2 of the kHz phase comparator 16 to the integrating circuit 20 via the phase comparator selector 19. In the example of FIG. 4 (2), since the pulse is ahead of the clock, the control pulse for controlling the delay direction is sent to -2. As a result, 3SB ₂ operates in the integrator circuit 20 to send ground air to the capacitor C via the resistor R ₂ so that the capacitor C discharges and lowers the terminal voltage. Is controlled so that the pulse approaches the 16 kHz clock.

Even if the phase of the 8kHz clock 12 is shifted while the phase is controlled by the 64kHz clock 11, the phase comparison with the 8kHz clock 12 is always performed. Since it is sent to 18, if the phase shift becomes large, it will be switched to the phase control by the 8kHz clock again and the phase will be adjusted.

As described above, in the present invention, first, the phase comparator for 8 kHz is used.
Phase control is performed by 17 and 64kH when the phases match
Since it is switched to the phase control by the z phase comparator 16,
It is possible to create a timing signal whose phase is exactly the same as kHz and whose frequency is 64 kHz.

As is apparent from the above embodiment, the present invention requires two sets of phase comparators and a phase comparator selector 19, but has a very simple structure and the counter 27 required in the prior art shown in FIG. Since the edge detection circuit 29 or the P-stage protection circuit 30 is not necessary, the overall economy can be achieved.

Even if the 8kHz clock 12 is disturbed, the
Hz phase comparator 17, phase comparator selector 19, integrating circuit 20
Since the phase is adjusted via the voltage-controlled oscillation circuit 13, the phase does not change abruptly, and therefore the count value of the loop counter 14 does not change abruptly. That is,
Since the counter is not reset by the 8 kHz clock as in the prior art, the output circuit is not disturbed.

〔The invention's effect〕

As described above, according to the present invention, the phase control by the low-speed clock and the switching to the phase control by the high-speed clock are performed so that the low-speed clock and the high-speed clock have the same phase, and the high-speed clock and the frequency have the same stable timing. The signal can be created at low cost, and the counter directly connected to the output circuit is driven by the phase control result without being reset by the low-speed clock, so that even if the low-speed clock is disturbed, the output circuit is not disturbed. This makes it possible to contribute to the economicalization and stabilization of the phase synchronization control circuit.

[Brief description of drawings]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a circuit block diagram of an embodiment of the present invention, FIG. 3 is a time chart of an embodiment of the phase comparison operation of the present invention, and FIG. 4 is a phase difference monitoring operation of the present invention. An example time chart, FIG. 5 is a block diagram of the prior art. In the figure, 1 ... High-speed clock 2 ... Low-speed clock 3 ... Voltage-controlled oscillation circuit 4 ... First frequency dividing means 5 ... Second frequency dividing means 6 ... High-speed clock phase comparison means 7 ... Low-speed Clock phase comparison means 8 ... Phase difference monitoring means 9 ... Selection means 10 ... Integrating circuit.

Front Page Continuation (72) Inventor Hozumi Sasaki 2-2-1 Ichibancho, Aoba-ku, Sendai City, Miyagi Prefecture Fujitsu Tohoku Digital Technology Co., Ltd.

Claims (1)

(57) [Claims] 1. A high-speed clock (1) and a low-speed clock (2) having a defined phase are received, and a timing signal is generated using the high-speed clock (1) as a frequency reference and the low-speed clock (2) as a phase reference. In the phase locked loop circuit, a voltage controlled oscillator circuit (3) that generates a signal clock for the timing signal and whose output frequency changes according to a control voltage, and an input circuit that divides the signal clock by inputting it And a first frequency dividing means (4) for outputting a high-speed phase comparison signal clock divided to the same frequency as the high-speed clock (1), and inputting the high-speed phase comparison signal clock. Second frequency dividing means (5) for outputting a signal clock for low-speed phase comparison, which is divided into the same frequency as the low-speed clock (2), and the high-speed clock (1) and the signal clock for high-speed phase comparison And a low-speed clock (2) and a low-speed phase comparison signal clock, which outputs a first control pulse having a pulse length proportional to the phase difference. Low-speed clock phase comparison means (7) for inputting and comparing phases and outputting a second control pulse having a pulse length proportional to the phase difference, and the second control pulse from the low-speed clock phase comparison means (7) And a phase difference monitoring means (8) for outputting a lock signal when the pulse length of the second control pulse is shorter than a preset pulse length and an unlock signal when the pulse length is longer than the preset pulse length, and the high-speed clock phase comparison means. When the first control pulse is input from (6) and the second control pulse is input from the low speed clock phase comparison means (7), and the lock signal is received from the phase difference monitoring means (8), the first control pulse is input. , Selecting means (9) for outputting a second control pulse when receiving a lock-up signal, and receiving and integrating the first control pulse or the second control pulse output from the selecting means (9). Comparing the high-speed clock phase when the phase difference between the signal clock output from the voltage-controlled oscillation circuit (3) and the low-speed clock (1) is small, comprising an integration circuit (10) that outputs to the voltage-controlled oscillation circuit (3) The first control pulse from the means (7) and the second control pulse from the low speed clock phase comparison means (6) when the phase difference is large, the voltage controlled oscillator circuit (3).
A phase synchronization circuit characterized by controlling the.