KR950007435B1 - Clock recovery circuit - Google Patents

Abstract

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Description

Clock recovery circuit

1 is a block diagram of a known PLL.

2 is a block diagram of a conventional clock recovery circuit.

3 is a block diagram of a clock recovery circuit according to the present invention.

4 is a circuit diagram of one embodiment according to FIG.

FIG. 5 is a waveform diagram for describing FIG. 4. FIG.

* Explanation of symbols for main parts of the drawings

10: PLL (Phase Locked Loop) 100: Edge detection unit

101: first flip-flop 102: second flip-flop

103: AND gate 200: PLL input clock generator

201: Inverter 202: First Counter

203: second counter.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a clock recovery circuit for recovering a clock from data for receiving data to be transmitted and extracting data on a transmission side. The present invention relates to a circuit capable of accurately recovering a clock even in case of non-return to zero (NRZ) data that may have a stream.

In general, in a digital communication system, a phase detector 12, a low pass filter 13, a voltage controlled oscillator 14, and a divider 15 as shown in FIG. A PLL circuit composed of

Such a PLL circuit is not suitable for extracting a clock from NRZ data transmitted serially at high speed, which is due to the characteristics of the NRZ data.

Among several prior arts for solving this drawback, a clock recovery circuit as shown in FIG. 2 is disclosed in US Pat. No. 4,787,097, which was invented by Raymond P. Rizza.

The patent is a method of controlling a restored clock output through a known PLL circuit as shown in FIG. 1 to operate within a predetermined frequency range by a monitor circuit and a recovery circuit.

Referring to FIG. 2, an output pulse output from the voltage controlled oscillator 14 of the PLL 10 and a predetermined reference clock are input to the exclusive logic sum gate XOR 31 in the monitoring circuit 30.

The XOR 31 detects and outputs a sum or difference between the output pulse of the PLL 10 and the reference clock as a discrete detection signal.

The discrete detection signal is applied to a low pass filter (LPF) 32 to remove a high frequency component, thereby forming a continuous signal (voltage of DC component) having a frequency difference between the PLL output pulse and the reference clock.

The continuous signal is output as a discrete signal by comparator 33 for comparing inputs with a predetermined DC voltage and applied to phase and frequency detector 34 via line 37.

On the other hand, the reference clock applied to the divider 36 is frequency-divided according to the set frequency bandwidth of the supervisory circuit 30 and applied to the phase and frequency detector 34 via the line 38.

The phase and frequency detector 34 compares the phase and frequency of the two signals input through the lines 37 and 38.

Here, for example, if the signal of the line 37 has a higher frequency than the signal of the line 38, the frequency difference between the output pulse of the PLL 10 and the reference clock is outside the set frequency bandwidth. This means that the PLL 10 is operated outside of a predetermined frequency bandwidth.

Therefore, when the PLL 10 is operated outside the predetermined frequency bandwidth, the retriggerable multivibrator 35 in the monitoring circuit 30 operates to operate the PLL 10 within the predetermined frequency bandwidth. The inhibit control signal INHIBIT is outputted to the phase detector 12 in the PLL 10 via the line 39.

Therefore, the phase detector 12 is turned off by the prohibition control signal INHIBIT. At this time, the phase and frequency detector 21 in the recovery circuit 20 is enabled to operate.

On the contrary, if the signal of the line 37 has a lower frequency than the signal of the line 38, the frequency difference between the output pulse of the PLL 10 and the reference clock is within the predetermined frequency bandwidth.

This means that the PLL 10 is phase locked. In this case, the retriggerable multi-vibrator 35 outputs the inverted control signal INHIBIT through the line 39.

Accordingly, the phase detector 12 is enabled and operated, and the phase and frequency detector 21 in the recovery circuit 20 is turned off to stop operation.

Therefore, the circuit as described above continuously monitors the clock of the NRZ data input through the monitoring circuit 30, and when the phase synchronization is not corrected, the PLL (within the frequency range predetermined by the recovery circuit 20). 10) can be seen that the way to control to operate.

However, in the conventional circuit as described above, since the output of the reference clock and the PLL oscillated by the oscillator installed inside or outside is monitored by the monitoring circuit, the synchronization is synchronized by the recovery circuit, and thus the time for synchronizing the synchronization is delayed. In addition, the hardware configuration for monitoring the output pulse of the PLL is also very complicated.

In addition, since the phase and frequency detectors 41 in the phase detector 12 or the recovery circuit 20 are selectively switched as a prohibition control signal, the input data and the feedback control of the voltage controlled oscillator 14 are fed back. Time delay between signals occurs, resulting in a very unstable clock.

Therefore, since the data of the transmitting side is extracted by the unstable clock, it is obvious that it is difficult to accurately restore the data.

This phenomenon causes a very serious problem when the input data is high speed transmission.

Accordingly, it is an object of the present invention to provide a clock recovery circuit that can increase the reliability of a system by allowing an accurate clock to be recovered from input data.

Another object of the present invention is to provide a clock recovery circuit having a simple configuration.

It is still another object of the present invention to provide high-speed NRZ data in which data strings of logic "1" or "0" are contiguous for more than a few bits, not input data being a state in which logic "1" or "0" is continuously alternating. In this case, the present invention provides a clock recovery circuit that can recover a clock exactly synchronized with the input data.

According to the present invention for achieving the above object, a known PLL including a phase and frequency detector, a low pass filter, a voltage-controlled oscillator, and the rising or falling edge of the input data to a reference clock preset inside or outside. Edge detection means for outputting edge detection pulses of the data detected and input by the PLL input, and a PLL input applied to a phase and frequency detector in the PLL by inputting the edge detection pulses of the edge detection means and counting the reference clock. PLL input clock generating means for generating a clock is provided.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a clock recovery circuit according to the present invention, which detects rising or falling edges of input data to be transmitted by a preset reference clock therein and outputs an edge detection pulse of the input data. PLL input for generating a PLL input clock applied to the phase and frequency detector 12 in the PLL 10 by counting the reference clock according to an edge detector 100 and the edge detection pulse of the edge detector 100. The clock generator 200 and the PLL input clock output from the PLL input generator 200 and the output pulses fed back from the voltage controlled oscillator 14 are inputted to reduce the phase difference between the two clocks. It consists of a well-known PLL 10 which produces an output pulse.

4 is a detailed view of a preferred embodiment according to FIG. 3, wherein the edge detector 100 includes a first flip-flop 101, a second flip-flop 102, and an end gate 103. An example in which the clock generator 200 includes an inverter 201, a first counter 202, and a second counter 203 is illustrated.

5 is a waveform diagram of each circuit part according to FIG. 4.

Hereinafter, the dynamic relationship based on the above-described configuration of the present invention will be described in detail according to the embodiment.

FIG. 5 shows that an NRZ data having a transmission rate of 32 Kbps equal to the (51) waveform is applied to the input terminal D of the first flip-flop 101 through the line A of FIG. The first flip-flop 101 and the second through the line B as a reference clock preset at a frequency of 8.192 MHz, such as the (52) waveform output from [Temperature Compensated X-tal Oscillator (TCXO)], etc. When applied to the clock terminal CK of the flip-flop 102, the first flip-flop 101 detects the rising edge of the NRZ data according to the reference clock and outputs it to the output terminal (Q). Accordingly, the waveform 53 of FIG. 5 appears in the output line C of the first flip-flop 101.

The second flip-flop 102 latches the detection output of the output line C of the first flip-flop 101 according to the reference clock, and outputs the detected output to the output terminal Q.

Accordingly, a waveform of (54) appears in the output line D of the second flip-flop 102.

The AND gate 103 logically multiplies the two waveforms shown in the lines C and D to output an edge detection pulse, such as the waveform 55 of FIG. 5, to the output line E. FIG.

Here, although the embodiment of the edge detection means is composed of the D-flip flops and the end gate, it should be understood that the present invention is not limited thereto and may be implemented as other logic elements.

The edge detection pulse shown in the output line E of the AND gate 103 is input to the master reset (MR) terminal of the first and second counters 202 and 203 in the PLL input clock generator 200. Here, the first counter 202 and the second counter 203 are four stages of a ripple counter.

In this case, the first and second counters 202 and 203 are 256 binary counters which are operated as eight-step ripple counters by being connected to each other in a subordinate manner, and from the time when the detection pulse is applied to the master reset stage MR, the clock stage CK. It divides 256 reference clocks of 8.192MHZ inputted into and outputs 32KHZ divided clocks through the output line (F). In the absence of a reset signal, free running counting results in 32KHZ output.

Therefore, the PLL input clock generator 200 divides the reference clock 256 from the time point at which the edge detection pulse detected by the edge detector 100 and the line E is input, is input through the output line F. Output to the phase and frequency detector 12 of the PLL (10). On the other hand, since the edge detection pulse is edged on the rising or falling of the data input to the edge detector, the 32KHZ divided clock output to the output line (F) becomes an output signal almost in phase with the input data. The waveform shown in the output line F becomes the waveform (56) of FIG.

Importantly, when an edge detection pulse such as the waveform (55) of FIG. 5 is input to the master reset (MR) terminal of the first counter 202 and the second counter 203 during the counting operation by 256 divisions, It should be understood that the first and second counters 202 and 203 stop the counting operation and are reset.

The reference clock of 8.192MHZ, which is inverted by the inverter 201 and input to the clock stage CK of the first counter 202, is a signal independent of the NRZ data input at 32Kbps but corresponds to the frequency of 32Kbps. Since it is a signal having a frequency of 256 times of 32KHz, it can be seen that the PLL input clock generator 200 is a very important signal for generating the PLL input clock applied to the phase and frequency detector 12 in the PLL 10. Will be. The inverter 201 is an element for inverting the reference clock due to the characteristics of the first and second counters 202 and 203.

In the present embodiment, the first and second counters 202 and 203 may be simply configured as a commercial IC "74LS393", but it should be understood that the first and second counters 202 and 203 may be implemented as other addressers.

Accordingly, the 32 KHz clock, which is the (56) waveform of FIG. 5 shown in the output line F of the PLL input clock generator 200, is applied to one side input of the phase and frequency detector 12 of the PLL 10. do.

The phase and frequency detector 12 of the PLL 10 is fed back from the PLL input clock generated by the PLL input clock generator 200 and the voltage controlled oscillator 14 of the PLL 10. Then, the output pulses output through the divider 15 are compared and input, and the pulse corresponding to the difference is applied to the LPF 13. Therefore, the pulse applied to the LPF 13 becomes a DC voltage in which high frequency components are removed by the LPF 13, and is supplied as a control voltage of the VCO 14.

The VCO 14 changes the output frequency according to the control voltage. The VCO 14 oscillates toward a smaller phase difference between the two inputs applied to the phase and the input of the frequency detector 12, and is synchronized with the NRZ data. It outputs an accurate clock such as the waveform (57) of FIG.

In the clock recovery circuit according to the present invention operated as described above, the clock which is the output pulse of the PLL 10 and the PLL input clock generated by the PLL input clock generator 200 have the same duty. By being a clock signal, it is possible to recover a very stable clock and to accurately extract data on the transmission side. Therefore, the reliability of the system is improved, and the circuit configuration is simpler than that of the conventional clock recovery circuit, and the circuit can be implemented at low cost.

As described above, although a preferred embodiment of the present invention has been illustrated and described in the drawings, those skilled in the art can understand that various changes and modifications can be made without departing from the basic aspects of the present invention. will be. For example, the edge detection means described above may be implemented by another delay means, and the PLL input clock generating means may also be provided as another element.

In addition, although the above-described input data has been described assuming NRZ data, it can be seen that the present invention is not limited to NRZ data but also applicable to RZ (Return to Zero) data, and the like, and is applicable to not only a data communication system but also an optical communication system. Can be.

As described above, the present invention has the advantage of restoring a clock synchronized exactly with the data to be transmitted, thereby improving the reliability of the system and providing a compact circuit configuration.

Claims (10)

A clock recovery circuit of a digital communication system for recovering a clock from input data transmitted with a PLL including a phase and frequency detector, a low pass filter, and a voltage controlled oscillator, the rising or falling edge of the input data therein. Edge detection means for detecting an edge detection pulse of the input data by detecting by a preset reference clock; and counting the reference clock by inputting the edge detection pulse of the edge detection means to detect the phase and frequency detector in the PLL. And a PLL input clock generating means for generating a PLL input clock applied to the clock recovery circuit. The first delay element of claim 1, wherein the edge detection means outputs a first detection signal in which the rising or falling edge of the input data is detected at the rising edge of the preset reference clock. A second delay element for outputting a second detection signal by latching the first detection signal in accordance with the predetermined reference clock, and logic for outputting the edge detection pulse by logically combining the 1-2 detection signal; Clock recovery circuit, characterized in that consisting of elements. The clock recovery circuit of claim 1, wherein the PLL input clock generating means comprises a counting element for counting the predetermined reference clock by a predetermined coefficient after being reset according to an edge detection pulse of the edge detecting means. . The first delay element of claim 1, wherein the edge detection means outputs a first detection signal in which the rising or falling edge of the input data is detected at the edge of the preset reference clock. A second delay element for outputting a second detection signal by latching the first detection signal in accordance with the predetermined reference clock, and logic for outputting the edge detection pulse by logically combining the 1-2 detection signal; And a counting element for counting the predetermined reference clock by a predetermined coefficient at the time when the PLL input clock generation means is reset according to the edge detection pulse of the edge detection means. . 5. The clock recovery circuit according to claim 2 or 4, wherein the clock delay circuit comprises the first delay element and the second delay element flip-flop. The clock recovery circuit according to claim 2 or 4, wherein the logic element is composed of an AND gate. 5. The clock recovery circuit according to claim 2 or 4, wherein the first delay element and the second delay element are configured as D-flip flops, and the logic elements are configured as an AND gate. 5. The clock recovery circuit according to claim 3 or 4, wherein the counting element comprises a counter for counting a predetermined reference clock with 256 coefficients to apply the PLL input clock to the phase and frequency detector. The clock recovery circuit of claim 4, wherein the input data applied to the first delay element is NRZ data. Clock recovery circuit of a digital communication system for recovering a clock from NRZ input data transmitted with a PLL 10 including a phase and frequency detector 12, a low pass filter 13, and a voltage controlled oscillator 14 An input terminal D is connected to an input of NRZ input data and a clock terminal CK is connected to a preset reference clock to output the first detection signal delayed-synchronized with the NRZ input data according to the reference clock. An input terminal D is connected to a first flip flop 101 and a first detection signal of the first flip flop 101, and a clock terminal CK is connected to the preset reference clock to provide the first detection signal. The second flip-flop 102 for outputting the second detection signal synchronized with the delayed delay according to the reference clock, and the first detection signal and the second detection signal are ANDed to detect the NRZ input data and the rising edge. Edge detection pulse An output of the AND gate 103, an inverter 201 for inputting and inverting the reference clock, and a master reset (MR) terminal connected to an output of the AND gate 103 and inverted in the inverter 201. When the clock terminal CK is connected to a reference clock and the edge detection pulse is applied, the reference clock is divided by a predetermined coefficient and applied to one side input of the phase and frequency detector 12 in the PLL 10. And a counting element (202, 203) for the clock recovery circuit.