JPS61134125A - Lock detecting circuit of frequency synthesizer system channel selecting device - Google Patents

Abstract

PURPOSE:To obtain a lock detecting circuit not influenced by dispersion of manufacture and temperature by providing a charge transferring circuit that stores and transfers charge in each capacity by a clock and a comparing and judging device that compares the stored charge of the final stage capacity of above-mentioned circuit with a specified value. CONSTITUTION:A capacity 61 is connected between a terminal of a switch S2 and the ground, and a capacity 62 of n times (n is a positive number) the capacity 61, is connected between the another terminal and ground. A logical circuit 70 that outputs clocks, corresponding to difference in frequency or difference in phase between a divided signal of an office signal and a reference frequency signal in number is constituted of circuits 56-59. A charge transferring circuit 80 that stores the transfers charge successively by switches S1, S2 opened and closed by clocks phi, -phi is formed in capacities 61, 62. The charge stored in the final stage capacity 62 of the charge transferring circuit 80 is compared with a specified value by an NOT circuit 60 and thereby a comparing and judging device that detects lock of a phase lock loop is constituted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a PLL (Phase Lock) for digital tuning systems for TVs, VTRs, radios, etc.
The present invention relates to a lock detection circuit of a frequency synthesizer type tuning device, which detects whether or not a PLL is locked in a circuit that controls a tuning system using edLoop.

[Conventional technology]

Traditionally, receivers received broadcast stations by obtaining the desired local oscillation frequency by turning a variable capacitor, but in recent years,
In terms of cost reduction, easy operability, and stability of tuning, there is a shift toward electronic tuning systems that perform tuning digitally, and digital tuning systems using phase-locked loops (hereinafter abbreviated as PLL) are becoming more and more popular. It has been adopted.

FIG. 4 shows a block diagram of a standard PLL digital tuning system. In the figure, 1 is an antenna, 2 is a high frequency amplifier, 3 is a mixer, 4 is an intermediate frequency amplifier, 11 is a crystal oscillator, 12 is a reference frequency divider, 13 is a phase comparator, 14 is a low-pass filter, and 15 is a voltage control An oscillator, 16 a prescaler, 17 a programmable counter, 20 a PLL loop constituted by the above 11 to 17, 21 a lock detection circuit for detecting lock of the PLL loop 20, and 22 a key for manually inputting the reception frequency. An operation unit, 23 is a display unit that displays the reception frequency, 24
30 is the controller and memory for controlling the programmable counter 17 and the display unit 23; 30 is the controller 21 to 24 mentioned above;
This is a control section composed of. A portion surrounded by a dashed line in the figure constitutes a local oscillation circuit and a control section 10 configured using a PLL system.

Next, the operation will be explained based on this block diagram. Oscillation frequency FO of the voltage controlled oscillator (hereinafter abbreviated as VCO) 15, which is the local oscillator of this tuning system
is divided by 1/P by the prescaler 16 to reduce the frequency to a frequency at which the programmable counter can operate, and further by the programmable counter 17 to reduce the frequency to L/N.
The frequency is divided, and the frequency-divided output FS becomes the comparison input of the phase comparison 813. On the other hand, the oscillation signal of the crystal oscillator 11 is frequency-divided by the reference frequency divider 12 to become the comparison reference frequency FR, and this and the frequency-divided output FS are compared by the phase comparator 13, and the comparison output is the low $ The signal is output to a pass filter (hereinafter abbreviated as LPF) 14, and its DC output voltage is fed back to the VCO 15.

The voltage controlled oscillation frequency of VC:O15 (assuming that the comparison reference frequency of the phase comparator 13 is FR) is expressed by the following equation.

F O-F RX P X N -(
1) Therefore, by controlling the frequency division number N of the programmable counter 17 by the control unit 30,
A desired local oscillation frequency can be obtained.

The outline of the operation of the PLL has been explained above, and the phase comparator will be explained using FIG. 5. In FIG. 5, if the signal of the comparison reference frequency FH from the reference branching unit and the signal of the comparison frequency FS from the programmable counter are input to the phase comparator 13, and their outputs are DP and DN, then the DP of the phase comparator 13 is The output terminal is a P-channel insulated gate field effect transistor (PMO) whose source is connected to the positive power supply.
The DN output terminal is connected to the gate of an N-channel insulated gate field effect transistor (hereinafter abbreviated as NMO3) Nl whose source is connected to ground.

Further, the connection terminals of the drain of PMO3Pi (7) and the drain of 8MO3Nl are both connected to the input terminal of the LPF 14, and the DP output terminal and the DN output terminal are respectively connected to two input terminals of the lock detection circuit 21, and the lock detection circuit 21 is connected to the input terminal of the lock detection circuit 21. The output terminal of the circuit 21 is input to a control section 30 shown in FIG.

Next, the operation will be explained.

The phase comparator 13 compares the phases of the comparison reference frequency FR and the comparison frequency FS divided by the programmable counter 17, and generates an error signal according to the phase difference. If the comparison frequency FS is lower in frequency or delayed in phase than the comparison reference frequency FR, the DP output terminal will be at the "L" level and the DN output terminal will be at the 'L' level for a time corresponding to the phase difference. Therefore, at this time, PMO3PI turns ON, 8MO3Nl turns OFF, and LP
1H" is input to F14. Conversely, if FS has a higher frequency or a phase lead than FR, the DP output terminal is "H" and the DN output terminal is "H" for a time corresponding to the phase difference. becomes “H”, therefore, PMO3PI becomes 0 at this time.
FFL, 8MO3Nl is ONL, LPF14□ is “L”
” is input. And if it also matches the frequency 0 phase,
The DP output terminal becomes “H”, the DN output terminal becomes “L”,
Both PMO3PI and 8MO3N1 are 0FFL, the output is high impedance, and the PLL 20 is in a locked state.

The lock detection circuit 21 detects whether or not this F'LL 20 is in a locked state, and depending on the detection result, the control unit 30 controls the frequency division ratio of the programmable counter @
When the PLL 20, which performs control such as changing or sustaining 1/N, is not in the locked state (hereinafter referred to as unlocked state), the DP output terminal power PL" or the DN output terminal becomes 'H', which is the lock state. It is detected by the detection circuit 21.

When the comparison reference frequency is 5KHz, the unlock state time, that is, the time when the phase difference error signal is generated, is 2
If it is ~3 μs or less, the screen on a cathode ray tube such as a TV will change, but this change cannot be confirmed with the human eye, so there is no need to control the loop to lock with the controller. Furthermore, 2 to 3μ
If the controller detects an error signal that is less than Or, it may take longer than necessary to lock the device.

Therefore, it is necessary to take measures to prevent the lock detection circuit from detecting error signals with a phase difference of 2 to 3 μS or less. A conventional example of such a lock detection circuit is shown in Fig. 6.
In the figure, the DP output terminal of the phase comparator 13 is connected to NAND
It is connected to one input terminal of the circuit 41, and the DN output terminal of the phase comparator 13 is connected to the NAND circuit 4 via the NOT circuit 42.
The output terminal of the NAND circuit 41 is connected to the input terminal of a NOT circuit 43 via a resistor 44, and its output terminal is connected to the controller 24 as an output terminal of the lock detection circuit 21. Also, NOT circuit 43
A capacitor 45 is connected between the input terminal and ground.

Next, the operation of this conventional circuit will be explained. When the DP output terminal of the phase comparator 13 outputs the Lj signal for a period of 3 μs, PMO5PI is turned on for 3 μs, and LPF1
4, a 3 μs error signal is input. On the other hand, at this time, D
Since the N output terminal is at "L", the output terminal of the NAND circuit 41 is at "H" for a period of 3 μs. Here, NOT circuit 4
The input transition voltage VB of No. 3 is set to, for example, half of the positive power supply (VDD), and the
When the values of the capacitor 45 and the resistor 44 are set so that the time constant of R is 6 μs, no change appears in the output of the lock detection circuit 21 with an input signal of 3 μs or less, and a lock state signal is input to the controller 24. be done. In other words, by setting the CR time constant and transition voltage VB to certain values,
An error signal with a phase less than a certain period (3 μS or less in the above example) cannot be detected, so by detecting only an error signal with a phase longer than a certain period, the controller 24
can be controlled with.

[Problem that the invention seeks to solve]

The lock detection circuit of the conventional frequency synthesizer type tuning device is configured as described above, and the signal whose length corresponds to the unlocked state is integrated by the integrating circuit of the capacitor C and the resistor R. In an LSI in which a lock detection circuit is integrated with a controller, a programmable counter, a phase comparator, etc. on a single chip, the values of capacitance and resistance are large to set the time constant to 6 μs, resulting in a large LSI chip and high cost. There are things to do. In addition, due to manufacturing
There are problems in that the capacitance value and resistance value vary, and the time constant changes due to the influence of temperature, so the period of an error signal that does not need to be detected changes.

The present invention has been made in order to solve the above-mentioned problems, and provides a frequency synthesizer type tuning device in which the period during which error signal detection is not required takes discrete values and is not affected by manufacturing variations or temperature. The purpose is to obtain a lock detection circuit.

(Means for Solving the Problems) The lock detection circuit of the frequency synthesizer type tuning device according to the present invention has a lock detection circuit of the frequency synthesizer type tuning device according to the present invention. A charge transfer circuit, which is composed of a logic circuit that outputs , a ladder circuit consisting of a switch and a capacitor, and which transfers charge to each capacitor Mi11 by the above clock, and a charge accumulated in the final stage capacitor of the circuit, is compared with a predetermined value. A comparison and judgment means is set up.

[Effect]

In this invention, charge is sequentially accumulated and transferred in each capacitor of the charge transfer circuit by the number of clocks corresponding to the frequency difference or phase difference between the frequency-divided signal of the local oscillation signal and the reference frequency signal, so that the charge is accumulated in the capacitor. The charge generated can be controlled by the clock cycle and the capacitance ratio, and the period for determining the presence or absence of a phase error signal can be set discretely.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a lock detection circuit of a frequency synthesizer type tuning device according to an embodiment of the present invention.
is the N07 circuit, 57 is the NAND AND circuit, 59 is the N07 circuit, Sl is the switch that opens and closes according to the output φ of the AND circuit, and S2 is the output φ of the NOT circuit 59.
60 is the N07 circuit, 61.6
2 are capacitors each having a capacitance value of C+nC (n is a positive number).

In this figure, the output terminal D of the phase comparator 13 in FIG.
P is connected to one side of the NAND circuit 57, and the output terminal DN of the phase comparator 13 is connected to the NAND circuit via the NOT circuit 56.
Connect to the other input of D circuit 57. Further, the output terminal of the NAND circuit 57 is used as one input of the AND circuit 58, and a clock signal (CLK) is input to the local input terminal. One of the switches S1, which is turned on during the "H" period of the ANDφ signal and off during the "L" period, is connected to the positive power supply +V, and the other terminal is connected to the switch S2, which is turned on during the "H" period of the 1 signal and turned off during the "L" period. The other terminal of the switch S2 is connected to the input of the NOT circuit 60, and the output terminal A of the NOT circuit 60 is connected to the output terminal of the lock detection circuit 21. A capacitor 61 (capacitance value C) is connected between the terminal of the switch S2 and the ground, and a capacitor 62 which is n times the capacitor 61 (n is a positive number) is connected between the other terminal of the switch S2 and the ground. The logic circuit 70 that outputs the number of clocks according to the frequency difference or phase difference between the frequency-divided signal of the local oscillation signal and the reference frequency signal is configured, and the ladder circuit consisting of the above-mentioned SL, S2, 61, 62, The amount of charge accumulated in the capacitor 62 of the final stage of the charge transfer circuit 80 is transferred to a predetermined value by the switch 60, which is opened and closed by the clocks φ and φ, into the capacitors !61 and 62 provided in parallel between the power supply ■ and the ground. Comparing and determining means is configured to compare the phase difference and thereby detect the locking of the phase loft loop.

Next, the operation will be explained. The configuration of a frequency synthesizer type tuning device to which the present invention is applied is as shown in FIG. 4, as in the prior art. Now, the comparison frequency FS is the comparison reference frequency F
Consider a case where the phase is delayed by T1 compared to R. Therefore, the phase comparator 13
DP output terminal becomes “L”, DN output terminal becomes “L”,
The output B of the NAND circuit 57 has a waveform as shown in FIG. Therefore, as the φ signal, a number M of clocks having a period T2 that satisfy the following equation are output for a period T1.

M=T1/T2...(2)
Then, this φ signal and the inverted signal j of the φ signal are applied to the switch S.
1 and S2, respectively. Now, considering the case where φ is "H" and i is "L" during the first T2 period of the φ signal, the switch s1 is on and the switch S2 is off. Therefore, the capacitor 61 has a charge Q that satisfies the following equation.
1 is accumulated.

Ql-CV ・(3) Then φ
During the first T2 period of the signal, φ is “L”.

When φ is “H”, switch S1 is off, switch S
2 is turned on. Therefore, a part of the charge stored in the capacitor 61 flows into the capacitor 62, and the capacitor 61 and the capacitor 62
The charge Q1 is distributed to the capacitance in proportion to the size of the capacitance. Therefore, the potential v1 of the capacitor 62 from the ground is expressed by the following equation.

Next, considering the second period T2 of the φ signal, when the φ signal is “H” and the 1 signal is “L”, the switch S1 is on, the switch S2 is off, and the capacitor 61 has a charge of Cv. is accumulated. Next, when the φ signal is “L” and the T signal is “H”, the switch S1 is turned off and the switch S2 is turned on.
The sum of the charge (1·nC) accumulated in the second period is distributed to the capacitors 61 and 62 in an amount proportional to the capacitance of each capacitor. Therefore, the potential (2) of the capacitor 62 from the ground is expressed by the following equation.

Next, consider the third period T2 of the φ signal. When the φ signal is "H" and the φ signal is "L", a charge Cv is accumulated in the capacitor 61, and when the φ signal is "L" and the 1 signal is "H'", the charge Cv of the capacitor 61 and the charge Cv of the capacitor 62 are accumulated. The sum of charges v2·nC is distributed to each capacitor. Therefore, the potential v3 of the capacitor 62 from the ground is expressed by the following equation.

Next, the potential VM of the capacitor 62 from the ground at the Mth φ signal is expressed by the following equation.

Therefore, from equation (2), if the input transition voltage of the N07 circuit 60 is VB, when the potential VM of the capacitor 62 is lower than the input transition voltage VB, the output terminal A becomes H1, and when the potential of the capacitor 62 is high, the output terminal A becomes L”.

Therefore, the period T1 during which error signal detection is unnecessary is capacitance 61.6.
The ratio n of 2, the pulse width of Kurofuku can be set to 〒2, and the NOT circuit circuit 6 people 0. Moreover, this period T1 is determined by the capacitance ratio and is not dependent on the size of the capacitance 61.62. Therefore, by selecting a capacitance 61.62 with a small value, it is possible to adjust the chip size when converting into an LSI. can be reduced.

Note that the switch S1 and the switch S in the above embodiment
2 is a complementary insulated gate field transistor (CMO)
3), it can be replaced with a transmission gate consisting of PMO3P, NMO3N, and NOT circuit (2) as shown in FIG.

〔Effect of the invention〕

As described above, according to the frequency synthesizer type lock detection circuit according to the present invention, charge is transferred using the number of clocks whose number corresponds to the frequency difference or phase difference between the frequency-divided signal of the local oscillator signal and the reference frequency signal. Charge is accumulated and transferred sequentially through each capacitor in the circuit, and locking of the phase-locked loop is detected based on the amount of charge accumulated in the final stage capacitor, so that the charge accumulated in the capacitor is determined by the clock cycle.

It can be controlled by the capacitance ratio, and the period for determining the presence or absence of a phase error signal can be set discretely. Therefore, it is possible to obtain a product that is not affected by manufacturing variations or temperature changes. There is an effect that can be achieved.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of a frequency synthesizer type lock detection circuit according to an embodiment of the present invention, FIG. 1(a) is a circuit configuration diagram of its logic circuit, and FIG. 1(b) is its charge transfer circuit and A configuration diagram of the comparison/judgment means, Fig. 2 is a timing diagram of Fig. 1, and Fig. 3 is a 0M diagram of the switch used in the circuit of Fig. 1.
Figure 4 is a block diagram of the PLL digital tuning system, Figure 5 shows how O3 is used to replace the system.
This figure is a block diagram of the phase comparator and lock detection circuit shown in FIG. 4, and FIG. 6 is a circuit diagram of a conventional lock detection circuit. 20... Phase locked loop, 21... Lock detection circuit, 70... Logic circuit, 80... Charge transfer circuit, 6
1. 6 2...Capacity, S L. S2・=S4 Sochi, 6°O-NOT circuit (comparison and determination means).

Claims (1)

[Claims] (1) In the lock detection circuit that detects the locked state of the phase lock loop that oscillates the local oscillation signal in the frequency synthesizer type tuning device, the frequency difference or phase difference between the frequency division signal of the local oscillation signal and the reference frequency signal is detected. a logic circuit that outputs a corresponding number of clocks; a charge transfer circuit that is configured by a ladder circuit consisting of switches and capacitors, and that switches the switch a number of times equal to the number of clocks and stores and transfers charge to each of the capacitors; 1. A lock detection circuit for a frequency synthesizer type tuning device, characterized in that the lock detection circuit includes a comparison determination means for comparing the amount of charge accumulated in a final stage capacitor of a charge transfer circuit with a predetermined value.