JPH0546357Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field The present invention relates to a PLL circuit that compares the phases of a reference frequency signal and a variable frequency signal using a phase comparison circuit to lock the oscillation frequency of a VCO.

(b) Prior art In general, a PLL circuit, as shown in Figure 2,
Reference frequency signal f _R obtained by dividing the oscillation output from crystal oscillation circuit 1 by reference divider 2
and a variable frequency signal f _P obtained by dividing the oscillation output from VCO 3 by programmable divider 4.
The phase comparison circuit 5 compares the DC voltage V _T corresponding to the phase difference output with the charge pump circuit 6 and
obtained by LPF7, and its DC voltage V _T is VCO3
By controlling the oscillation frequency f _OSC of VCO3
It is used to clock the Further, the output of the phase comparison circuit 5 is applied to the unlock detection circuit 8,
In the unlock detection circuit 8, when the phase difference is equal to or greater than a predetermined pulse width, it is detected that the unlock state has been reached, and an unlock signal is output.

The unlock detection circuit may be constructed of a capacitor and a resistor, or a digital circuit, and these are described in Japanese Patent Publication No. 11138/1983.

(c) Problems to be solved by the invention The signal generated by the PLL circuit shown in Figure 2 is used as a carrier wave in a transmitter and is often FM modulated. In this case, as the modulation frequency decreases, the phase difference of the phase comparator circuit increases. As a result, the unlock detection circuit 8 may output an unlock detection signal even though it is in the locked state. Also,
If the loop gain of the PLL circuit is large, it will work to restore the modulated signal to its original state, resulting in insufficient modulation. On the other hand, if the loop gain is small, there will be an inconvenience that the lockup time will be long when switching channels.

(d) Means for Solving the Problems The present invention was created in view of the above points, and includes a switching gate that selectively outputs one of a plurality of clock pulses of different frequencies, and a switching gate that selectively outputs one of a plurality of clock pulses of different frequencies. By providing an unlock detection circuit comprising a pulse width discrimination circuit to which a clock pulse outputted from the clock pulse is applied and which discriminates the output pulse width of the phase comparator circuit based on the pulse width of the clock pulse, a lock state and a lock up state can be determined. By making it possible to change the pulse width for discriminating the output pulse width of the phase comparator circuit, and by providing a sub-charge pump circuit that is simultaneously controlled by a signal that controls the unlock detection circuit, the lock state and lock-up can be changed. This can be solved by changing the loop gain depending on the state.

(E) Effect According to the above means, when the PLL circuit is in the lock state, the clock signal having a pulse width longer than the output pulse width of the phase comparator circuit output by modulation is subjected to pulse width discrimination by the control signal. Since the voltage is applied to the circuit, the phase difference caused by modulation is not detected as an unlocked state, and the auxiliary charge pump circuit is also not activated, so the loop gain of the PLL circuit becomes small and sufficient modulation can be obtained. . On the other hand, when switching channels, a clock pulse with a short pulse width is applied to the pulse width discriminator circuit, so the unlocked state can be accurately detected, and the sub charge pump circuit is operated simultaneously to adjust the loop gain of the PLL circuit. By increasing the size, the lockup time can be shortened.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention, in which 9 is a phase comparator circuit, 10 is a charge pump circuit, 11 is an LPF, 12 is an unlock detection circuit,
13 is a sub-charge pump circuit.

As in FIG. 2, the phase comparator circuit 9 inputs the reference divider output Fr and the programmable divider output Fp, and outputs a low active signal PH _A and a high active signal PH _B according to the phase difference. Output. Charge pump circuit 10
is composed of C-MOS, the output PH _A of the phase comparator circuit 9 is applied to the gate of P-MOS, and the N-
The output PH _B is applied to the gate of the MOS. LPF
11 is composed of an inverting amplifier circuit 12, a resistor R1 and a capacitor C connected to its input/output, and a resistor R2 connected to its input, and the output of the charge pump circuit 10 is applied to the resistor R2. The sub charge pump circuit 13 is the charge pump circuit 10
The output is connected to the LPF 11 via a resistor R3 which is smaller than the resistor R2. A control signal is input to the input of the sub-charge pump circuit 13.
A gate circuit 14 to which CONT is applied is provided. That is, when the PLL circuit is in the lock state, the control signal CONT is "0", and the sub charge pump circuit 13 receives the output of the phase comparison circuit 9.
PH _A and PH _B are not output, and only the charge pump circuit 10 operates. On the other hand, when the PLL circuit is in the unlocked state, by setting the control signal CONT to "1", the output of the phase comparator circuit 9 is
Since PH _A and PH _B are output and the sub charge pump circuit 13 is operated, the loop gain is increased and the lockup time is shortened.

The unlock detection circuit 12 receives the inverted signals *PH _A and PH _B of the output PH _A of the phase comparison circuit 9.
The OR gate 15 constitutes a pulse width discrimination circuit, and the output of the OR gate 15 is applied to the D input of the D-FF16, and the clock pulses CL1 and CL2 are applied to the clock input CL of the D-FF16 as the control signal CONT. Gate circuit 1 that outputs based on
7, an unlock signal UNLOCK is output in synchronization with the rise of output Q of D-FF16, and D-FF
The timer circuit 18 eliminates the unlock signal UNLOCK after a predetermined period of time has elapsed since the fall of the output Q of 16. clock pulse CL
1 and CL2 are frequency-divided outputs taken from the middle of the reference divider 2 _shown in _FIG . The falling edge is clock pulse CL1 and clock pulse
It will be synchronized with the falling edge of CL2. Also,
Clock pulse CL2 has a lower frequency than clock pulse CL1, and the pulse width of CL2 is greater than the phase difference output when the signal generated by the PLL circuit is FM modulated. D-
FF16 is D at the falling edge of clock input CL.
Since the theoretical value of the input is held and output until the next falling edge of the clock input CL, when the clock pulse CL1 is selectively outputted by the gate circuit 17, the phase difference signals PH _A and PH whose period is less than the period of the clock pulse CL1 are output. _B is not detected, and when the clock pulse CL2 is selectively outputted by the gate circuit 17, the phase difference signals PH _A and PH _B having a period less than the period of the clock pulse CL2 are not detected.

Next, the operation of the PLL circuit shown in FIG. 1 will be explained.

First, when the PLL circuit is in the lock state, the control signal CONT is "0" and the clock pulse
CL2 is selected by the gate circuit 17, and the operation of the sub charge pump circuit 13 is prohibited. Therefore,
Since the phase difference signals PH _A and PH _B drive only the charge pump circuit 10, the gain of the PLL circuit becomes small and the degree of modulation of the VCO can be increased. Furthermore, since a phase difference signal shorter than the period of the clock pulse CL2 is not detected by the D _{- FF16} , the unlock detection output is
Does not occur.

On the other hand, when switching channels, the control signal CONT is set to "1", the sub charge pump circuit 13 is put into operation, and the gate circuit 17 selects the clock pulse CL1. Then the phase difference signal
PH _A and PH _B drive the charge pump circuit 10 and the sub charge pump circuit 13, so PLL
The loop gain of the circuit is increased and the lockup time is reduced. Further, since the pulse widths of the phase difference signals PH _A and PH _B are discriminated by the clock pulse CL1 having a short pulse width, the output of the D-FF 16 becomes "0" when a complete lock state is approached. When the output of the D-FF 16 becomes "0", the timer circuit 18 operates, and after a predetermined time, the unlock signal UNLOCK becomes "0" and the PLL is activated.
It can be seen that the circuit is now in a locked state. Normally, the unlock signal UNLOCK is applied to something that controls a PLL circuit, such as a microcomputer, and the control signal CONT is output from the microcomputer or the like.

(G) Effects of the invention As described above, according to the invention, when switching channels, the loop gain of the PLL circuit is increased, the lock-up time is shortened, and the pulse width detected by the unlock detection circuit is narrowed. Unlock can be reliably detected when switching channels, and in the locked state, the loop gain can be reduced to increase the degree of VCO modulation, and erroneous unlock detection can be achieved due to the phase difference caused by modulation. This has the advantage that a highly reliable PLL circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention;
FIG. 2 is a block diagram showing a conventional example. 9... Phase comparison circuit, 10... Charge pump circuit, 11... LPF, 12... Unlock detection circuit, 13... Sub charge pump circuit.

Claims (1)

[Claims for Utility Model Registration] 1. A reference divider that divides the frequency of a reference oscillation signal, a voltage controlled oscillation circuit (VCO), a programmable divider that divides the oscillation output of the VCO, and the reference divider. a phase comparison circuit for comparing the phase difference between the output of the programmable divider and the output of each of the programmable dividers; a charge pump circuit connected to the output of the phase comparison circuit; and a charge pump circuit for smoothing the output of the charge pump circuit and for smoothing the output of the charge pump circuit.
A PLL circuit consisting of a low-pass filter (LPF) that generates a control voltage for the VCO, and an unlock detection circuit that detects that the output of the phase comparison circuit exceeds a predetermined pulse width and outputs an unlock signal. A sub-charge pump circuit connected to the output of the phase comparison circuit and whose operation is controlled by a control signal is provided, and the unlock detection circuit is controlled by the control signal and has a plurality of charge pumps at different frequencies. a switching gate that selectively outputs one of the clock pulses; and a pulse width discrimination circuit that receives the clock pulse output from the switching gate and discriminates the output pulse width of the phase comparison circuit based on the pulse width of the clock pulse. A PLL circuit characterized in that a clock pulse with a short pulse width is output from a switching gate when the sub-charge pump circuit is in operation. 2. The PLL circuit according to claim 1, wherein the pulse width discrimination circuit is constituted by a D flip-flop in which the output of the switching gate is applied to a clock input, and the output of the phase comparison circuit is applied to a D input. characterized by
PLL circuit.