JPS5763936A - Phase-locked loop - Google Patents

Phase-locked loop

Info

Publication number
JPS5763936A
JPS5763936A JP55139368A JP13936880A JPS5763936A JP S5763936 A JPS5763936 A JP S5763936A JP 55139368 A JP55139368 A JP 55139368A JP 13936880 A JP13936880 A JP 13936880A JP S5763936 A JPS5763936 A JP S5763936A
Authority
JP
Japan
Prior art keywords
frequency
output
voltage
pll
vco10
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55139368A
Other languages
Japanese (ja)
Inventor
Seiji Koyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GEN RES ELECTRONICS Inc
GENERAL RES OBU EREKUTORONITSUKUSU KK
ZENERARU RESEARCH OBU EREKUTORONITSUKUSU KK
Original Assignee
GEN RES ELECTRONICS Inc
GENERAL RES OBU EREKUTORONITSUKUSU KK
ZENERARU RESEARCH OBU EREKUTORONITSUKUSU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GEN RES ELECTRONICS Inc, GENERAL RES OBU EREKUTORONITSUKUSU KK, ZENERARU RESEARCH OBU EREKUTORONITSUKUSU KK filed Critical GEN RES ELECTRONICS Inc
Priority to JP55139368A priority Critical patent/JPS5763936A/en
Publication of JPS5763936A publication Critical patent/JPS5763936A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/187—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop
    • H03L7/189—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using means for coarse tuning the voltage controlled oscillator of the loop comprising a D/A converter for generating a coarse tuning voltage
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals

Abstract

PURPOSE:To obtain a wide PLL frequency range with detuning reduced, by controlling a voltage-controlled oscillator VCO by a voltage regarding an output frequency setting digital data supplied to a programmable frequency divider. CONSTITUTION:A digital frequency-division indication signal P supplied to a programmable frequency divider 12 is supplied to a D/A converter 22 as well. The output Vo of the converter 22 has a voltage value corresponding to the specified frequency-division ratio N of the frequency divider 12, and a VCO10 is controlled by the voltage. The VCO10 has an oscillation frequency specified by the Vo, and the frequency is divided by N at the frequency divider 12, whose output is compared, in terms of phase, with a reference signal from a reference frequency generator 14 by a phase comparator 16 to supply their difference to the VCO10 as a voltage Vp through an LPF18. The principal decision on a PLL output frequency by the signal P is made by the output Vo of the converter 22 and only the correction for accurate PLL output setting is performed by the output Vp of the LPF18, so the modulation sensitivity of VCO is set small, thereby reducing noises in the PLL output signal following up large modulation sensitivity.
JP55139368A 1980-10-07 1980-10-07 Phase-locked loop Pending JPS5763936A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55139368A JPS5763936A (en) 1980-10-07 1980-10-07 Phase-locked loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55139368A JPS5763936A (en) 1980-10-07 1980-10-07 Phase-locked loop

Publications (1)

Publication Number Publication Date
JPS5763936A true JPS5763936A (en) 1982-04-17

Family

ID=15243692

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55139368A Pending JPS5763936A (en) 1980-10-07 1980-10-07 Phase-locked loop

Country Status (1)

Country Link
JP (1) JPS5763936A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4568888A (en) * 1983-11-08 1986-02-04 Trw Inc. PLL Fast frequency synthesizer with memories for coarse tuning and loop gain correction
US5281927A (en) * 1993-05-20 1994-01-25 Codex Corp. Circuit and method of controlling a VCO with capacitive loads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4568888A (en) * 1983-11-08 1986-02-04 Trw Inc. PLL Fast frequency synthesizer with memories for coarse tuning and loop gain correction
US5281927A (en) * 1993-05-20 1994-01-25 Codex Corp. Circuit and method of controlling a VCO with capacitive loads

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