JPS6416741U - - Google Patents

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Publication number
JPS6416741U
JPS6416741U JP11135687U JP11135687U JPS6416741U JP S6416741 U JPS6416741 U JP S6416741U JP 11135687 U JP11135687 U JP 11135687U JP 11135687 U JP11135687 U JP 11135687U JP S6416741 U JPS6416741 U JP S6416741U
Authority
JP
Japan
Prior art keywords
vco
output
gain
variable
phase comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11135687U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11135687U priority Critical patent/JPS6416741U/ja
Publication of JPS6416741U publication Critical patent/JPS6416741U/ja
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の直接変調方式周波数シンセサイ
ザの一構成例、第2図はVCOの発振周波数によ
る変調感度特性、第3図は本考案により変調感度
偏差を相殺する直接変調方式周波数シンセサイザ
の構成例、第4図は、第3図に示した構成で変調
感度偏差が相殺される動作を示す特性図である。 1:基準信号発生器、3:位相比較器、5:電
圧制御発振器、7:オーデイオ回路、8:利得可
変回路。
Figure 1 shows a configuration example of a conventional direct modulation frequency synthesizer, Figure 2 shows modulation sensitivity characteristics depending on the oscillation frequency of the VCO, and Figure 3 shows a configuration example of a direct modulation frequency synthesizer that cancels modulation sensitivity deviations according to the present invention. , FIG. 4 is a characteristic diagram showing the operation in which the modulation sensitivity deviation is canceled out in the configuration shown in FIG. 3. 1: Reference signal generator, 3: Phase comparator, 5: Voltage controlled oscillator, 7: Audio circuit, 8: Variable gain circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基準信号発生器、位相比較器、ループフイルタ
、電圧制御発振器(以下VCO)およびVCOの
出力信号を分周する可変分周器を備え、前記基準
信号発生器の出力と可変分周器の出力を前記位相
比較器で比較し、その比較出力を前記ループフイ
ルタを介して前記VCOに加えるように構成され
、さらに前記VCOの変調端子に、前記位相比較
器から出力される信号により利得が可変できる利
得可変回路の出力を接続し、該利得可変回路の入
力に変調信号を入力してVCOの出力信号に周波
数変調波を得る直接変調方式周波数シンセサイザ
において、前記VCOの発振周波数に対応するV
COの変調感度と前記利得可変回路の利得の積が
一定となるよう、前記位相比較器から出力される
信号により、前記利得可変回路の利得を可変する
ようにしたことを特徴とする直接変調方式周波数
シンセサイザ。
It is equipped with a reference signal generator, a phase comparator, a loop filter, a voltage controlled oscillator (hereinafter referred to as VCO), and a variable frequency divider that divides the output signal of the VCO, and the output of the reference signal generator and the output of the variable frequency divider are A gain whose gain is configured to be compared by the phase comparator and to apply the comparison output to the VCO via the loop filter, and whose gain can be varied by the signal output from the phase comparator is connected to the modulation terminal of the VCO. In a direct modulation frequency synthesizer in which the output of a variable circuit is connected and a modulation signal is input to the input of the variable gain circuit to obtain a frequency modulated wave as the output signal of the VCO, a VCO corresponding to the oscillation frequency of the VCO is used.
A direct modulation method characterized in that the gain of the variable gain circuit is varied by a signal output from the phase comparator so that the product of the modulation sensitivity of the CO and the gain of the variable gain circuit is constant. frequency synthesizer.
JP11135687U 1987-07-22 1987-07-22 Pending JPS6416741U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11135687U JPS6416741U (en) 1987-07-22 1987-07-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11135687U JPS6416741U (en) 1987-07-22 1987-07-22

Publications (1)

Publication Number Publication Date
JPS6416741U true JPS6416741U (en) 1989-01-27

Family

ID=31349326

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11135687U Pending JPS6416741U (en) 1987-07-22 1987-07-22

Country Status (1)

Country Link
JP (1) JPS6416741U (en)

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