JPH0425330U - - Google Patents
Info
- Publication number
- JPH0425330U JPH0425330U JP6577790U JP6577790U JPH0425330U JP H0425330 U JPH0425330 U JP H0425330U JP 6577790 U JP6577790 U JP 6577790U JP 6577790 U JP6577790 U JP 6577790U JP H0425330 U JPH0425330 U JP H0425330U
- Authority
- JP
- Japan
- Prior art keywords
- guided
- signal
- phase
- output
- gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案のＰＬＬ回路の電気的構成を示
すブロツク図、第２図は従来のＰＬＬ回路の電気
的構成を示すブロツク図である。
１……位相比較器、２……ローパスフイルタ（
ループフイルタ）、３……可変利得増幅器、４…
…電圧制御発振器（ＶＣＯ）、５……分周器、６
……ロツク検出回路。
FIG. 1 is a block diagram showing the electrical configuration of a PLL circuit according to the present invention, and FIG. 2 is a block diagram showing the electrical configuration of a conventional PLL circuit. 1... Phase comparator, 2... Low pass filter (
loop filter), 3...variable gain amplifier, 4...
...Voltage controlled oscillator (VCO), 5... Frequency divider, 6
...Lock detection circuit.
Claims (1)
較器と、この位相比較器の出力が導かれたループ
フイルタと、このループフイルタの出力が制御端
子に導かれると共にその出力が分周器を介して前
記位相比較器の他方の入力に導かれた電圧制御発
振器とからなるＰＬＬ回路において、 前記ループフイルタと前記電圧制御発振器との
間に介挿された可変利得増幅器と、 前記基準信号と前記分周器から出力される比較
信号とに基づいて位相のロツク状態を検出すると
共に、その検出信号を前記可変利得増幅器の利得
制御端子に送出するロツク検出回路とを備え、 前記可変利得増幅器は、前記ロツク検出回路か
らの検出信号が位相のアンロツク状態を示す信号
であるときには、利得を小さくする制御を行い、
前記ロツク検出回路からの検出信号が位相のロツ
ク状態を示す信号であるときには、利得を大きく
する制御を行うことを特徴とするＰＬＬ回路。[Claims for Utility Model Registration] A phase comparator to which a reference signal is guided to one input, a loop filter to which the output of this phase comparator is guided, and an output of this loop filter to be guided to a control terminal. and a voltage controlled oscillator whose output is guided to the other input of the phase comparator via a frequency divider, the variable gain interposed between the loop filter and the voltage controlled oscillator. an amplifier; and a lock detection circuit that detects a phase lock state based on the reference signal and the comparison signal output from the frequency divider, and sends the detection signal to a gain control terminal of the variable gain amplifier. The variable gain amplifier controls the gain to be small when the detection signal from the lock detection circuit is a signal indicating a phase unlocked state;
A PLL circuit characterized in that when the detection signal from the lock detection circuit is a signal indicating a phase lock state, control is performed to increase the gain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6577790U JPH0425330U (en) | 1990-06-21 | 1990-06-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6577790U JPH0425330U (en) | 1990-06-21 | 1990-06-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0425330U true JPH0425330U (en) | 1992-02-28 |
Family
ID=31597911
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6577790U Pending JPH0425330U (en) | 1990-06-21 | 1990-06-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0425330U (en) |
-
1990
- 1990-06-21 JP JP6577790U patent/JPH0425330U/ja active Pending