JPS6168525U - - Google Patents

Info

Publication number
JPS6168525U
JPS6168525U JP15325584U JP15325584U JPS6168525U JP S6168525 U JPS6168525 U JP S6168525U JP 15325584 U JP15325584 U JP 15325584U JP 15325584 U JP15325584 U JP 15325584U JP S6168525 U JPS6168525 U JP S6168525U
Authority
JP
Japan
Prior art keywords
frequency
signal
variable
vco
control voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15325584U
Other languages
Japanese (ja)
Other versions
JPH0349473Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984153255U priority Critical patent/JPH0349473Y2/ja
Publication of JPS6168525U publication Critical patent/JPS6168525U/ja
Application granted granted Critical
Publication of JPH0349473Y2 publication Critical patent/JPH0349473Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Superheterodyne Receivers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はPLL周波数シンセサイザチユーナの
従来例を示すブロツク図、第2図は第1図のチユ
ーナにおける制御電圧対同調周波数及び局部発振
周波数の変化特性を示す図、第3図は本考案の実
施例を示すブロツク図、第4図は第3図のチユー
ナにおける制御電圧対同調周波数及び局部発振周
波数の変化特性を示す図である。 主要部分の符号の説明、1…RF同調回路、2
…VCO、8…可変利得直流増幅器。
Fig. 1 is a block diagram showing a conventional example of a PLL frequency synthesizer tuner, Fig. 2 is a diagram showing the change characteristics of control voltage versus tuning frequency and local oscillation frequency in the tuner of Fig. 1, and Fig. 3 is a diagram showing the change characteristics of the tuner of the present invention. FIG. 4, a block diagram showing the embodiment, is a diagram showing the change characteristics of control voltage versus tuning frequency and local oscillation frequency in the tuner of FIG. 3. Explanation of symbols of main parts, 1...RF tuning circuit, 2
...VCO, 8...Variable gain DC amplifier.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 制御電圧に応じて発振周波数が変化するVCO
(電圧制御発振器)と、該VCOの発振信号を任
意の分周比で分周する可変分周手段と、該可変分
周手段の出力信号と基準信号との位相差に応じて
前記制御電圧を発生する位相検出手段と、前記可
変分周手段の分周比に応じた利得で前記制御電圧
を増幅する可変利得直流増幅手段と、該可変利得
直流増幅手段の出力電圧に応じた同調周波数を得
るRF(高周波)同調回路と、該RF同調回路か
ら出力されるRF信号を前記VCOの発振信号と
混合してIF(中間周波)信号に変換するミキサ
とを含むことを特徴とするPLL周波数シンセサ
イザチユーナ。
VCO whose oscillation frequency changes depending on the control voltage
(voltage controlled oscillator), variable frequency dividing means for dividing the oscillation signal of the VCO at an arbitrary frequency division ratio, and controlling the control voltage according to the phase difference between the output signal of the variable frequency dividing means and the reference signal. generating phase detection means, variable gain DC amplification means for amplifying the control voltage with a gain according to the frequency division ratio of the variable frequency division means, and obtaining a tuning frequency according to the output voltage of the variable gain DC amplification means. A PLL frequency synthesizer comprising an RF (high frequency) tuning circuit and a mixer that mixes the RF signal output from the RF tuning circuit with the oscillation signal of the VCO and converts it into an IF (intermediate frequency) signal. Yuna.
JP1984153255U 1984-10-11 1984-10-11 Expired JPH0349473Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984153255U JPH0349473Y2 (en) 1984-10-11 1984-10-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984153255U JPH0349473Y2 (en) 1984-10-11 1984-10-11

Publications (2)

Publication Number Publication Date
JPS6168525U true JPS6168525U (en) 1986-05-10
JPH0349473Y2 JPH0349473Y2 (en) 1991-10-22

Family

ID=30711289

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984153255U Expired JPH0349473Y2 (en) 1984-10-11 1984-10-11

Country Status (1)

Country Link
JP (1) JPH0349473Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0248832A (en) * 1987-05-23 1990-02-19 Nec Corp Antenna tuning circuit and individual selective call receiver using the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4958219U (en) * 1972-08-29 1974-05-22
JPS57158234U (en) * 1981-03-31 1982-10-05

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4958219U (en) * 1972-08-29 1974-05-22
JPS57158234U (en) * 1981-03-31 1982-10-05

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0248832A (en) * 1987-05-23 1990-02-19 Nec Corp Antenna tuning circuit and individual selective call receiver using the same

Also Published As

Publication number Publication date
JPH0349473Y2 (en) 1991-10-22

Similar Documents

Publication Publication Date Title
JP3974679B2 (en) Receiver with piezoelectric crystal oscillation circuit
US4355413A (en) Phase locked loop circuit
JPS6168525U (en)
JPH0156580B2 (en)
JPS6448941U (en)
JPH0339962Y2 (en)
JPS61156310U (en)
JPH0469930U (en)
JPS6219010Y2 (en)
JPS6188333U (en)
JPH0188531U (en)
JPH0423962B2 (en)
JPS6423132U (en)
JPH0425330U (en)
JPS6217234U (en)
JPH0236215U (en)
JPS6093339U (en) Chuyuna
JPS6438022U (en)
JPH0362605A (en) Frequency modulation circuit
JPH01142228U (en)
JPH0344932U (en)
JPS6230426U (en)
JPS62158943U (en)
JPS6416741U (en)
JPH01115342U (en)