JPH0344932U - - Google Patents

Info

Publication number
JPH0344932U
JPH0344932U JP10351689U JP10351689U JPH0344932U JP H0344932 U JPH0344932 U JP H0344932U JP 10351689 U JP10351689 U JP 10351689U JP 10351689 U JP10351689 U JP 10351689U JP H0344932 U JPH0344932 U JP H0344932U
Authority
JP
Japan
Prior art keywords
output
amplifier
frequency
pll circuit
controlled oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10351689U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10351689U priority Critical patent/JPH0344932U/ja
Publication of JPH0344932U publication Critical patent/JPH0344932U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示すブロツク図、
第2図は従来のPLL回路の一例を示すブロツク
図である。 1……基準クロツク信号入力端子、2……位相
比較器、3……低域波器、4,9……直流増幅
器、5……電圧制御発振器、6……PLL回路の
出力端子、7……N分周回路、8……周波数検出
回路、10……セレクタ。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing an example of a conventional PLL circuit. DESCRIPTION OF SYMBOLS 1...Reference clock signal input terminal, 2...Phase comparator, 3...Low frequency converter, 4, 9...DC amplifier, 5...Voltage controlled oscillator, 6...Output terminal of PLL circuit, 7... ...N frequency divider circuit, 8...frequency detection circuit, 10...selector.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 基準クロツク信号にロツクしたクロツク信号を
発生するPLL回路であつて、電圧制御発振器と
、該電圧制御発振器の出力をN(N:任意の整数
)分周するN分周回路と、該分周回路の出力信号
の位相と前記基準クロツク信号の位相とを比較し
、その位相差に応じた電圧を発生する位相比較器
と、該位相比較器の出力に接続された低域波器
と、該低域波器の出力を増幅する直流増幅器と
を有し、この直流増幅器の出力により前記電圧制
御発振器の出力周波数を制御して、該電圧制御発
振器の出力をPLL回路の出力信号として取り出
すPLL回路において、前記位相比較器の出力信
号を検出する周波数検出回路と、前記直流増幅器
に対し並列的に接続されて該第1の直流増幅器よ
り小さい利得を有する第2の直流増幅器と、前記
周波数検出回路の出力に基いて前記位相比較器の
出力信号の周波数が当該PLL回路のロツク状態
の周波数の半分になつたとき利得の大きい前記第
1の直流増幅器をそれぞれ利得の小さい前記第2
の直流増幅器に切り替える手段を具備したことを
特徴とするPLL回路。
A PLL circuit that generates a clock signal locked to a reference clock signal, which includes a voltage controlled oscillator, an N frequency divider circuit that frequency divides the output of the voltage controlled oscillator by N (N: any integer), and the frequency divider circuit. a phase comparator that compares the phase of the output signal of the reference clock signal with the phase of the reference clock signal, and generates a voltage according to the phase difference; a low frequency generator connected to the output of the phase comparator; A PLL circuit comprising: a DC amplifier that amplifies the output of the bandpass filter; the output frequency of the voltage controlled oscillator is controlled by the output of the DC amplifier, and the output of the voltage controlled oscillator is taken out as an output signal of the PLL circuit; , a frequency detection circuit for detecting the output signal of the phase comparator; a second DC amplifier connected in parallel to the DC amplifier and having a smaller gain than the first DC amplifier; Based on the output, when the frequency of the output signal of the phase comparator becomes half the frequency of the lock state of the PLL circuit, the first DC amplifier with a large gain is replaced with the second DC amplifier with a small gain.
A PLL circuit characterized by comprising means for switching to a DC amplifier.
JP10351689U 1989-09-05 1989-09-05 Pending JPH0344932U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10351689U JPH0344932U (en) 1989-09-05 1989-09-05

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10351689U JPH0344932U (en) 1989-09-05 1989-09-05

Publications (1)

Publication Number Publication Date
JPH0344932U true JPH0344932U (en) 1991-04-25

Family

ID=31652348

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10351689U Pending JPH0344932U (en) 1989-09-05 1989-09-05

Country Status (1)

Country Link
JP (1) JPH0344932U (en)

Similar Documents

Publication Publication Date Title
JPH0344932U (en)
JPS6329304Y2 (en)
JPH02112030U (en)
JPH0328606Y2 (en)
JPH0425330U (en)
JPS63288518A (en) Pll circuit
JPH0422575Y2 (en)
JPS6352316U (en)
JPH0339962Y2 (en)
JPH089937Y2 (en) Digital phase synchronization circuit
JPS5838665Y2 (en) Receiving machine
JPS62119029U (en)
JPS62186533U (en)
JPS6298806A (en) Fm modulator
JPH0467823U (en)
JPH02134781U (en)
JPH0339918U (en)
JPS5946043U (en) radio receiver
JPS63111075U (en)
JPS6188333U (en)
JPS5830356U (en) radio receiver
JPH03117946U (en)
JPH0386635U (en)
JPS6168525U (en)
JPH0472725U (en)