JPS6093339U - Chuyuna - Google Patents

Chuyuna

Info

Publication number
JPS6093339U
JPS6093339U JP18359283U JP18359283U JPS6093339U JP S6093339 U JPS6093339 U JP S6093339U JP 18359283 U JP18359283 U JP 18359283U JP 18359283 U JP18359283 U JP 18359283U JP S6093339 U JPS6093339 U JP S6093339U
Authority
JP
Japan
Prior art keywords
circuit
frequency
voltage
phase
controlled oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18359283U
Other languages
Japanese (ja)
Inventor
山中 栄一郎
Original Assignee
日本電気ホームエレクトロニクス株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気ホームエレクトロニクス株式会社 filed Critical 日本電気ホームエレクトロニクス株式会社
Priority to JP18359283U priority Critical patent/JPS6093339U/en
Publication of JPS6093339U publication Critical patent/JPS6093339U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、従来のFMチューナの構成図、第2図は、本
考案の一実施例の構成図、第3図aおよびbは、受信信
号の選択度特性曲線を示し、それg ぞれ、受信周波数を偏移させる前および偏移させた後を
示す。 1・・・・・・電圧制御発振器(VCO)、2・・・・
・・プログラム・デイバイダ、3・・・・・・CPU、
 4・・・・・・操作部、5・・・・・・位相検出器、
6・・・・・・基準発振器、7・・・・・・ループフィ
ルタ(LPF)、10・・・・・・位相固定閉ループ(
PLL)回路、11・・・・・・周波数保持回路、12
・・・・・・周波数偏移回路、20・・・・・・アンテ
ナ、21・・・・・・高周波増幅回路(RFアンプ)、
22・・間層波数混合回路(ミキサ)、23・・・・・
・中間周波数増幅回路(IF’アンプ)、a、b・・・
・・・スイッチ、fo・・・・・・発振周波数、f、・
・・・・・基準周波数、SL・・・・・・位相固定信号
、vc・・・・・・直流制御電圧。
Fig. 1 is a block diagram of a conventional FM tuner, Fig. 2 is a block diagram of an embodiment of the present invention, and Figs. 3 a and b show selectivity characteristic curves of received signals. , before and after shifting the receiving frequency. 1... Voltage controlled oscillator (VCO), 2...
...Program divider, 3...CPU,
4... Operation unit, 5... Phase detector,
6... Reference oscillator, 7... Loop filter (LPF), 10... Phase locked closed loop (
PLL) circuit, 11... Frequency holding circuit, 12
... Frequency shift circuit, 20 ... Antenna, 21 ... High frequency amplification circuit (RF amplifier),
22... Interlayer wave number mixing circuit (mixer), 23...
・Intermediate frequency amplifier circuit (IF' amplifier), a, b...
...Switch, fo...Oscillation frequency, f,...
...Reference frequency, SL...Phase fixed signal, vc...DC control voltage.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電圧制御発振器を有する位相固定閉ループ回路を局部発
振回路に用いたチューナにおいて、前記電圧制御発振器
の次段に接続され、前記位相固定閉ループ回路の位相固
定信号によりその時の発振周波数を保持する周波数保持
回路と、前記電圧制御発振器に直流制御電圧を与えて前
記発振周波数を偏移させる周波数偏移回路とを具備して
いることを特徴とするチューナ。
In a tuner using a phase-locked closed loop circuit having a voltage-controlled oscillator as a local oscillation circuit, a frequency holding circuit is connected to the next stage of the voltage-controlled oscillator and holds the oscillation frequency at that time by a phase-locked signal of the phase-locked closed-loop circuit. and a frequency shift circuit that applies a DC control voltage to the voltage controlled oscillator to shift the oscillation frequency.
JP18359283U 1983-11-30 1983-11-30 Chuyuna Pending JPS6093339U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18359283U JPS6093339U (en) 1983-11-30 1983-11-30 Chuyuna

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18359283U JPS6093339U (en) 1983-11-30 1983-11-30 Chuyuna

Publications (1)

Publication Number Publication Date
JPS6093339U true JPS6093339U (en) 1985-06-26

Family

ID=30397297

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18359283U Pending JPS6093339U (en) 1983-11-30 1983-11-30 Chuyuna

Country Status (1)

Country Link
JP (1) JPS6093339U (en)

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