JPS6385930U - - Google Patents
Info
- Publication number
- JPS6385930U JPS6385930U JP18123686U JP18123686U JPS6385930U JP S6385930 U JPS6385930 U JP S6385930U JP 18123686 U JP18123686 U JP 18123686U JP 18123686 U JP18123686 U JP 18123686U JP S6385930 U JPS6385930 U JP S6385930U
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- band
- mixer
- frequency synthesizer
- heterodyne
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims 4
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Superheterodyne Receivers (AREA)
- Noise Elimination (AREA)
Description
第１図は本考案のヘテロダイン受信機の原理ブ
ロツク図、第２図は一実施例のヘテロダイン受信
機のブロツク図、第３図は一実施例の帯域除去フ
イルタの共振回路図、第４図は帯域除去フイルタ
の特性図、第５図は従来のヘテロダイン受信機の
ブロツク図である。
図において、１は位相比較器（ＰＤ）、２は基
準発振器、３は固定分周器、４は電圧制御発振器
（ＶＣＯ）、５は可変分周器、６はローパスフイ
ルタ（ＬＰＦ）、７はアンテナ、８はＲＦアンプ
、９はミキサー（ＭＩＸ）、１０はバンドパスフ
イルタ、１１は帯域除去フイルタ（ＢＥＦ）、１
２は周波数シンセサイザ、１３は局発入力端を示
している。
Fig. 1 is a principle block diagram of the heterodyne receiver of the present invention, Fig. 2 is a block diagram of a heterodyne receiver of an embodiment, Fig. 3 is a resonant circuit diagram of a band rejection filter of an embodiment, and Fig. 4 is a block diagram of the principle of the heterodyne receiver of the present invention. FIG. 5, which is a characteristic diagram of a band rejection filter, is a block diagram of a conventional heterodyne receiver. In the figure, 1 is a phase comparator (PD), 2 is a reference oscillator, 3 is a fixed frequency divider, 4 is a voltage controlled oscillator (VCO), 5 is a variable frequency divider, 6 is a low-pass filter (LPF), and 7 is a Antenna, 8 RF amplifier, 9 mixer (MIX), 10 band pass filter, 11 band rejection filter (BEF), 1
2 represents a frequency synthesizer, and 13 represents a local oscillator input terminal.
Claims (1)
れる局発信号とをミキサー９にてヘテロダイン検
波して中間周波信号を作成するヘテロダイン受信
機において、 前記ミキサー９の局発入力端１３の近傍に帯域
除去フイルタ１１を設け、該帯域除去フイルタ１
１を介して前記周波数シンセサイザ１２とミキサ
ー９間を接続するとともに、前記帯域除去フイル
タ１１の共振周波数を前記周波数シンセサイザ１
２の源発信周波数あるいは、その整数倍、または
整数分の１でなお且つ前記局発周波数の帯域外の
近傍に設定したことを特徴とするヘテロダイン受
信機。[Claims for Utility Model Registration] In a heterodyne receiver that generates an intermediate frequency signal by heterodyne-detecting a received signal and a local oscillation signal output from a frequency synthesizer 12 in a mixer 9, the local oscillator input terminal of the mixer 9 A band removal filter 11 is provided near the band removal filter 13.
The frequency synthesizer 12 and the mixer 9 are connected via the frequency synthesizer 1, and the resonant frequency of the band rejection filter 11 is connected to the frequency synthesizer 1
1. A heterodyne receiver characterized in that the source oscillation frequency is set at a source oscillation frequency of 2, an integral multiple thereof, or an integer fraction thereof, and in the vicinity outside the band of the local oscillation frequency.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18123686U JPS6385930U (en) | 1986-11-25 | 1986-11-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18123686U JPS6385930U (en) | 1986-11-25 | 1986-11-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6385930U true JPS6385930U (en) | 1988-06-04 |
Family
ID=31125920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18123686U Pending JPS6385930U (en) | 1986-11-25 | 1986-11-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6385930U (en) |
-
1986
- 1986-11-25 JP JP18123686U patent/JPS6385930U/ja active Pending
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