JPH09130146A - Low frequency data modulation circuit for fm radio unit - Google Patents

Low frequency data modulation circuit for fm radio unit

Info

Publication number
JPH09130146A
JPH09130146A JP7283822A JP28382295A JPH09130146A JP H09130146 A JPH09130146 A JP H09130146A JP 7283822 A JP7283822 A JP 7283822A JP 28382295 A JP28382295 A JP 28382295A JP H09130146 A JPH09130146 A JP H09130146A
Authority
JP
Japan
Prior art keywords
frequency
signal
modulation
voltage
local
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7283822A
Other languages
Japanese (ja)
Inventor
Isao Hayashi
功 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP7283822A priority Critical patent/JPH09130146A/en
Publication of JPH09130146A publication Critical patent/JPH09130146A/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the current consumption and also to secure an automatic frequency control function for the modulation circuit by applying the FM modulation to a voltage control oscillator oscillating by the control voltage via a modulation AF signal and using the oscillator as a reference signal source for a synthesizer of the 2nd local frequency and the reference frequency. SOLUTION: The switches SW1 and SW2 are turned on and off respectively and at the same time the receiving signal of the receiving input Rx undergoes the automatic frequency control AFC. When this AFC is over, the lock voltage is read by an A/D converter of a control part 12. Then the SW1 and SW2 are turned off and on respectively, and the voltage read by the A/D converter is sent via a D/A converter of the part 12. The 2nd local frequency is held to be equal to the frequency that is set in a closed loop mode of a PLL synthesizer. As a result, the 2nd local frequency is equal to the mere oscillation frequency and the modulation AF signal can be modulated from DC. This output is used by the 2nd local signal and also as the reference signal of the PLL synthesizer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、FM無線機におけ
る低周波データ変調回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low frequency data modulation circuit in an FM radio.

【0002】[0002]

【従来の技術】自動車電話機等のFM無線機は、制御信
号に音声周波数帯(300Hz〜3KHz)より低い3
00Hz以下の信号にて搬送波をFM変調し、制御信号
として使用している。
2. Description of the Related Art FM radios such as car telephones have a control signal which is lower than a voice frequency band (300 Hz to 3 KHz).
The carrier wave is FM-modulated by a signal of 00 Hz or less and used as a control signal.

【0003】FM無線機で、Tx波に300Hz以下の
低周波データ等にてFM変調を掛ける方法は色々ある
が、第1に図2に示すように、温度制御水晶発振器(T
CXO)からなる1つのPLLic、ローパスフィルタ
LPFとからなる一つのPLLシンセサイザーを介して
電圧制御発振器(VCO)に変調用AF信号を入力して
FM変調をかけ直接Tx周波数をつくりだす直接方式が
ある。第2に図3に示すように、Rxシンセサイザーか
らの1stローカル周波数と図2で作り出された固定的
な周波数をミキサー(MIX)でPLLシンセサイザー
でつくりだしたものとをミックスしてTx周波数をつく
りだすいわゆるミックス方式がある。
There are various methods for FM-modulating Tx waves with low-frequency data of 300 Hz or less in an FM radio device. First, as shown in FIG. 2, a temperature-controlled crystal oscillator (T
There is a direct method in which a modulation AF signal is input to a voltage controlled oscillator (VCO) via one PLL synthesizer including one PLLic including CXO) and a low-pass filter LPF to perform FM modulation to directly generate a Tx frequency. Second, as shown in FIG. 3, the Tx frequency is created by mixing the 1st local frequency from the Rx synthesizer with the fixed frequency created in FIG. 2 by the mixer (MIX) created by the PLL synthesizer. There is a mix method.

【0004】[0004]

【発明が解決しようとする課題】しかし両方式とも、低
周波信号にてFM変調をかけるためPLLシンセサイザ
ーの設計が難しいという問題がある。一方、基準発振器
TCXOの周波数にも変調用AF信号にてFM変調をか
ければPLLシンセサイザーの設計は楽であるが、この
基準発振器にて制御されている他のPLLシンセサイザ
ー、例えば1stローカルPLLシンセサイザーにも影
響を与えてしまう。
However, both methods have a problem that it is difficult to design a PLL synthesizer because FM modulation is applied to a low frequency signal. On the other hand, if FM modulation is applied to the frequency of the reference oscillator TCXO with the AF signal for modulation, the design of the PLL synthesizer is easy, but it is possible to use another PLL synthesizer controlled by this reference oscillator, for example, the 1st local PLL synthesizer. Will also affect.

【0005】なお、図4に示すように1stローカルP
LLシンセサイザー1と2ndローカルPLLシンセサ
イザー2の2つを使うシステムも考えられる。しかしこ
の場合は2ndローカルPLLシンセサイザー2の設計
が難しくなってしまう。この場合も基準発振器TCXO
にも変調用AF信号にてFM変調をかければPLLシン
セサイザーの設計は楽であるが、前技術と同様、他のP
LLシンセサイザーに影響を与えてしまうという問題が
生じる。
As shown in FIG. 4, the 1st local P
A system using two of the LL synthesizer 1 and the 2nd local PLL synthesizer 2 is also conceivable. However, in this case, it becomes difficult to design the 2nd local PLL synthesizer 2. Also in this case, the reference oscillator TCXO
Also, if FM modulation is applied with a modulating AF signal, designing a PLL synthesizer is easy, but as with the prior art, other P
There arises a problem of affecting the LL synthesizer.

【0006】以上の考察から、基準発振器TCVOを2
個持てば解決するはずであるが、この場合はコストアッ
プになる、また自動周波数調整AFCが難しくなってし
まう。
From the above consideration, the reference oscillator TCVO is set to 2
It would be a solution if you had one, but in this case the cost would increase and the automatic frequency adjustment AFC would become difficult.

【0007】本発明の目的は、かかる問題点を解決した
自動周波数調整機能を持った変調回路を提供することに
ある。
An object of the present invention is to provide a modulation circuit having an automatic frequency adjusting function, which solves the above problems.

【0008】[0008]

【課題を解決するための手段】上記課題を解決するため
に、本発明は、PLLシンセサイザー及び電圧制御発振
器を用いて第1及び第2のローカル周波数を出力する第
1及び第2のPLLを備え、該第2のPLLシンセサイ
ザーからのアナログ信号をA/D変換し、変換されたデ
ジタル信号をロック電圧として保持する制御部を設け、
該制御部により前記第2のPLLシンセサイザーを閉ル
ープとした後に、前記D/A変換器により出力された制
御電圧で発振している電圧制御発振器に変調用AF信号
でFM変調をかけることにより第2のローカル周波数及
び基準周波数用シンセサイザーの基準信号源として使用
するようにした。
In order to solve the above problems, the present invention comprises first and second PLLs that output first and second local frequencies using a PLL synthesizer and a voltage controlled oscillator. A control unit for A / D converting the analog signal from the second PLL synthesizer and holding the converted digital signal as a lock voltage,
After the control section makes the second PLL synthesizer a closed loop, the voltage-controlled oscillator oscillated by the control voltage output by the D / A converter is FM-modulated by the AF signal for modulation. It was used as the reference signal source of the synthesizer for local frequency and reference frequency.

【0009】[0009]

【発明の実施の形態】図1は、本発明の変調回路の実施
形態を示す回路図である。
1 is a circuit diagram showing an embodiment of a modulation circuit of the present invention.

【0010】受信入力3は、RF−AMP4を経て第1
ミキサー5に入力される。第1ミキサー5にはPLLシ
ンセサイザー6からの1stローカル周波数が入力され
てバンドパスフィルタBPFを介して第2ミキサー7に
入力される。第2ミキサー7には、PLLic8、ロー
パスフィルタLPFからの信号に電圧制御発振器VCO
9に変調用AF信号が入力されてFM変調された2nd
ローカル周波数が入力される。第2ミキサー7の出力
は、中間周波数検出回路10に入力される。中間周波数
検出回路10からのAF信号出力はキャンセル回路11
を経て出力される。ここでPLLシンセサイザーを構成
するPLLic8、LPFにはスイッチSW1、SW2
を介して制御部12が接続されている。制御部12はL
PFからのアナログ信号をデジタル信号に変換するA/
D変換器と、デジタル信号をアナログ信号に変換するD
/A変換器を有しており、ロック電圧の保持を行う。ま
た、電圧制御発振器9から出力される2ndローカル周
波数は、分周器1/Nを介してPLLic13に入力さ
れPLLic13とLPFからの信号が変調用AF信号
によって電圧制御発振器14でFM変調され基準信号と
なる。
The reception input 3 is connected to the first via the RF-AMP4.
Input to the mixer 5. The 1st local frequency from the PLL synthesizer 6 is input to the first mixer 5, and is input to the second mixer 7 via the bandpass filter BPF. In the second mixer 7, the voltage from the voltage controlled oscillator VCO is supplied to the signals from the PLLic 8 and the low pass filter LPF.
The modulation AF signal is input to 9 and FM-modulated 2nd
The local frequency is input. The output of the second mixer 7 is input to the intermediate frequency detection circuit 10. The AF signal output from the intermediate frequency detection circuit 10 is canceled by the cancellation circuit 11.
Is output through Here, switches SW1 and SW2 are provided in PLLic8 and LPF which configure the PLL synthesizer.
The control unit 12 is connected via. The control unit 12 is L
A / which converts analog signal from PF to digital signal
D converter and D for converting digital signals to analog signals
It has a / A converter and holds the lock voltage. The 2nd local frequency output from the voltage controlled oscillator 9 is input to the PLLic 13 via the frequency divider 1 / N, the signals from the PLLic 13 and the LPF are FM-modulated by the voltage controlled oscillator 14 by the modulation AF signal, and the reference signal is output. Becomes

【0011】ここで、SW1をオン、SW2をオフとし
た場合、2ndローカル周波数は、PLLic8、LP
F、SW1、抵抗R、コンデンサCのループにてPLL
シンセサイザーを構成する。この状態にて、受信入力R
xの受信信号に自動周波数調整AFCが行われる。AF
C完了後、ロック電圧を制御部12のA/D変換器で読
み込み、SW1をオフ、SW2をオンとして、A/D変
換器で読み込んだ電圧を制御部12のD/A変換器から
送出して2ndローカルの周波数をPLLシンセサイザ
ーの閉ループ時と同一周波数となるようホールドを行
う。次にこのPLLシンセサイザーのPLLic8等の
電源を切る。
When SW1 is turned on and SW2 is turned off, the second local frequency is PLLic8, LP.
PLL in loop of F, SW1, resistor R, capacitor C
Configure a synthesizer. In this state, receive input R
Automatic frequency adjustment AFC is performed on the received signal of x. AF
After the completion of C, the lock voltage is read by the A / D converter of the control unit 12, SW1 is turned off and SW2 is turned on, and the voltage read by the A / D converter is sent from the D / A converter of the control unit 12. Then, the 2nd local frequency is held so as to become the same frequency as the closed loop of the PLL synthesizer. Next, the power supply of the PLLic 8 etc. of this PLL synthesizer is turned off.

【0012】そうすると2ndローカル周波数は単なる
発振器となり、変調用AF信号はDCからの変調が可能
となる。この出力を2ndローカル信号で使うと共に、
PLLシンセサイザーの基準信号として使用する。
Then, the 2nd local frequency becomes a mere oscillator, and the modulation AF signal can be modulated from DC. This output is used for 2nd local signal,
Used as a reference signal for the PLL synthesizer.

【0013】Tx周波数の変調はこの変調のかかった基
準信号と必要に応じて電圧制御発振器VCO14にも変
調用AF信号を外乱として与えることによって、DCか
らの理想的な変調器が構成される。2ndローカル信号
は、電圧制御発振器9にて変調用AF信号にてFM変調
がかかっているため、中間周波数検出回路IFDET出
力のAF信号中に変調用AF信号が復調されてしまう、
よってこれをキャンセルするためのキャンセル回路11
を必要に応じて付加する。
In the modulation of the Tx frequency, an ideal modulator from DC is constructed by giving the modulated reference signal and, if necessary, the modulating AF signal to the voltage controlled oscillator VCO 14 as well. Since the 2nd local signal is FM-modulated by the voltage-controlled oscillator 9 with the modulating AF signal, the modulating AF signal is demodulated in the AF signal output from the intermediate frequency detection circuit IFDET.
Therefore, a cancel circuit 11 for canceling this
Is added as needed.

【0014】以上にて、通話を行うわけであるが、2n
dローカルは通話中は制御部12からのD/A変換器に
よって変換された電圧にて周波数をホールドしてあるた
め、AFC回路及び制御部12のコントロール下に置か
れていることとなり、通話中のAFCを前記電圧のコン
トロールにて達成される。
With the above, a call is made.
Since the d-local holds the frequency with the voltage converted by the D / A converter from the control unit 12 during the call, it is placed under the control of the AFC circuit and the control unit 12, and the call is in progress. AFC is achieved by controlling the voltage.

【0015】[0015]

【発明の効果】以上説明したように、本発明の構成なら
びに方法によれば、変調回路の低消費電流化が達成され
るとともに、自動周波数調整機能も達成される。
As described above, according to the configuration and method of the present invention, the current consumption of the modulation circuit can be reduced and the automatic frequency adjustment function can be achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の変調回路の回路図。FIG. 1 is a circuit diagram of a modulation circuit of the present invention.

【図2】従来の回路図。FIG. 2 is a conventional circuit diagram.

【図3】従来の回路図。FIG. 3 is a conventional circuit diagram.

【図4】従来の回路図。FIG. 4 is a conventional circuit diagram.

【符号の説明】[Explanation of symbols]

1 1stローカルPLLシンセサイザー 2 2ndローカルPLLシンセサイザー 3 受信入力 4 RF−AMP 5 第1ミキサー 6 PLLシンセサイザー 7 第2ミキサー 8 PLLic 9 電圧制御発振器 10 中間周波数検出回路 11 キャンセル回路 12 制御部 13 PLLic 14 電圧制御発振器 1 1st local PLL synthesizer 2 2nd local PLL synthesizer 3 reception input 4 RF-AMP 5 1st mixer 6 PLL synthesizer 7 2nd mixer 8 PLLic 9 voltage control oscillator 10 intermediate frequency detection circuit 11 cancel circuit 12 control unit 13 PLLic 14 voltage control Oscillator

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】PLLシンセサイザー及び電圧制御発振器
を用いて第1及び第2のローカル周波数を出力する第1
及び第2のPLLを備え、該第2のPLLシンセサイザ
ーからのアナログ信号をA/D変換し、変換されたデジ
タル信号をロック電圧として保持する制御部を設け、該
制御部により前記第2のPLLシンセサイザーを閉ルー
プとした後に、前記D/A変換器により出力された制御
電圧で発振している電圧制御発振器に変調用AF信号で
FM変調をかけることにより第2のローカル周波数及び
基準周波数用シンセサイザーの基準信号源として使用す
るようにしたことを特徴とするFM無線機における低周
波データ変調回路。
1. A first for outputting a first and a second local frequency using a PLL synthesizer and a voltage controlled oscillator.
And a second PLL, the analog signal from the second PLL synthesizer is A / D converted, and a control unit for holding the converted digital signal as a lock voltage is provided, and the second PLL is operated by the control unit. After making the synthesizer a closed loop, FM modulation is applied to the voltage controlled oscillator oscillated by the control voltage output by the D / A converter by the AF signal for modulation, so that the second local frequency and reference frequency synthesizer A low frequency data modulation circuit in an FM radio, characterized by being used as a reference signal source.
JP7283822A 1995-10-31 1995-10-31 Low frequency data modulation circuit for fm radio unit Pending JPH09130146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7283822A JPH09130146A (en) 1995-10-31 1995-10-31 Low frequency data modulation circuit for fm radio unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7283822A JPH09130146A (en) 1995-10-31 1995-10-31 Low frequency data modulation circuit for fm radio unit

Publications (1)

Publication Number Publication Date
JPH09130146A true JPH09130146A (en) 1997-05-16

Family

ID=17670605

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7283822A Pending JPH09130146A (en) 1995-10-31 1995-10-31 Low frequency data modulation circuit for fm radio unit

Country Status (1)

Country Link
JP (1) JPH09130146A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100501182B1 (en) * 1998-07-07 2005-09-26 삼성전기주식회사 Broadband 2-Input Modulation Circuit
CN105634484A (en) * 2015-12-24 2016-06-01 熊猫电子集团有限公司 Frequency modulation continuous wave signal source based on external triggering

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100501182B1 (en) * 1998-07-07 2005-09-26 삼성전기주식회사 Broadband 2-Input Modulation Circuit
CN105634484A (en) * 2015-12-24 2016-06-01 熊猫电子集团有限公司 Frequency modulation continuous wave signal source based on external triggering

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