JPH0799448A - Pll frequency synthesizer circuit - Google Patents

Abstract

PURPOSE:To realize a PLL frequency synthesizer circuit capable of obtaining a signal whose oscillating frequency is maade constant even at frequency other than a multiple of N(frXN) of a reference frequency fr. CONSTITUTION:The PLL frequency synthesizer circuit is provided with a reference signal oscillator 21, a reference frequency divider 22, a frequency converter 23, a band pass filter(BPF) 24, a phase comparator (PD) 25, a loop filter(LPF) 26, a VCO(voltage controlled oscillator) 27, a frequency divider 28, comparison frequency dividers 29, 30 and a CPU 31, and a reference signal fr obtained by 1/R frequency division to a reference frequency fLCXO of the reference signal oscillator 21 is frequency-converted (fL1=fr+ or -fd/N) with a signal through the frequency divider 28 and the comparison frequency divider 29 to generate a reference signal and the phase of the reference signal and the phase of a comparison signal fr'(=fVCO/N) resulting from 1/N frequency division to a signal fVCO of the VCO 27 are compared.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a PLL (Phase Locked).
Loop) frequency synthesizer circuit, and more particularly, to a multi-circuit PLL frequency synthesizer circuit for high-speed frequency switching.

[0002]

2. Description of the Related Art A PLL frequency synthesizer circuit is used for a tuning circuit of mobile band communication equipment such as a digital cordless telephone and a mobile telephone. The PLL frequency synthesizer circuit is an oscillator that oscillates an accurate frequency and that can be easily set to a large number of values having different frequencies at equal intervals, and is an indispensable local source for mobile band communication equipment. There is.

FIG. 8 is a circuit diagram of a conventional PLL frequency synthesizer circuit. In FIG. 8, the PLL frequency synthesizer circuit 10 includes a reference signal generator 11, a frequency divider 12, a phase comparator (PD) 13, a loop filter (LP).
F) 14, VCO (Voltage Controlled Oscillator) 15, comparison frequency divider 16 and CPU 17
It is composed of

The frequency divider 12 and the phase comparator (PD) 13
The comparison frequency divider 16 constitutes a PLL circuit as a whole, and the CPU 17 controls the PLL circuit so as to output a control signal to each section to obtain a predetermined synthesizer output. As the reference signal generator 11, a crystal oscillator having a high stability is used as a reference frequency f _tcxo oscillator. When the reference frequency f _tcxo is input from the reference signal generator 11, the frequency divider 12
_Divides the reference frequency f _tcxo of the reference signal generator 11 by R,
The reference signal f _r (= f _tcxo / R) _{divided by} R is output to the phase comparator (PD) 13.

The phase comparator (PD) 13 has a reference signal f _r (= f _tcxo / R) _divided by R by the frequency divider 12 and a VCO 15
Signal f _vco is compared with the comparison signal f _r ′ (= f _vco / N) obtained by _dividing the signal f _vco by N by the comparison frequency divider 16, and the error signal is output to the loop filter (LPF) 14. The loop filter (LPF) 14 integrates the input error signal and converts it into an error voltage, and applies this error voltage to the control terminal of the VCO 15. As a result, the VCO 15 operates so that f _r = f _r ′ and obtains a signal in which the frequency of f _vco = f _r × N is kept constant.

[0006]

By the way, such a conventional PLL frequency synthesizer circuit has a drawback that the settable frequency is only a frequency which is N times (f _r × N) of the reference frequency f _r . . For example, in the conventional PLL frequency synthesizer circuit shown in FIG. 8, the case where the frequency of the following channel ch (carrier) scheduled to be used in the digital cordless telephone system is set is taken as an example. Channel spacing is 300 kHz
z. 1ch 1895.15 [MHz] 2ch 1895.45 [MHz] ... 77ch 1917.95 [MHz]

Now, the reference frequency f _tcxo = 12 [MHz] is input from the reference signal oscillator 11, and the frequency divider 12 divides the reference frequency f _tcxo of the reference signal oscillator 11 by R = 40 and divides by R. and outputs the reference signal f _r = 300kHz to the phase comparator (PD) 13. Phase comparator (PD) 13
Is a reference signal f _r = 300 [k
Hz] and the comparison signal f _r '(= f _vco / N) obtained by dividing the signal f _vco of the VCO 15 by the comparison frequency divider 16 by phase, and outputting the error signal to the loop filter (LPF) 14. . Therefore, the frequency that can be set by this PLL frequency synthesizer circuit is (f _tc x _o / R) × N,
The frequency that can be set when f _tcxo = 12 [MHz] and R = 40 is 0.3 [MHz] × N. Taking the case of 1ch as an example (same for other channels), 189
Since 5.15 = 0.3 × N, N = 6317.16
Since N is not an integer, it cannot be set.

Therefore, an object of the present invention is to provide a PLL frequency synthesizer circuit capable of obtaining a signal with a constant oscillation frequency even at a frequency other than N times (f _r × N) times the reference frequency f _r. There is.

[0009]

In order to achieve the above object, a PLL frequency synthesizer circuit according to the invention of claim 1 is provided with a reference signal generator for outputting a reference frequency signal and a reference frequency output by the reference signal generator. Frequency conversion means for frequency-converting a signal, a voltage-controlled oscillator for outputting a signal having a different frequency according to an applied voltage, a frequency divider for frequency-dividing a predetermined frequency signal output from the voltage-controlled oscillator, and the frequency divider. Phase-comparing the frequency-divided signal and the frequency-converted reference frequency signal output by the frequency conversion means, and outputting a phase comparator that outputs an error signal of the phase, and the error signal output by the phase comparator as a voltage. And a loop filter for converting the signal into a signal and outputting it as an oscillation control voltage to the voltage controlled oscillator.

According to a second aspect of the present invention, a reference signal generator for outputting a reference frequency signal, a voltage controlled oscillator for outputting a signal having a different frequency according to an applied voltage, and a predetermined frequency signal output by the voltage controlled oscillator. A frequency conversion means for frequency conversion, a frequency divider for frequency-converting the frequency-converted signal, a frequency-divided signal by the frequency divider, and a reference frequency signal output by the reference signal generator. A phase comparator that compares phases and outputs an error signal of the phase, and a loop filter that converts the error signal output by the phase comparator into a voltage signal and outputs the voltage signal to the voltage controlled oscillator as an oscillation control voltage are provided. ing.

According to a third aspect of the present invention, a reference signal generator for outputting a reference frequency signal, a voltage controlled oscillator for outputting a signal having a different frequency according to an applied voltage, and a predetermined frequency signal output by the voltage controlled oscillator. A frequency divider that divides
Frequency conversion means for frequency-converting the frequency-divided signal by the frequency divider, phase-comparing the frequency-converted signal by the frequency conversion means and the reference frequency signal output by the reference signal generator, and an error signal of the phase And a loop filter for converting the error signal output by the phase comparator into a voltage signal and outputting it as an oscillation control voltage to the voltage controlled oscillator.

The frequency conversion means may have a frequency converter for frequency-converting based on the reference frequency signal output from the reference signal generator, as described in claim 4, for example.

As a preferred mode, the frequency conversion means is a first frequency conversion means for performing frequency conversion based on a reference frequency signal output from the reference signal generator, as described in claim 5, for example. And a second frequency conversion means for frequency-converting the signal frequency-converted by the first frequency conversion means with the reference frequency signal output from the reference signal oscillator. The frequency conversion means may include a bandpass filter that passes a signal in a predetermined band of the frequency-converted signals, as described in claim 6, for example.

[0014]

According to the present invention, the reference frequency signal output from the reference signal generator is frequency-converted by the frequency conversion means, and the predetermined frequency signal output from the voltage controlled oscillator is frequency-divided by the frequency divider. . The phase comparator compares the frequency of the frequency-divided signal by the frequency divider with the reference frequency signal whose frequency is converted by the frequency conversion means. The error signal from the phase comparator is converted into an error voltage by the loop filter and input to the control terminal of the voltage controlled oscillator, and the voltage controlled oscillator outputs a frequency signal whose output frequency is kept constant. Therefore, the reference frequency f _r
It is possible to obtain a signal with a constant oscillation frequency even at a frequency other than N times (f _r × N).

According to the second aspect of the invention, first, when the voltage controlled oscillator outputs a signal having a different frequency according to the applied voltage, the predetermined frequency signal output from the voltage controlled oscillator is frequency converted by the frequency conversion means. The frequency-converted signal is further frequency-converted by the frequency conversion means, and is frequency-divided by the frequency divider. The phase comparator compares the phase of the frequency-divided signal from the frequency divider with the reference frequency signal output from the reference signal generator. And the error signal from the phase comparator is
It is converted into an error voltage by the loop filter and input to the control terminal of the voltage controlled oscillator, and the voltage controlled oscillator outputs a frequency signal whose output frequency is kept constant. Therefore, it is possible to obtain a signal with a constant oscillation frequency even at frequencies other than N times (f _r × N) the reference frequency f _r .

According to the third aspect of the present invention, the reference frequency signal output from the reference signal generator is frequency-converted by the frequency conversion means, and the voltage controlled oscillator outputs a signal having a different frequency according to the applied voltage. The predetermined frequency signal output from the oscillator is divided by the frequency divider. The phase comparator compares the phase of the frequency-divided signal from the frequency divider with the reference frequency signal output from the reference signal generator. The error signal from the phase comparator is converted into an error voltage by the loop filter and input to the control terminal of the voltage controlled oscillator, and the voltage controlled oscillator outputs a frequency signal whose output frequency is kept constant. Therefore,
It becomes possible to obtain a signal with a constant oscillation frequency in N times (f _r × N) except the frequency of the reference frequency f _r.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a diagram showing a first embodiment of a PLL frequency synthesizer circuit according to the present invention.

First, the structure will be described. FIG. 1 is a block diagram of a PLL frequency synthesizer circuit. In FIG. 1, P
The LL frequency synthesizer circuit 20 includes an original signal oscillator 2
1. Reference frequency divider 22, mixer 23, bandpass filter (BPF) 24, phase comparator (PD) 25, loop filter (LPF) 26, VCO (voltage controlled oscillator) 27,
It is composed of a frequency divider 28, comparison frequency dividers 29 and 30, and a CPU 31. As the original signal oscillator 21, a crystal oscillator having high stability is used as the original frequency signal f _tcxo oscillator. As a crystal oscillator, a voltage-controlled crystal oscillator that has a voltage control terminal so that the oscillation frequency can be minutely changed, and a temperature-compensated crystal oscillator that stabilizes the frequency against temperature changes by combining with a frequency compensation circuit that has temperature characteristics May be used.

The reference frequency divider 22 frequency-divides the original frequency signal f _tcxo of the original signal oscillator 21 and outputs the R-frequency-divided reference frequency signal f _r (= f _tcxo / R) to the mixer 23. Here, R represents indicates a frequency dividing ratio for determining the channel spacing f _r.
The frequency divider 28 receives the original frequency signal f from the original signal oscillator 21.
A signal f _d (= f _tcxo / X) _obtained by _{dividing tcxo} by X and _dividing by X
Is output to the comparison frequency divider 29. The comparison frequency divider 29 frequency-divides the X frequency-divided signal f _d (= f _tcxo / X) by N and outputs the N frequency-divided signal (f _d / N) to the mixer 23. Here, X represents the frequency division ratio that determines the frequency f _d to be shifted, and N represents the frequency division ratio that determines the channel.

The mixer 23 mixes the original frequency signal f _tcxo of the original signal oscillator 21 with the signal _divided by R by the reference frequency divider 22 and the signal passed through the frequency divider 28 and the comparison frequency divider 29 (f _t1
= Fr ± f _d / N) to generate a reference frequency signal. The band pass filter (BPF) 24 is a desired signal (f _t1 = f _r + f _d / N or f _t1 among the signals mixed by the mixer 23).
= F _r −f _d / N). Phase comparator (P
D) 25 compares the phase of the signal from the bandpass filter (BPF) 24 and the comparison signal f _r ′ (= fv _co / N) obtained by dividing the signal f _vco of the VCO 27 by N by the comparison frequency divider 30, The error signal is output to the loop filter (LPF) 26.

The loop filter (LPF) 26 is composed of a low-pass filter, integrates the error signal from the phase comparator (PD) 25 to remove high frequency components and converts it into an error voltage, and this error voltage is VCO 27. Add to the control terminal of.
VCO27 operates such that f _t1 = fr 'by the error voltage from the loop filter _{(LPF) 26 f vco = f} r
It outputs a frequency signal in which the frequency of × N ± f _d is kept constant.

The comparison frequency divider 30 frequency-divides the output signal f _vco from the VCO ₂₇ by N, and compares the comparison signal f _r ′ (= f _vco / N).
Is fed back to the phase comparator (PD) 25. The frequency of the synthesizer is set by changing the frequency division ratio N. The CPU 31 includes the reference frequency divider 22 and the frequency divider 2 described above.
8. Control signals are output to the comparison frequency dividers 29 and 30 and the band pass filter (BPF) 24 to control each unit so as to obtain a predetermined synthesizer output. That is, the CPU
Reference numeral 31 designates a pass band of the band pass filter (BPF) 24, a frequency division ratio R for determining the channel interval by the reference frequency divider 22, and a frequency division ratio for determining a frequency to be shifted by the frequency divider 28. X is set, and the frequency division ratio N for determining the channels is set by the comparison frequency dividers 29 and 30. The original signal oscillator 21 and the reference frequency divider 22 constitute a reference signal generator, and the mixer 23, the band pass filter (BP)
F) 24, a frequency divider 28 and the comparison frequency divider 29 constitute a frequency converting means for frequency converting a reference frequency signal f _r.

Next, the operation of the first embodiment will be described. First, the CPU 31 causes the bandpass filter (B
The PF) 24, the reference frequency divider 22, the frequency divider 28, and the comparison frequency dividers 29 and 30 are set. Original signal oscillator 21
The original frequency signal f _tcxo oscillated by the reference frequency divider 22
Then, the reference frequency divider 22 _divides the original frequency signal f _tcxo from the original signal oscillator 21 by R (determines the channel interval based on R).

On the other hand, in the frequency divider 28, the original signal oscillator 21
The original frequency signal f _{tcxo from} is _divided by X (which determines the frequency to be shifted based on X), and the _divided signal f is _divided by X.
_d (= f _t c _xo / X) is input to the comparison frequency divider 29. In the comparison frequency divider 29, the X frequency- _divided signal (f _tcxo / X) is further _{frequency-divided by} N (channel is determined based on N), and the N _{frequency-divided} signal (f _d / N) is mixed. 23 is output. That is, in _addition to the R frequency _division of the original frequency signal f _tcxo by the normal reference frequency divider 22 for _dividing the original frequency signal f _tcxo by R, the original frequency of the original signal oscillator 21 is _divided by the frequency divider 28 and the comparison frequency divider 29. A signal is _generated by _{dividing the} frequency signal f _tcxo by X · N.

The reference frequency signal f _r (= f _tcxo / R) _divided by R by the reference divider 22 and the signal _divided by N (f _d / N) by the comparison divider 29 are mixed together. is output to the 23, the mixer 23, a reference frequency signal f _r and the frequency divider 28 and the comparison frequency divider 29 an original frequency signal f _TCXO with reference frequency divider 22 is R dividing the original signal oscillator 21 through The mixed signal (f _t1 = f _r ± f _d / N) is performed by the signal and output to the band pass filter (BPF) 24. In the bandpass filter (BPF) 24, a desired signal (f _t1 = f _r + f _d / N or f _t1 = f of the signals mixed by the mixer 23 is selected.
_r -f _d / N) only it is passed through a predetermined desired signal _{(e.g., f t1 = f r + f} d / N) is outputted to the phase comparator (PD) 25.

[0026] That is, the reference frequency signal f _r of the original frequency signal f _TCXO was R divider by reference divider in the prior art (=
Since f _tcxo / R) is directly output to the phase comparator (PD), the settable frequency is N of the original frequency signal f _r .
Although the frequency is only doubled (f _r × N), the signal input to the phase comparator (PD) 25 is frequency-converted from the original frequency signal f _tcxo (f _t1 = f _tcxo / R ±) in this embodiment. f _d /
Varying the frequency because they be input as the reference frequency signal N) signal to N times the original frequency signal f _r (f _r × N) except for the frequency setting value _{(f r × N ± f d} ) Will be able to.

When the signal from the band pass filter (BPF) 24 is input to the phase comparator (PD) 25, the phase comparator (PD) 25 causes the band pass filter (BP) to pass.
F) The signal from v 24 and the signal f _vco of VCO ₂₇ are _divided by N by the comparison frequency divider 30 to _obtain a comparison signal f _r ′ (= f _vco /
N) and the error signal are output to a loop filter (LPF) 26. Loop filter 2 (LP
In F2) 36, the error signal from the phase comparator (PD) 25 is integrated and converted into an error voltage, and this error voltage is VCO.
Add to 27 control terminals. The VCO 27 operates by the error voltage from the loop filter (LPF) 26 so that f _t1 = f _r ′, and the frequency signal f _vco = f _t1 × N = f _r × N ± f _d is kept constant. Is output. Also, VCO
The output signal f _{vco of} 27 is fed back to the comparison frequency divider 30,
And divided by N by a comparison frequency divider 30, compares the signal f _r '
It is fed back to the phase comparator (PD) 25 as (= f _vco / N).

Thus, in this embodiment, the original signal oscillator 2
1. Reference frequency divider 22, mixer 23, bandpass filter (BPF) 24, phase comparator (PD) 25, loop filter (LPF) 26, VCO (voltage controlled oscillator) 27,
The frequency divider 28, the comparison frequency dividers 29 and 30, and the CPU 31 are provided, and the reference frequency signal f _r obtained by _dividing the original frequency signal f _tcxo of the original signal oscillator 21 by R is _supplied to the frequency divider 28 and the comparison frequency divider 29. Mixed by the passed signal (f _d / N) (f _t1 =
f _r ± f _d / N) and a band pass filter (BPF) 24
A frequency-converted signal is generated via the frequency conversion signal, and the frequency-converted signal and the comparison signal f _r ′ (= f _vco / N) obtained by dividing the signal f _vco of the VCO ₂₇ by N are compared in phase. original frequency signals f _r N times (f _r × N) results in a frequency setting value _{f d (= f tcxo / X} ) frequency can be a change made, even at frequencies other than N times the original frequency signals f _r A signal with a constant oscillation frequency can be obtained.

The above-mentioned operation will be described in more detail with reference to specific numerical values. The prerequisite condition is, for example, the case where the frequency of the channel ch in the conventional PLL frequency synthesizer circuit shown in FIG. 8 is set, and the channel interval is 300 kHz. Now, the original frequency signal f _tcxo from the original signal oscillator 21 = 12 [MH
z] is input, the reference frequency divider 22 frequency-divides the original frequency signal f _tcxo of the original signal oscillator 21 by R = 40, and outputs the frequency-divided reference frequency signal f _r = 300 [kHz] to the mixer 23. To do.

On the other hand, in the frequency divider 28, the original signal oscillator 21
The original frequency signal f _tcxo = 12 MHz from X is X (= 24
0) frequency- _{divided and} X- _divided signal f _d (= f _tcxo / X =
0.05 [MHz]) is further divided by N in the comparison frequency divider 29, and the signal (0.05 / N [MHz]) is mixed by the mixer 2
Input to 3. The mixer 23 mixes the reference frequency signal f _r = 0.3 [MHz] input from the reference frequency divider 22 with the signal input from the comparison frequency divider to obtain f _t1 (= 0.3).
± 0.05 / N [MHz]) with band pass filter (B
PF) 24 to output a bandpass filter (BPF) 2
4 is a frequency in a predetermined band (for example, f _t1 (= 0.3 +
0.05 / N [MHz]) signal from the phase comparator (P
Output to D).

Further, the phase comparator (PD) has V
A signal f _r '(= f _vco / N [MHz]) obtained by dividing the output signal from the CO 27 by N by the comparison frequency divider 30 is input, and the f _t1 (= 0.3 + 0.05 / N [MHz]) is input. And f _r '
The phase is compared with (= f _vco / N [MHz]), and the error signal is output to the loop filter (LPF) 26.

[0032] Thus, the frequency can be set in the PLL frequency synthesizer circuit 20 is because it is _{ft 1 = f r 'f vco} = f t1 × N = (f r + f d / N) × N, f
_The frequency that can be set when _tcxo = 12 [MHz], R = 40, and X = 240 is 0.3 [MHz] x N + 0.05.
[MHz]. Taking the case of 1ch as an example (the same applies to other channels), 1895.15 = 0.3 × N
Since +0.05, N = 6317, and N is an integer, so that the target frequency f _vco can be set. That is,
It is possible to change the frequency f _d (= f _tcxo / X) to the frequency setting value that is N times (f _r × N) of the original frequency signal f _r .

Second Embodiment FIG. 2 is a diagram showing a second embodiment of the present invention, which is an example applied to a PLL frequency synthesizer circuit. In the description of this embodiment, the same components as those in the first embodiment will be designated by the same reference numerals, and the description of the overlapping parts will be omitted.

First, the structure will be described. FIG. 1 is a block diagram of a PLL frequency synthesizer circuit. In FIG. 1, P
The LL frequency synthesizer circuit 40 uses the original signal oscillator 2
1, reference frequency divider 41, phase comparator (PD) 42, loop filter (LPF) 43, VCO (voltage controlled oscillator) 4
4, frequency divider 45, mixer 46, bandpass filter (B
PF) 47, a comparison frequency divider 48 and a CPU 49. The reference frequency divider 41 frequency-divides the original frequency signal f _tcxo of the original signal oscillator 21 and outputs the R-frequency-divided reference frequency signal f _r (= f _tcxo / R) to the phase comparator (PD) 42. . Here, R indicates a channel interval. The phase comparator (PD) 42 is a source frequency signal f of the source signal oscillator 21.
Reference frequency signal f _{r obtained} by _{dividing tcxo} by R by the reference divider 41
(= F _tcxo / R) and bandpass filter (BPF) 43
Comparison signal f _{t2 obtained by dividing the} signal of
The phase of (= fv _co ± f _d ) / N is compared, and the error signal is output to the loop filter (LPF) 43.

The loop filter (LPF) 43 is composed of a low-pass filter, integrates the error signal from the phase comparator (PD) 42 to remove the high frequency component and converts it into an error voltage, and this error voltage is VCO 44. Add to the control terminal of.
The VCO 44 operates so that f _r = f _t 2 by the error voltage from the loop filter (LPF) 43, and f _vco = f _r ×
A frequency signal with the frequency of N ± f _d kept constant is output. The frequency divider 45 divides the original frequency signal f _tcxo from the original signal oscillator 21 by X and divides it by X to _obtain a signal f _d (= f _tcxo /
X) is output to the mixer 46. Here, X represents the frequency to be shifted.

The mixer 46 mixes the output signal f _vco from the VCO 44 with the signal f _d (= f _tcxo / X) _obtained by _dividing the original frequency signal f _tcxo of the original signal oscillator 21 by X by the frequency divider 45 ( f _v c _o ± f _d ). Bandpass filter (BPF) 4
7 passes only the desired signal (f _vco + f _d or f _vco −f _d ) among the signals frequency-converted by the mixer 46. The comparison frequency divider 48 divides the signal (for example, f _vco −f _d ) from the band pass filter (BPF) 47 by N and divides it by N (for example, (f _vco −f _d ) / N). To the phase comparator (PD) 42.

The CPU 49 outputs a control signal to the reference frequency divider 41, the frequency divider 45, the bandpass filter (BPF) 47 and the comparison frequency divider 48 to control each section so as to obtain a predetermined synthesizer output. . That is, the CPU 49
The reference frequency divider 41 sets the channel interval based on R, the frequency divider 45 sets the frequency to shift based on X, the pass band frequency of the bandpass filter (BPF) 47 is set, and the comparison frequency divider 48 is set. To set the channel based on N. The mixer 46, the bandpass filter (BP
F) 47 constitutes frequency conversion means for frequency-converting the output signal f vco from the VCO 44.

Next, the operation of the second embodiment will be described. First, the CPU 43 sets the reference frequency divider 41, the frequency divider 45, the bandpass filter (BPF) 47, and the comparison frequency divider 48. The original frequency signal f _tcxo oscillated by the original signal oscillator 21 is input to the reference frequency divider 41 and the frequency divider 45, and the original frequency signal f _tcxo from the original signal oscillator 21 is frequency- _divided by the reference frequency divider 41. .

On the other hand, in the frequency divider 45, the original signal oscillator 21
The original frequency signal f _{tcxo from} is _divided by X, and the X- _divided signal f _d (= f _tcxo / X) is input to the mixer 46.
In the mixer 46, the output signal f _vco from the VCO 44 is
The original frequency signal f _tcxo of the original signal oscillator 21 is mixed with a signal f _d (= f _tcxo / X) _obtained by _dividing the original frequency signal f _tcxo by the frequency divider 45 (f _vco ± f
_d ) and output to the bandpass filter (BPF) 47. The bandpass filter (BPF) 47 includes the mixer 4
Among the signals mixed by 6, only the desired signal (f _vco + f _d or f _vco −f _d ) is passed, and a predetermined desired signal (for example, f _vco −fd) is output to the comparison frequency divider 48 and compared. signal from the band pass filter (BPF) 47 by divider 48 (e.g., f _vco -f _d) is divided by N, N divider signal _{(e.g., (f vco -f d) /} N) phase It is output to the comparator (PD) 42.

That is, the R of the original frequency signal f _tcxo is _divided by the normal reference frequency divider 41 for _dividing the original frequency signal f _tcxo by R.
Separately from the frequency division, the output signal f _vco from the VCO 44 is mixed with the signal f _d (= f _tcxo / X) _obtained by _dividing the original frequency signal f _tcxo of the original signal oscillator 21 by the frequency divider 45 (f _vco ± f _d )
Then, the mixed signal is converted into a bandpass filter (BP
F) It is converted to a predetermined frequency through 47, and the comparison frequency divider 4
It is divided by N by 8 and output to the phase comparator (PD) 42.

Here, in the conventional example, since the signal (f _vco / N) obtained by _dividing the output signal f _vco from the VCO by N is output as it is to the phase comparator (PD), the settable frequency is the original frequency signal f. _{Although the} frequency was only N times _r (fr × N), the output signal f from the VCO 44 in this embodiment is f.
_Since a signal based on the signal obtained by frequency-converting _vco is input to the phase comparator (PD) 42 for phase comparison, the frequency is set to a frequency setting value other than N times (f _r × N) of the original frequency signal f _r. Will be able to change.

The reference frequency signal f _r (= f _tcxo /) obtained by _dividing the input original frequency signal f _tcxo of the original signal oscillator 21 by the reference frequency divider 41 by the phase comparator (PD) 42.
R) and the signal of the band pass filter (BPF) 43 are divided by N by the comparison frequency divider 48 to _obtain a comparison signal f _t2 (= (f _vco
± f _d ) / N) is compared in phase, and the error signal is output to the loop filter (LPF) 43. The loop filter 2 (LPF2) 43 integrates the error signal from the phase comparator (PD) 42 to convert it into an error voltage, and applies this error voltage to the control terminal of the VCO 44. The VCO 44 receives f _r due to the error voltage from the loop filter (LPF) 26.
= F _t2 and outputs a frequency signal in which the frequency of f _vco = f _t2 × N is kept constant. Also, VCO44
Output signal f _vco is fed back to the mixer 46 and the band pass filter (BPF) 43, frequency-converted, and fed back to the phase comparator (PD) 42.

The above-mentioned operation will be described in more detail with reference to specific numerical values. The prerequisite condition is, for example, the case where the frequency of the channel ch in the conventional PLL frequency synthesizer circuit shown in FIG. 8 is set, and the channel interval is 300 kHz. Now, the original frequency signal f _tcxo from the original signal oscillator 21 = 12 [MH
z] are input, the reference divider 41 is the original frequency signal f _TCXO of the original signal oscillator 21 and R = 40 divides, R divider and reference frequency signal f _r = 300 phase comparators [kHz] (P
D) Output to 42.

On the other hand, in the frequency divider 45, the original signal oscillator 21
The original frequency signal f _tcxo = 12 MHz from X is X (= 24
0) frequency- _{divided and} X- _divided signal f _d (= f _tcxo / X =
50 [kHz]) is input to the mixer 46. Mixer 4
6, the output signal f _vco from the VCO 44 is mixed with the signal f _d (= 50 [kHz]) obtained by _dividing the original frequency signal f _tcxo = 12 [MHz] of the original signal oscillator 21 by the frequency divider 45 ( f _vco ± f _d ) and band pass filter (BPF)
It is output to 47. Band pass filter (BPF) 47
Of the signals mixed by the mixer 46, for example, the lower band pass signal (f _vco −f _d = f _vco −0.05 [MH
z]) only is passed. The signal (f _vco −f _d from the band pass filter (BPF) 47 is output by the comparison frequency divider 48.
= F _vco −0.05 [MHz]) is divided by N, and the N divided signal (here, (f _vco −0.05) / N) is output to the phase comparator (PD) 42. .

The phase comparator (PD) 42 is the reference frequency divider 4
Reference frequency signal divided by R by 1 f _r = 300 [kHz]
And a comparison signal f _{t2 obtained} by frequency-converting the signal f _vco of the VCO 15 and dividing the frequency by N are output, and the error signal is output to the loop filter (LPF) 43. Therefore, this PL
The frequency that can be set by the L frequency synthesizer circuit 40 is f
Since r = f _t2 , f _vco = f _r × N + f _d , and f _tcxo
= 12 [MHz], R = 40, X = 240, the frequency that can be set is f _vco = 0.3 [MHz] × N + 0.0
It is 5 [MHz]. Taking the case of 1 channel as an example (the same applies to other channels), 1895.15 = 0.3 ×
Since N + 0.05, N = 6317, and N is an integer, so that the target frequency f vco can be set. That is, it is possible to change the _{f d (= f tcxo / X} ) becomes the frequency to the frequency setting value N becomes doubled (f _r × N) of the original frequency signals f _r.

Third Embodiment FIG. 3 is a diagram showing a third embodiment of the present invention, in which the frequency characteristic of the second embodiment is further improved. In the description of this embodiment, the same components as those in the second embodiment will be designated by the same reference numerals, and the description of the overlapping parts will be omitted.

First, the structure will be described. FIG. 3 is a block diagram of the PLL frequency synthesizer circuit. The PLL frequency synthesizer circuit 40 includes an original signal oscillator 21 and a reference frequency divider 4.
1, phase comparator (PD) 42, loop filter (LP
F) 43, VCO (voltage controlled oscillator) 44, frequency divider 4
5, mixer 46, mixer 61, bandpass filter (B
PF) 47, 62, a comparison frequency divider 48, and a CPU 63. The mixer 61 _divides the original frequency signal f _tcxo from the original signal oscillator 21 into the original frequency signal f _tcxo of the original signal oscillator 21 by the frequency divider 45 to _divide the signal f _d (= f).
_tcxo / X) (f _tcxo ± f _d ). The band pass filter (BPF) 62 is a desired signal (f _tcxo + f _d or f _tcxo −f _d ) of the signals whose frequency is converted by the mixer 61.
Only pass through. The CPU 63 uses the reference frequency divider 4
1. Control signals are output to the frequency divider 45, the bandpass filter (BPF) 47, and the comparison frequency divider 48 to control each unit so as to obtain a predetermined synthesizer output. Mixer 4
6, the bandpass filter (BPF) 47, the mixer 61, and the bandpass filter (BPF) 62 constitute first frequency conversion means and second frequency conversion means, respectively.

In the above configuration, the original frequency signal f _tcxo oscillated by the original signal oscillator 21 is input to the reference frequency divider 41 and the frequency divider 45, and the frequency divider 45 outputs the original frequency signal from the original signal oscillator 21. f _tcxo is frequency- _divided by X, and the X-frequency- _divided signal f _d (= f _tcxo / X) is input to the mixer 61. In mixer 61, the original signal from the oscillator 21 frequency divider 45 an original frequency signal f _TCXO input without passing the original signal oscillator 21 of the original frequency signal f _TCXO with divider 45 X dividing the signal f Mixed with _d (= f _tcxo / X) (f _tcx o ± f _d )
And output to the bandpass filter (BPF) 62. The bandpass filter (BPF) 62 is a mixer 61.
In the desired signal _{f d (= f t c xo} + f d or f _TCXO -f _d) passing only one of the mixed signals. In the mixer 46,
The output signal f _vco from the VCO 44 is supplied to the mixer 61 in the preceding stage.
And mixed with the signal f _d (= f _tcxo + f _d or f _tcxo −f _d ) which has been mixed by the band pass filter (BPF) 62 (f _vco ± (f _tcxo ± f _d )), (BPF) 47.

Here, in the second embodiment, since the frequency conversion is performed with the change amount f _d , the band pass filter (BP
F) The pass band of 47 must be small, and the pass band must be controlled for each set frequency, but according to the present embodiment, the mixer 6 is mixed before the mixing by the mixer 46.
By mixing (f _tcxo ± f _d ) by 1, the pass band of the band pass filter (BPF) 47 can be increased, and depending on the setting range, the control of the band pass filter (BPF) 47 is unnecessary. In some cases

Fourth Embodiment FIG. 4 is a diagram showing a fourth embodiment of the present invention, which is a modification of the second embodiment. In describing the present embodiment, the second
The same components as those in the embodiment are designated by the same reference numerals, and the description of the overlapping portions will be omitted.

First, the structure will be described. FIG. 4 is a block diagram of the PLL frequency synthesizer circuit. The PLL frequency synthesizer circuit 70 includes an original signal oscillator 21 and a reference frequency divider 4.
1, phase comparator (PD) 42, loop filter (LP
F) 43, VCO (voltage controlled oscillator) 44, frequency divider 4
5, the comparison frequency dividers 71 and 72, the mixer 73, the bandpass filter (BPF) 74, and the CPU 75. The comparison frequency divider 71 _divides the original frequency signal f _tcxo of the original signal oscillator 21 by X by the frequency divider 45 to _generate a signal f _d (= f _tcxo).
/ X) is divided by N, and a signal (f _d / N) divided by N is output to the mixer 73. The comparison frequency divider 72 divides the output signal f _vco from the VCO 44 by N and divides it by N (f _vco /
N) is output to the mixer 73. Mixer 73 is VCO4
The signal (f _vco / N) obtained by _dividing the output signal f _{vco of} 4 by N is
The original frequency signal f _tcxo of the original signal oscillator 21 is mixed with a signal (f _d / N) _obtained by _dividing by X and N ((f _vco ± f _d ) /
N)

The band pass filter (BPF) 74 is a desired signal ((f
_vco + f _d) / N or _{(f vco -f d) / N} ) to pass only. The CPU 75 has the reference frequency divider 41 and the frequency divider 4 described above.
5, the control signals are output to the comparison frequency dividers 71 and 72 and the bandpass filter (BPF) 74 to control each unit so as to obtain a predetermined synthesizer output. The mixer 73,
The bandpass filter (BPF) 74 constitutes frequency conversion means for converting the frequency.

In the above configuration, the original frequency signal f _tcxo oscillated by the original signal oscillator 21 is input to the reference frequency divider 41 and the frequency divider 45, and in the frequency divider 45, the original frequency signal from the original signal oscillator 21. The f _tcxo is frequency- _divided by X, and the X-frequency- _divided signal f _d (= f _tcxo / X) is input to the comparison frequency divider 71. In the comparison frequency divider 71, the X-divided signal f
_d (= f _tcxo / X) is further _divided by N, and the N- _divided signal (f _d / N) is output to the mixer 73.

On the other hand, the output signal f _vco from the VCO 44 is fed back to the comparison frequency divider 72, and the comparison frequency divider 72 divides the output signal f _vco from the VCO 44 by N to obtain N.
The frequency- _divided signal (f _vco / N) is output to the mixer 73. The mixer 73 outputs the output signal f _{vco of the} VCO 44 to N
A signal (f _vco / N) obtained by _dividing the original frequency signal f _tcxo of the original signal oscillator 21 by X and N (f _d
/ N) and mixed ((f _vco ± f _d ) / N) and output to the band pass filter (BPF) 74. The bandpass filter (BPF) 74 is a desired signal ((f _vco + f _d ) / N or (f _vco −f _d )) of the signals mixed by the mixer 73.
/ N), and outputs it to the phase comparator (PD) 42.

The above operation will be described in more detail with reference to specific numerical values. The prerequisite conditions are the same as in the case of the second embodiment. Now, the original frequency signal f _tcxo = 12 [MHz] from the original signal oscillator 21 is input, and the reference frequency divider 41 outputs the original frequency signal f _tcxo of the original signal oscillator 21 to R
= 40 frequency division, R frequency division reference frequency signal _fr = 300
The kHz is output to the phase comparator (PD) 42.

In the frequency divider 45, the original frequency signal f _tcxo = 12 [MHz] from the original signal oscillator 21 is X (= 240).
The frequency- _{divided and} X- _divided signal f _d (= f _tcxo / X = 50
[KHz]) is input to the comparison frequency divider 71. In the comparison frequency divider 71, the X- _divided signal f _d (= f _tcxo / X) is further _divided by N, and the N- _divided signal (0.05 / N).
[MHz]) is output to the mixer 73. On the other hand, VCO
The output signal f _vco from 44 is frequency- _divided by the comparison frequency divider 72, and the frequency- _divided signal (f _vco / N [MH
z]) is output to the mixer 73.

In the mixer 73, the output signal f of the VCO 44
The N-dividing the signal _{f r '(= f vc o} / N) of the _vco, mixed with the original frequency signal f _TCXO of the original signal oscillator 21 X division and N divider signal (0.05 / N) ( (F _vco ± 0.0
5) / N) and the mixed ((f _vco ± 0.05) / N) signal is output to the bandpass filter (BPF) 74. The bandpass filter (BPF) 74 is the mixer 7
Of the signals mixed in 3, for example, the lower bandpass signal f
_It passes _t4 ((f _vco −0.05) / N) and outputs it to the phase comparator (PD) 42. Phase comparator (PD) 42
Is the reference frequency signal f _r = R divided by the reference frequency divider 41.
300 [kHz] and band pass filter (BPF) 74
Phase comparison with the comparison signal f _t4 (= 300 [kHz]) output from the loop filter (LP
F) Output to 43. Therefore, the frequency that can be set by the PLL frequency synthesizer circuit 70 is fr = f _t4 , and therefore f _vco = f _r × N + f _d , and f _tcxo = 12.
The frequency that can be set when [MHz], R = 40, and X = 240 is 0.3 [MHz] × N + 0.05 [MHz].

Taking the case of 1 channel as an example (the same applies to other channels), 1895.15 = 0.3 × N + 0.
Therefore, the target frequency f _vco can be set because N = 6317 and N is an integer. That is, the frequency set value that is N times (f _r × N) of the original frequency signal f _r becomes f
_The frequency _d (= f _tcxo / X) can be changed, and the same effect as the second embodiment can be obtained.

Fifth Embodiment FIGS. 5 to 7 are views showing a fifth embodiment of the present invention. This embodiment is an example in which the present invention is applied to a digital cordless portable telephone device. That is, each of the above-described embodiments mainly uses the PLL frequency synthesizer circuit of the present invention as the transmission channel c.
This fifth embodiment is an example in which the PLL frequency synthesizer circuit is used for both the transmission / reception system (particularly, the local oscillator) of the digital cordless mobile phone device.

This digital cordless portable telephone device adopts a multi-carrier TDMA-TDD communication system and a .pi. / 4 shift QPSK system as a modulation system. At the time of reception, it is 15 from 1.9 GHz by a two-stage mixer.
The frequency is converted to 0 to 250 MHz and further to 10 MHz for demodulation, and at the time of transmission, the frequency is simultaneously converted to 1.9 GHz by the direct modulation method. The frequency between these multi-carriers (between channels) is 300 KHz, and the frequency of this carrier is an integral multiple of the frequency of the channel interval (for example, 1895.15 MH).
z). First, the configuration of the PLL frequency synthesizer circuit will be described. FIG. 5 is a block diagram of a PLL frequency synthesizer circuit. In FIG. 5, a PLL frequency synthesizer circuit 100 includes an original signal oscillator 101, a reference frequency divider 102,
Phase comparator (PD) 103, loop filter (LPF)
104, VCO (voltage controlled oscillator) 105, comparison frequency divider 106, mixer 107, bandpass filter (BPF)
108, a switch circuit 109, a frequency conversion signal oscillator 110, and a CPU 111.

The reference frequency divider 102 divides the original frequency signal f _tcxo of the original signal oscillator 21 by R and divides the reference frequency signal f _r (= f _tcxo / R) by R into the phase comparator (PD) 103.
Output to. Here, f _r corresponds to the channel interval. The phase comparator (PD) 103 is the original signal oscillator 10
The reference frequency signal f _r (= f _tcxo / R) _obtained by _dividing the original frequency signal f _tcxo of 1 by the reference frequency divider 102 by R and the signal of the band pass filter (BPF) 108 by the comparison frequency divider 106. The phase of the comparison signal f _r 'compared is compared and the error signal is output to the low pass filter (LPF) 104.

The low-pass filter (LPF) 104 integrates the error signal from the phase comparator (PD) 103 to remove the high frequency component and converts it into an error voltage, which is VC.
Add to the control terminal of O105. The VCO 105 receives fr from the error voltage from the low pass filter (LPF) 104.
= F _r ′, and the output signal f _vco outputs to the mixer 107 a frequency signal kept constant as the channel frequency at the time of transmission or the first local oscillation frequency at the time of reception.

On the other hand, the frequency conversion signal oscillator 110 is for generating a second local oscillation frequency, for example, a PLL.
When setting the frequency of the channel ch in the frequency synthesizer circuit, if the channel interval is 300 kHz and the fractional part thereof is 50 kHz (at the time of transmission) as in the above, the frequency conversion signal oscillator 110 has the following fractional part. A signal f _2nd (for example, 229.25 [MHz]) that absorbs a frequency that is an odd multiple of minutes (50 kHz) is generated. f _2nd = 229.25 [MHz] = (300 [kHz] × N) +50 [kHz] Note that the difference between the output frequencies during transmission and reception is 240.0.
It is 5 [MHz]. Therefore, for example, the output frequency at the time of transmission is 1895.15 [MHz] = (300
[KHz] × N) +50 [kHz] = (300 [kH
z] × 6317) +50 [kHz], the output frequency at the time of reception is 1655.1 [MHz] = (300 [kH
z] × N) = (300 [kHz] × 5517).
Here, if f _2nd is the frequency at the time of transmission and at the time of reception,
It is not necessary to switch the frequency division ratio N of the comparison frequency divider 106 between transmission and reception. However, this f _2nd is set to 229.25 because the two stages of the reception side of the high frequency part of the cordless mobile telephone device described later are used. This is for use with the local oscillation frequency of the eye. The switch circuit 109 is turned on / off based on a control signal from the CPU 111, and controls the supply of the output signal f _2nd of the frequency conversion signal oscillator 110 to the mixer 107 (that is, the passage of the signal f _2nd is turned on / off). ).
Specifically, the switch circuit 109 is turned on at the time of transmission to supply the signal f _2nd to the mixer 107, and turned off at the time of reception to stop the supply of the signal f _2nd .

The mixer 107 transmits the VCO 105 during transmission.
From the output signal f _vco of the frequency conversion signal oscillator 110 supplied via the switch circuit 109.
_The signals are mixed (f _vco ± f _2nd ) in the _2nd and output to the bandpass filter (BPF) 108, and at the time of reception, the output signal f _vco from the VCO 105 is passed as it is and output to the bandpass filter (BPF) 108. A band pass filter (BPF) 108 passes a signal in a predetermined frequency band (for example, a signal in the 1600 [MHz] band), and is a desired signal (f _vco − at the time of transmission) among the signals frequency-converted by the mixer 107. f _2nd , only f _vco signal at reception) is passed. The comparison frequency divider 106 uses the signal (for example, f _vco −f _2nd ) from the band pass filter (BPF) 108.
Or f _vco) and N divides, N divider signal _{(e.g., (f v c o -f 2nd} ) and outputs the / N or f _vco / N) phase comparator (PD) 103. In this case, the frequency division ratio is N = 5553 during transmission and N = 551 during reception.
Set to 7.

The CPU 111 outputs a control signal to the comparison frequency divider 106 and the switch circuit 109 to control each section so as to obtain a predetermined synthesizer output. That is, the CPU 111 causes the comparison frequency divider 106 to divide the frequency by the frequency division ratio N.
A channel is set on the basis of the above, and as the value of N, for example, N = 5553 is set at the time of transmission, N = 5517 is set at the time of reception, and the switch circuit 109 is set by the transmission / reception.
To control the supply of the output signal f _2nd of the frequency conversion signal oscillator 110 to the mixer 107. The mixer 107, the bandpass filter (B
The PF) 108, the frequency conversion signal oscillator 110, and the switch circuit 109 output the output signal f from the VCO 105.
A frequency conversion means for frequency converting _vco is configured.

Next, the operation of the PLL frequency synthesizer circuit of the fifth embodiment will be described. First, the CPU 111 sets the comparison frequency divider 106 and the switch circuit 109. For example, a control signal that turns on during transmission and turns off during reception is output to the switch circuit 109. Original signal oscillator original frequency signal oscillated by 101 f _TCXO is input to the reference divider 102, a reference frequency divider 102 is the original frequency signal ft _CXO from the original signal oscillator 101 in response to the R divider (channel spacing min peripheral) is, the reference frequency signal _{f r (= f t c xo} / R) is outputted to the phase comparator (PD) 103. For example, f _r = 300k
It becomes Hz.

In the phase comparator (PD) 103, the original frequency signal f _tcxo of the original signal oscillator 101 is _converted into R by the reference frequency divider 102.
Dividing the reference frequency signal _{f r (= f tcxo / R} ) and a band pass filter (BPF) 108 signal comparison frequency divider 10
6, the phase is compared with the comparison signal f _r ' _divided by N,
The error signal is output to the low pass filter (LPF) 104. When the error signal becomes 0, f _r '≈ 300 kHz
z. In the low pass filter (LPF) 104, the error signal from the phase comparator (PD) 103 is integrated to remove the high frequency component and converted into an error voltage, which is then applied to the control terminal of the VCO 105. Then VC
In O105, operation such that f _r = f _r 'is performed due to the error voltage from the low pass filter (LPF) 104,
The frequency signal f _vco is output to the mixer 107.

A. At the time of transmission Here, at the time of transmission, the channel ch is 1 ch = 1895.
Taking the case of 15 [MHz] as an example, the VCO 105 outputs a frequency signal of f _vco = 189.15 [MHz] to the mixer 107. At this time, the frequency conversion signal oscillator 110 generates a signal f _2nd = 229.25 [MHz] that absorbs a fractional frequency (50 kHz) of the set frequency of the channel ch as the second local oscillation frequency. At this time, the switch circuit 109 is turned on at the time of transmission, and the signal f _2nd = 229.25 [MH
z] is supplied to the mixer 107 via the switch circuit 109, and the mixer 107 outputs the output signal f from the VCO 44.
_vco = 1895.15 [MHz] is f _2nd = 229.25
Mixed with [MHz], 1895.15 ± 229.25
The signal of [MHz] is a band pass filter (BPF) 10
8 is output.

Since the bandpass filter (BPF) 108 can pass only the signal in the 1600 [MHz] band, the desired signal (f _vco
−f ₂ n _d ) = 1895.15−229.25 = 166
5.9 [MHz] is output to the comparison frequency divider 106. The comparison frequency divider 106 includes a bandpass filter (BPF) 10
Signal 1665.9 [MHz] from 8 is N (for example, N
= 5553), and the frequency-divided signal f _r '(166
5.9 / 5555) ≈ 300 kHz is the phase comparator (P
D) is output to 103. As a result, the phase comparator (P
D) In 103, the original frequency signal f _tcxo is _applied to the reference frequency divider 102.
Reference frequency signal f _r (= f _tcxo / R) = 3 _{divided by} R
00 kHz and the comparison signal f _r '≈300 kHz obtained by dividing the signal of the band pass filter (BPF) 108 by the comparison frequency divider 106 by N are phase-compared, and the error signal is output to the low pass filter (LPF) 104. Therefore, in the end, the VCO 105 has a low-pass filter (LP
F) The error voltage from 104 causes operation such that f _r = f _r ', and the frequency of 1ch during transmission is 18
It is kept at 95.15 [MHz].

B. During reception Since the local oscillation frequency for reception is an integral multiple of the reference signal during reception, the fractional frequency (50 KHz) is not absorbed as in the above-described transmission, and the frequency is directly divided by the comparison frequency divider 106. Therefore, in the VCO 105, f _vco = 1655.1
A frequency signal of [MHz] is output to the mixer 107. At this time, the switch circuit 109 is turned off during reception, and the signal f _2nd = 229.25 [MHz] is supplied to the mixer 107 via the switch circuit 109. Disappear. Therefore, the output signal fv _co = 165 from the VCO 44
The 5.1 [MHz] passes through the mixer 107 as it is, and is output to the band pass filter (BPF) 108.

Since the band-pass filter (BPF) 108 can pass only the signal in the 1600 [MHz] band, the output signal 1655.1 [MHz] of the mixer 107 directly passes through the band-pass filter (BPF) 108. It is output to the comparison frequency divider 106. In the comparison frequency divider 106, the signal 1655. from the band pass filter (BPF) 108.
1 [MHz] is divided by N (for example, N = 5517),
Signal f divided by N f _r '(1655.1 / 5517) ≈3
00 kHz is output to the phase comparator (PD) 103.
As a result, in the phase comparator (PD) 103, the reference frequency signal f _r (= f _tcxo / R) = 300 kHz _obtained by _{dividing the} original frequency signal f _tcxo by R by the reference frequency divider 102, and the band pass filter (BPF) 108. Is compared with the comparison signal f _r '≈300 kHz, which is obtained by frequency-dividing the signal of N by the comparison frequency divider 106, and the error signal thereof is a low-pass filter (LPF).
By being output to 104, the VCO 105 eventually operates such that f _r = f _r ′ due to the error voltage from the low-pass filter (LPF) 104, and the local oscillation frequency during reception is 1655.1 [MHz. ]].

As described above, the PLL frequency synthesizer circuit of this embodiment can be used as the same local oscillation circuit at the time of transmission / reception while obtaining the same effect as that of the above-mentioned embodiment. That is, at the time of transmission that is not an integral multiple of the reference frequency, the CPU 111 controls the switch circuit 109 to input a signal of a fractional frequency to the frequency conversion circuit, and VCO1
The reference frequency is set to the frequency of the channel interval by absorbing the output of 05 into a frequency corresponding to a fraction. On the other hand, when receiving a signal that is an integral multiple of the reference frequency, VC
The output of O105 is not frequency-converted, and the reference frequency becomes the same frequency as the channel interval during both transmission and reception. In particular, when the modulation method is the direct modulation method, the local oscillator must output the transmission frequency (channel frequency) at the time of transmission. Therefore, if the comparison frequency is an integer, the reference frequency is 5
Since it becomes 0 kHz, it is difficult to obtain characteristics such as high-speed lockup and low spurious. However, with the configuration according to the present embodiment, the channel frequency that is not an integral multiple of the channel interval (reference frequency) Also in the above, it is possible to realize a PLL frequency synthesizer circuit capable of setting the reference frequency to the frequency of the channel interval by frequency converting the output of the VCO 105.

Next, a specific example of a digital cordless portable telephone device incorporating one PLL frequency synthesizer circuit for switching the local oscillation frequency between transmission and reception as in this embodiment will be described. FIG. 6 is a diagram showing a configuration of a high frequency part of the digital cordless mobile phone device, and FIG. 7 is a diagram showing a configuration of a signal processing part of the digital cordless mobile phone device. Referring to FIG. 6, the receiving system will be described first. A transmission / reception radio frequency (RF) in the 1.9 GHz band from the antenna 201 is a bandpass filter (BPF) 202.
Then, the signal is distributed to the receiving side by the antenna switch 203 which distributes the transmission / reception, and amplified by the high frequency amplifier (RF / AMP) 204.
IX) 205. In the first mixer 205, the signal amplified by the high frequency amplifier 204 is transferred to the buffer amplifier 2
06 is mixed with the output signal from the PLL frequency synthesizer circuit 207 supplied via 06, and frequency-converted into a first intermediate frequency signal (first IF signal: 250 MHz band),
The first intermediate frequency signal is output to the first intermediate frequency amplifier 208 and amplified. In this case, the PLL frequency synthesizer circuit 207 uses the communication control microcomputer 27 shown in FIG.
8 and operates as a first local oscillator for selection at the time of reception. For example, in the case of 1ch, 1655.1
A local oscillation signal having a frequency of [MHz] is output to the first mixer 205 via the buffer amplifier 206.

The first intermediate frequency signal amplified by the first intermediate frequency amplifier 208 is a bandpass filter (BPF) 20.
After passing through 9, it is supplied to the second mixer (second MIX) 210. The second mixer 210 mixes with the local oscillation signal from the frequency conversion signal oscillator 110 of the PLL frequency synthesizer circuit 207 and mixes it with the second intermediate frequency signal (second I2).
(F signal: 10.7 MHz band), the second intermediate frequency signal is output to the second intermediate frequency amplifier 212 and amplified. The second amplified by the second intermediate frequency amplifier 212
The intermediate frequency signal is a band pass filter (BPF) 213.
Then, the signal is supplied to a quadrature demodulator 214, demodulated into an analog signal, separated into an I signal and a Q signal, and output to a modem block 261 (see FIG. 7) described later.

Next, the transmission system will be described. The I signal and Q signal from the modem block 261 (see FIG. 7) are input to the quadrature modulator 251 and are supplied via the buffer amplifier 254 to the PLL frequency synthesizer circuit 207. Digital modulation (for example, π /
The frequency is converted into a transmission / reception radio frequency (RF: 1.9 GHz) and amplified by the drive amplifier 256. In this case, PL
The L frequency synthesizer circuit 207 is controlled by the communication control microcomputer 278 shown in FIG.
A local oscillation signal having a frequency of 15 [MHz] is output to the mixer 253 via the buffer amplifier 254. Next, the output of the drive amplifier 256 is the power amplifier 257.
After the power is amplified by the communication control microcomputer 278, the antenna switch 203 is switched to the transmission side, and after passing through the band pass filter (BPF) 202,
It is emitted from the antenna 201 into the air.

Next, the configuration of the signal processing unit of the digital cordless portable telephone device will be described with reference to FIG. In FIG. 7, reference numeral 261 denotes a modem block, which transmits the separated IQ data from the quadrature demodulator 214 to the TDMA signal processing unit 266, which will be described later, as a data string on the receiving side and the TDMA signal processing unit 266 on the transmitting side. IQ data is created from the received data, modulated by π / 4 shift QPSK, and output. That is, at the time of reception, the demodulated I signal and Q signal supplied from the quadrature demodulator 214 are fetched, and the respective signals are A / D converters 262, 26.
A / D conversion is performed at 3 and a synchronous clock is extracted at a clock extractor 264, a demodulated signal is detected by a wave detector 265 based on the synchronous clock and converted into an audio signal, and output to a TDMA signal processing unit 266. . Further, at the time of transmission, the TDM signal output from the TDMA signal processing unit 266 is output.
The A-processed audio signal is digitally modulated by the modulator 267, D / A-converted by the D / A converters 268 and 269, and the quadrature modulator 2 is used as an I signal and a Q signal, respectively.
Output to 51.

The TDMA signal processing unit 266 divides the radio frequency into time and transmits a transmission / reception signal in a burst in a specific time zone.
Time division multiple access) processing is performed. The TDMA signal processing unit 266 is connected to the speech codec 270, and the speech codec 270 performs compression / expansion processing of the digital audio signal. Specifically, on the receiving side, the ADPCM audio signal (4
bit × 8 kHz = 32 kbps is a PCM audio signal (8
bit × 8 kHz = 64 kbps) to expand and output to the PCM codec 271, and the transmitting side encodes the PCM audio signal sent from the PCM codec 271 into an ADPCM audio signal and compresses it. Output to the TDMA signal processing unit 266

The speech codec 270 is connected to the PCM codec 271 and the PCM codec 271 performs analog / digital conversion processing. Specifically, D / A
The converter 272 converts the PCM audio signal input from the speech codec 270 into an analog signal, and the amplifier 2
A / D converter 277 A / D-converts an analog audio signal input by a transmitter (microphone, etc.) 275 and amplified by an amplifier 276 while performing processing for output to a receiver (speaker, etc.) 274 via 73. Then, a process of encoding and outputting a PCM digital signal (PCM audio signal) is performed. The handset 274 and the transmitter 275 are configured, for example, as a handset, which is connected and integrated via a grip portion. In addition to this, a ringer section for ringing the ringer is provided.

A communication control microcomputer 278 controls the entire apparatus in accordance with a predetermined protocol.
It is composed of U, ROM, RAM and the like. The communication control microcomputer 278 is a digital cordless mobile phone including a control process for the PLL frequency synthesizer circuit 207 described above using a RAM that temporarily stores data and calculation results according to a microprogram stored in an internal ROM. Controls various operations of the device. Further, the communication control microcomputer 278 takes in operation information from the keyboard 280 via the man-machine interface microcomputer 279, and displays it on the display unit 281 including an LCD for displaying the caller number, time, call time, call charge, and the like. Output the necessary data to it. The keyboard 280 has a predetermined key matrix and is provided with, for example, a numeric keypad and various function keys.

As described above, when the PLL frequency synthesizer circuit 207 of the present invention is incorporated in the digital cordless portable telephone device, the PLL frequency synthesizer circuit 20 is used.
Even if 7 is different in local oscillation frequency between transmission and reception, the switching operation can be performed. That is, even at a channel (carrier) frequency which is not an integral multiple of the channel interval (reference frequency) by one PLL frequency synthesizer circuit 297, the reference frequency is absorbed by absorbing the fractional frequency of the output of the PLL frequency synthesizer circuit 207. Can be the frequency of the channel spacing.

In each of the above-described embodiments, the signal input to the phase comparator is frequency-converted, but any signal conversion means for frequency-converting the signal input to the phase comparator may be used. Any configuration or conversion method may be used, and the type and number of each frequency divider, the control method, etc.
It goes without saying that anything can be used. Also,
In each of the above embodiments, the crystal oscillator is used as the original signal oscillator, but it is needless to say that the crystal oscillator is not limited to the crystal oscillator as long as it can oscillate an accurate signal. Furthermore, in the third embodiment, the second
Although f _d is mixed with f _tcxo in order to increase the pass band of the band pass filter (BPF) 47 of the embodiment, this embodiment is not _limited to the second embodiment, and other embodiments (first embodiment and It can also be applied to the fourth embodiment).

[0082]

According to the present invention, the original frequency signals f _r of N
It is possible to obtain a signal with a constant oscillation frequency even at a frequency other than double (f _r × N).

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a first embodiment of a PLL frequency synthesizer circuit according to the present invention.

FIG. 2 is a circuit configuration diagram of a second embodiment of a PLL frequency synthesizer circuit according to the present invention.

FIG. 3 is a circuit configuration diagram of a third embodiment of a PLL frequency synthesizer circuit according to the present invention.

FIG. 4 is a circuit configuration diagram of a fourth embodiment of a PLL frequency synthesizer circuit according to the present invention.

FIG. 5 is a circuit configuration diagram of a fifth embodiment of a PLL frequency synthesizer circuit according to the present invention.

FIG. 6 is a configuration diagram of a mobile phone device using the PLL frequency synthesizer circuit of the embodiment.

FIG. 7 is a configuration diagram of a mobile phone device using the PLL frequency synthesizer circuit of the embodiment.

FIG. 8 is a circuit configuration diagram of a conventional PLL frequency synthesizer circuit.

[Explanation of symbols]

20, 40, 60, 100 PLL frequency synthesizer circuit 21, 101 Original signal oscillator 22, 41, 102 Reference frequency divider 23, 46, 61, 73, 107 Mixer 24, 47, 62, 74, 108 Bandpass filter ( BPF) 25, 42, 103 Phase comparator (PD) 26, 43, 104 Low pass filter (LPF) 27, 44, 105 VCO (voltage controlled oscillator) 28, 45 Divider 29, 30, 48, 71, 72, 106 comparison frequency divider 31, 49, 63, 75, 111 CPU 207 PLL frequency synthesizer circuit 278 communication control microcomputer

Claims (6)

[Claims] 1. A reference signal generator for outputting a reference frequency signal, frequency conversion means for frequency-converting the reference frequency signal output by the reference signal generator, and a voltage for outputting a signal having a different frequency according to an applied voltage. A controlled oscillator, a frequency divider that divides a predetermined frequency signal output from the voltage controlled oscillator, a phase-divided signal of the frequency divider and a frequency-converted reference frequency signal output from the frequency conversion means. Compare
A phase filter for outputting an error signal of the phase; and a loop filter for converting the error signal output by the phase comparator into a voltage signal and outputting it as an oscillation control voltage to the voltage controlled oscillator. And a PLL frequency synthesizer circuit. 2. A reference signal generator for outputting a reference frequency signal, a voltage controlled oscillator for outputting a signal having a different frequency according to an applied voltage, and a frequency conversion for frequency converting a predetermined frequency signal output by the voltage controlled oscillator. Means, a frequency divider for dividing the frequency-converted signal by the frequency converting means, and a phase comparison between the frequency-divided signal by the frequency divider and the reference frequency signal output by the reference signal generator. And a loop filter that converts the error signal output by the phase comparator into a voltage signal and outputs the voltage signal as an oscillation control voltage to the voltage controlled oscillator. PLL frequency synthesizer circuit. 3. A reference signal generator which outputs a reference frequency signal, a voltage controlled oscillator which outputs a signal having a different frequency according to an applied voltage, and a frequency divider which divides a predetermined frequency signal output by the voltage controlled oscillator. A frequency converter for frequency-converting the frequency-divided signal by the frequency divider, a frequency-converted signal by the frequency converter and a reference frequency signal output by the reference signal generator for phase comparison, And a loop filter that converts the error signal output by the phase comparator into a voltage signal and outputs the voltage signal as an oscillation control voltage to the voltage controlled oscillator. PLL frequency synthesizer circuit. 4. The frequency converter according to claim 1, wherein the frequency converter has a frequency converter that performs frequency conversion based on a reference frequency signal output from the reference signal generator. A PLL frequency synthesizer circuit according to any one of the claims. 5. The frequency conversion means includes first frequency conversion means for performing frequency conversion based on a reference frequency signal output from the reference signal generator, and a signal frequency-converted by the first frequency conversion means. 4. The PL according to claim 1, further comprising a second frequency conversion unit that performs frequency conversion with the reference frequency signal output from the reference signal oscillator.
L frequency synthesizer circuit. 6. The frequency conversion means has a bandpass filter that passes a signal in a predetermined band of the frequency-converted signals, claim 1, claim 2, claim 3, claim 4, or. The PLL according to claim 5.
Frequency synthesizer circuit.